[all-commits] [llvm/llvm-project] 0be51c: [RISCV] Add ISel patterns for Qualcomm uC Xqcicli ...

[quic_hchandel via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0be51cff91293eb0f4ee11088d4d9edade590b48
      https://github.com/llvm/llvm-project/commit/0be51cff91293eb0f4ee11088d4d9edade590b48
  Author: quic_hchandel <quic_hchandel at quicinc.com>
  Date:   2025-07-15 (Tue, 15 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    A llvm/test/CodeGen/RISCV/xqcicli.ll

  Log Message:
  -----------
  [RISCV] Add ISel patterns for Qualcomm uC Xqcicli extension (#148121)

Add CodeGen patterns for conditional load immediate instructions



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