[all-commits] [llvm/llvm-project] 31944a: [RISCV] Render P-ext simm10_unsigned as a simm10 a...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 31944ac45bb986122da639f195b19df4621fbfa8
      https://github.com/llvm/llvm-project/commit/31944ac45bb986122da639f195b19df4621fbfa8
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-07-14 (Mon, 14 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
    M llvm/test/MC/RISCV/rv32p-valid.s
    M llvm/test/MC/RISCV/rv64p-valid.s

  Log Message:
  -----------
  [RISCV] Render P-ext simm10_unsigned as a simm10 after parsing. (#148749)

Instead of allowing a parsed MCInst to have a either uimm10 or simm10,
always render as simm10. This avoids a mismatch between parsed MCInst
and disassembled MCInst when a uimm10 value is used.



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