[all-commits] [llvm/llvm-project] 085e8f: [RISCV] Relax destination instruction dag operand ...

[Sudharsan Veeravalli via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 085e8f1e520b91f5ed40e5b09f458bb2c4d7c0e0
      https://github.com/llvm/llvm-project/commit/085e8f1e520b91f5ed40e5b09f458bb2c4d7c0e0
  Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
  Date:   2025-07-15 (Tue, 15 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    M llvm/test/MC/RISCV/xqcilia-valid.s
    M llvm/utils/TableGen/CompressInstEmitter.cpp

  Log Message:
  -----------
  [RISCV] Relax destination instruction dag operand matching in CompresInstEmitter (#148660)

We have some 48-bit instructions in the `Xqci` spec that currently
cannot be compressed to their 32-bit variants due to the constraint in
`CompressInstEmitter` on destination instruction operands not being
allowed to mismatch with the DAG operands.

For eg. the` QC_E_ADDI` instruction can be compressed to the `ADDI`
instruction when the immediate is signed-12 bit but this is currently
not possible since the `QC_E_ADDI` instruction has `GPRNoX0` register
operands while the `ADDI` instruction has `GPR` register operands
leading to an operand type validation error.

I think we can remove the check that only source instruction operands
can mismatch with the corresponding DAG operands and rely on the fact
that we check if the DAG register operand type is a subclass of the
instruction register operand type.



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