[all-commits] [llvm/llvm-project] df3876: [RISCV] Remove -riscv-v-vector-bits-min from LoopV...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: df387661c4ab53938ea73cbd77a44f98c8f96083
      https://github.com/llvm/llvm-project/commit/df387661c4ab53938ea73cbd77a44f98c8f96083
  Author: Luke Lau <luke at igalia.com>
  Date:   2025-07-14 (Mon, 14 Jul 2025)

  Changed paths:
    M llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/low-trip-count.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/riscv-interleaved.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/riscv-unroll.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse-output.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/safe-dep-distance.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/scalable-basics.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/scalable-reductions.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/unroll-in-loop-vectorizer.ll

  Log Message:
  -----------
  [RISCV] Remove -riscv-v-vector-bits-min from LoopVectorize tests. NFC (#148565)

If I understand correctly there was a point where we used to need this
before it was implied by Zvl*b.

Now that it is though and we use -mattr=+v in pretty much every test we
can remove it.

In unroll-in-loop-vectorizer.ll we can force a VF of 1 instead by using
-force-vector-width=1, and in scalable-basics.ll the two RUN lines were
the same so I merged them.



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