[all-commits] [llvm/llvm-project] 0ae150: [RISCV] Add ISel patterns for Xqciac QC_SHLADD ins...

[Sudharsan Veeravalli via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0ae1506847ee9516630fe08f74d0db516eeaa993
      https://github.com/llvm/llvm-project/commit/0ae1506847ee9516630fe08f74d0db516eeaa993
  Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
  Date:   2025-07-14 (Mon, 14 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    M llvm/test/CodeGen/RISCV/xqciac.ll

  Log Message:
  -----------
  [RISCV] Add ISel patterns for Xqciac QC_SHLADD instruction (#148256)

Add a couple of patterns to generate the Xqciac QC_SHLADD shift left and
add immediate instruction.



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