[all-commits] [llvm/llvm-project] 1fdbe6: [NVPTX] support f32x2 instructions for sm_100+ (#...

[Princeton Ferro via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1fdbe6984976d9e85ab3b1a93e8de434a85c5646
      https://github.com/llvm/llvm-project/commit/1fdbe6984976d9e85ab3b1a93e8de434a85c5646
  Author: Princeton Ferro <pferro at nvidia.com>
  Date:   2025-07-11 (Fri, 11 Jul 2025)

  Changed paths:
    M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
    M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
    M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
    M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.td
    M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
    M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
    M llvm/lib/Target/NVPTX/NVPTXUtilities.h
    M llvm/test/CodeGen/NVPTX/aggregate-return.ll
    M llvm/test/CodeGen/NVPTX/bf16-instructions.ll
    M llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
    M llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
    A llvm/test/CodeGen/NVPTX/f32x2-instructions.ll
    A llvm/test/CodeGen/NVPTX/fp-contract-f32x2.ll
    M llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
    M llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
    M llvm/test/CodeGen/NVPTX/ldparam-v4.ll
    M llvm/test/CodeGen/NVPTX/load-store-256-addressing-invariant.ll
    M llvm/test/CodeGen/NVPTX/load-store-256-addressing.ll
    M llvm/test/CodeGen/NVPTX/load-store-vectors-256.ll
    M llvm/test/CodeGen/NVPTX/load-with-non-coherent-cache.ll
    M llvm/test/CodeGen/NVPTX/misaligned-vector-ldst.ll
    M llvm/test/CodeGen/NVPTX/read-global-variable-constant.ll
    M llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
    M llvm/test/CodeGen/NVPTX/vec-param-load.ll
    M llvm/test/CodeGen/NVPTX/vector-args.ll
    M llvm/test/CodeGen/NVPTX/vector-loads.ll
    M llvm/test/CodeGen/NVPTX/vector-stores.ll

  Log Message:
  -----------
   [NVPTX] support f32x2 instructions for sm_100+ (#126337)

Lower `fadd`, `fsub`, `fmul`, and `fma` to f32x2 variants introduced in
PTX 8.6 for sm_100+. Adds a new register class for v2f32 as a b64
register in PTX. This causes other vector operations like loads and
stores to lower as .b64 instead of .v2.b32 as appropriate.

Also update test cases to use the autogenerator.



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