[all-commits] [llvm/llvm-project] 6563c7: [RISCV] Handle implicit defs when ensuring pseudo ...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6563c795cd3f4fdfaba644897dada97be8f57e5b
      https://github.com/llvm/llvm-project/commit/6563c795cd3f4fdfaba644897dada97be8f57e5b
  Author: Luke Lau <luke at igalia.com>
  Date:   2025-07-12 (Sat, 12 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
    M llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir

  Log Message:
  -----------
  [RISCV] Handle implicit defs when ensuring pseudo dominates in peephole (#148181)

Previously we just assumed that no instruction that needed to be moved
would have an implicit def, but vnclip pseudos will.

We can still try to move them but we just need to check that no
instructions between have any reads or writes to the physical register.

Fixes #147986



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