[all-commits] [llvm/llvm-project] 9de657: [RISCV] Add ISel patterns for Xqciac QC.MULIADD in...

[Sudharsan Veeravalli via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9de657abaf3d60918cb10edbbada3c4b520b0b0c
      https://github.com/llvm/llvm-project/commit/9de657abaf3d60918cb10edbbada3c4b520b0b0c
  Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
  Date:   2025-07-11 (Fri, 11 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    A llvm/test/CodeGen/RISCV/xqciac.ll

  Log Message:
  -----------
  [RISCV] Add ISel patterns for Xqciac QC.MULIADD instruction (#147661)

Add basic isel patterns for the multiple accumulate QC.MULIADD
instruction.

While most case work with just the TD file pattern, there are few cases
which need to be handled in ISelLowering depending on the immediate we
are multiplying with:

- imm + 1 , imm - 1, 1 - imm, -1 - imm are a power of 2 --> these become
slli and add/sub
- immediate is 2^n - 2 ^m --> this becomes (add/sub (shl X, C1), (shl X,
C2))
- imm - 2, imm - 4, imm - 6 is a power of 2 --> these use shxadd when
zba is enabled

The patch does not decompose mul if Xqciac is present, for the above
conditions. There could be cases where this may not beneficial which I
plan to address in follow up patches.



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