[all-commits] [llvm/llvm-project] 66969c: [RISCV] Add ISel patterns for Qualcomm uC Xqcics e...

[quic_hchandel via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 66969c9494c39d0bd5e09a6f4aca1e9327c5b108
      https://github.com/llvm/llvm-project/commit/66969c9494c39d0bd5e09a6f4aca1e9327c5b108
  Author: quic_hchandel <quic_hchandel at quicinc.com>
  Date:   2025-07-11 (Fri, 11 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    M llvm/test/CodeGen/RISCV/select-cond.ll
    A llvm/test/CodeGen/RISCV/xqcics.ll

  Log Message:
  -----------
  [RISCV] Add ISel patterns for Qualcomm uC Xqcics extension (#146675)

Add CodeGen support for conditional select instructions in this
extension



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