[all-commits] [llvm/llvm-project] c0b82d: [MachinePipeliner] Add validation for missed loop-...

[Ryotaro Kasuga via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c0b82df5f3484870d3728156da7d7e3720ef53ad
      https://github.com/llvm/llvm-project/commit/c0b82df5f3484870d3728156da7d7e3720ef53ad
  Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
  Date:   2025-07-11 (Fri, 11 Jul 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/MachinePipeliner.h
    M llvm/lib/CodeGen/MachinePipeliner.cpp
    M llvm/test/CodeGen/Hexagon/swp-loop-carried-order-dep1.mir
    M llvm/test/CodeGen/Hexagon/swp-loop-carried-order-dep2.mir
    M llvm/test/CodeGen/Hexagon/swp-loop-carried-order-dep3.mir
    M llvm/test/CodeGen/Hexagon/swp-loop-carried-order-dep4.mir
    M llvm/test/CodeGen/Hexagon/swp-loop-carried-order-dep5.mir

  Log Message:
  -----------
  [MachinePipeliner] Add validation for missed loop-carried memory deps (#145878)

This patch adds an additional validation step to ensure that the
generated schedule does not violate loop-carried memory dependencies.
Prior to this patch, incorrect schedules could be produced due to the
lack of checks for the following types of dependencies:

- load-to-store backward (from bottom to top within the BB) dependencies
- store-to-load dependencies
- store-to-store dependencies

One possible solution to this issue is to add these dependencies
directly to the dependency graph, although doing so may lead to
performance degradation. In addition, no known cases of incorrect code
generation caused by these missing dependencies have been observed in
practice. Given these factors, this patch introduces a post-scheduling
validation phase to check for such previously missed dependencies,
instead of adding them to the graph before searching for a schedule.
Since no actual problems have been identified so far, it is likely that
most generated schedules are already valid. Therefore, this additional
validation is not expected to cause performance degradation in practice.

Split off from #135148 .

The remaining tasks are as follows:

- Address other missing loop-carried dependencies (e.g., output
dependencies between physical registers, barrier instructions, and
instructions that may raise floating-point exceptions)
- Remove code that are currently retained to maintain the existing
behavior but probably unnecessary.
- Eliminate `SwingSchedulerDAG::isLoopCarriedDep` and use
`SwingSchedulerDDG` to traverse edges after dependency analysis part.



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