[all-commits] [llvm/llvm-project] 27c9b5: [SPIRV] Add more id and range builtIns (#143909)
Krzysztof Parzyszek via All-commits
all-commits at lists.llvm.org
Thu Jul 10 06:07:03 PDT 2025
Branch: refs/heads/users/kparzysz/spr/v06-omp-future
Home: https://github.com/llvm/llvm-project
Commit: 27c9b55659c99fad4583fb6fa29dd079ea8b9582
https://github.com/llvm/llvm-project/commit/27c9b55659c99fad4583fb6fa29dd079ea8b9582
Author: Victor Lomuller <victor at codeplay.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsSPIRVCL.td
M clang/include/clang/Basic/BuiltinsSPIRVCommon.td
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/TargetBuiltins/SPIR.cpp
M clang/lib/Headers/__clang_spirv_builtins.h
M clang/test/CodeGenHLSL/semantics/DispatchThreadID.hlsl
M clang/test/CodeGenHLSL/semantics/SV_GroupID.hlsl
M clang/test/CodeGenHLSL/semantics/SV_GroupThreadID.hlsl
A clang/test/CodeGenSPIRV/Builtins/ids_and_ranges.c
A clang/test/Headers/spirv_ids.cpp
A clang/test/SemaSPIRV/BuiltIns/ids_and_ranges.c
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/IR/Intrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
A llvm/test/CodeGen/SPIRV/builtin_intrinsics_32.ll
A llvm/test/CodeGen/SPIRV/builtin_intrinsics_64.ll
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_DispatchThreadID.ll
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_GroupID.ll
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_GroupThreadID.ll
Log Message:
-----------
[SPIRV] Add more id and range builtIns (#143909)
The patch adds intrinsics and lowering logic for GlobalSize,
GlobalOffset, SubgroupMaxSize, NumWorkgroups, WorkgroupSize,
WorkgroupId, LocalInvocationId, GlobalInvocationId, SubgroupSize,
NumSubgroups, SubgroupId and SubgroupLocalInvocationId SPIR-V builtins.
The patch also extend spv_thread_id, spv_group_id and
spv_thread_id_in_group to return anyint rather than i32. This allows the
intrinsics to support the opencl environment.
For each of the intrinsics, new clang builtins were added as well as a
binding for the SPIR-V "friendly" format. The original format doesn't
define such binding (uses global variables) but it is not possible to
express the Input SC which is normally required by the environement
specs, and using builtin functions is the most usual approach for other
backend and programming models.
Commit: ab187bbd3a5c64451846aa3480f271a93dfba760
https://github.com/llvm/llvm-project/commit/ab187bbd3a5c64451846aa3480f271a93dfba760
Author: Andreas C. Osowski <andreas at osowski.de>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M clang/lib/AST/TypePrinter.cpp
A clang/test/AST/ast-print-cconv-preserve.cpp
M clang/test/Sema/preserve-call-conv.c
M clang/test/Sema/preserve-none-call-conv.c
M clang/test/SemaCXX/lambda-attributes.cpp
Log Message:
-----------
[clang][AST] Fix positioning of preserve cconv attributes in TypePrinter (#147285)
TypePrinter currently generates function pointer types that do not
compile when using the `preserve_.*` calling conventions as per
https://clang.llvm.org/docs/AttributeReference.html#preserve-all ff.
Running clang with `-Xclang -ast-print` on the following:
```cc
using IN1 = void (__attribute__((preserve_most)) *)();
using IN2 = __attribute__((preserve_most)) void (*) ();
```
outputs:
```cc
using IN1 = void (*)() __attribute__((preserve_most));
using IN2 = void ((*))() __attribute__((preserve_most));
```
However, this does not compile:
```cc
<source>:3:23: error: expected ';' after alias declaration
3 | using IN1 = void (*)() __attribute__((preserve_most));
```
This PR updates TypePrinter such that output is correct and compiles:
```cc
using IN1 = __attribute__((preserve_most)) void (*)();
using IN2 = __attribute__((preserve_most)) void ((*))();
```
I've verified via `-ast-dump` that the AST looks equivalent.
Commit: beea2a941470368a87b1816e455b1db366c1bbb9
https://github.com/llvm/llvm-project/commit/beea2a941470368a87b1816e455b1db366c1bbb9
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/TargetInfo.h
M clang/lib/AST/RecordLayoutBuilder.cpp
M clang/lib/Basic/TargetInfo.cpp
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/Basic/Targets/DirectX.h
M clang/lib/Basic/Targets/PPC.cpp
M clang/lib/Basic/Targets/PPC.h
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/Basic/Targets/WebAssembly.cpp
M clang/lib/Basic/Targets/WebAssembly.h
M clang/lib/Basic/Targets/X86.h
M clang/lib/Frontend/ASTUnit.cpp
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Interpreter/Interpreter.cpp
M clang/test/Layout/ms-x86-declspec-empty_bases.cpp
M clang/test/SemaCXX/ms-layout_version.cpp
M clang/tools/clang-import-test/clang-import-test.cpp
Log Message:
-----------
[Clang] Respect MS layout attributes during CUDA/HIP device compilation (#146620)
This patch fixes an issue where Microsoft-specific layout attributes,
such as __declspec(empty_bases), were ignored during CUDA/HIP device
compilation on a Windows host. This caused a critical memory layout
mismatch between host and device objects, breaking libraries that rely
on these attributes for ABI compatibility.
The fix introduces a centralized hasMicrosoftRecordLayout() check within
the TargetInfo class. This check is aware of the auxiliary (host) target
and is set during TargetInfo::adjust if the host uses a Microsoft ABI.
The empty_bases, layout_version, and msvc::no_unique_address attributes
now use this centralized flag, ensuring device code respects them and
maintains layout consistency with the host.
Fixes: https://github.com/llvm/llvm-project/issues/146047
Commit: 0740db9bc12672295bde72e7007f7837f7f632c0
https://github.com/llvm/llvm-project/commit/0740db9bc12672295bde72e7007f7837f7f632c0
Author: Ross Brunton <ross at codeplay.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M offload/tools/offload-tblgen/APIGen.cpp
Log Message:
-----------
[Offload] Add `_LAST` variant for generated enumerations (#147314)
Commit: 380954b26f64cb31da028d355941a394a3d0dacc
https://github.com/llvm/llvm-project/commit/380954b26f64cb31da028d355941a394a3d0dacc
Author: erichkeane <ekeane at nvidia.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M clang/test/AST/ast-print-cconv-preserve.cpp
Log Message:
-----------
Fix test failure introduced in ab187bb
This patch, #147285 introduced a test that used
preserve_none/preserve_all/preserve_most for the purposes of validating
its ast-dump. However, this attribute isn't supported on some
platforms, so this patch adds a triple to the test to ensure we try to
run it as a non-supported platform.
As this is simply an ast-dump test, there is no value to running it on
other configurations.
Commit: 13a1a632c25482f8fc0ffe2ca2147dec27d4d931
https://github.com/llvm/llvm-project/commit/13a1a632c25482f8fc0ffe2ca2147dec27d4d931
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/valarray/Makefile
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/valarray/TestDataFormatterStdValarray.py
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/valarray/main.cpp
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/valarray/Makefile
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/valarray/TestDataFormatterLibcxxValarray.py
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/valarray/main.cpp
Log Message:
-----------
[lldb][test] Move std::valarray from libcxx to generic directory (#147704)
This just moves the test from `libcxx` to `generic`. There are currently
no `std::valarray` formatters for libstdc++ so I didn't add a test-case
for it.
Split out from https://github.com/llvm/llvm-project/pull/146740
Commit: 8ff636309d995871627546572520b3c638830f68
https://github.com/llvm/llvm-project/commit/8ff636309d995871627546572520b3c638830f68
Author: A. Jiang <de34 at live.cn>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M libcxx/docs/Status/Cxx2cIssues.csv
Log Message:
-----------
[libc++][docs] Fix bad status and links in Cxx2cIssues.csv (#147669)
Currently, versions for (already implemented) LWG4024 and LWG4157 are
listed, but they are not marked "Complete" yet.
- LWG4024 was implemented together with P1020R1 + P1973R1 in 9af9d39a47d.
- LWG4157 was implemented together with P2167R3 in 557f7e1398e1.
Moreover, links for LWG issues resolved in 2025-02 Hagenberg meeting
were broken, they need to be fixed.
Commit: 1e6dd8c1e47f90f33b4ade4a13309d978212c297
https://github.com/llvm/llvm-project/commit/1e6dd8c1e47f90f33b4ade4a13309d978212c297
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/string/TestDataFormatterStdString.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/string/main.cpp
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/u8string/Makefile
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/u8string/TestDataFormatterStdU8String.py
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/u8string/main.cpp
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/msvcstl/string/Makefile
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/msvcstl/string/TestDataFormatterMsvcStlString.py
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/msvcstl/string/main.cpp
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/msvcstl/u8string/Makefile
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/msvcstl/u8string/TestDataFormatterMsvcStlU8String.py
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/msvcstl/u8string/main.cpp
Log Message:
-----------
[lldb][test] Merge MSVC STL std::(u8)string tests into generic directory (#147525)
Now that most STL formatter tests have been moved to `generic`. Do the
same for the MSVC tests (which are currently just for `std::string`).
The `std::string` test was mostly the same (MSVC just had 1 additional
check, which I moved over).
We also only tested `u8string` with MSVC. So i moved those into
`generic` as-is. I kept it separate from the existing std::string tests
since it requires c++20.
The tests are currently failing for libc++ and libstdc++ because MSVC
had a test case which checked that:
```
std::string overwritten_zero("abc");
const_cast<char *>(overwritten_zero.data())[3] = 'd';
```
prints as `"abc"`. But libc++ and libstdc++ print it as `"abcd"` (which
seems like the more correct thing to do?)
Commit: fa80a1a4d46d3efedd82855dc3b8c1031b11e4e1
https://github.com/llvm/llvm-project/commit/fa80a1a4d46d3efedd82855dc3b8c1031b11e4e1
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/ranges/ref_view/Makefile
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/ranges/ref_view/TestDataFormatterStdRangesRefView.py
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/ranges/ref_view/main.cpp
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/ranges/ref_view/Makefile
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/ranges/ref_view/TestDataFormatterLibcxxRangesRefView.py
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/ranges/ref_view/main.cpp
Log Message:
-----------
[lldb][test] Move std::ranges::ref_view from libcxx to generic directory (#147705)
This just moves the test from `libcxx` to `generic`. There are currently
no `std::ranges::ref_view` formatters for libstdc++ so I didn't add a
test-case for it.
Split out from https://github.com/llvm/llvm-project/pull/146740
Commit: a34db6f88937666d35a86d4aaa149e3506ecaec4
https://github.com/llvm/llvm-project/commit/a34db6f88937666d35a86d4aaa149e3506ecaec4
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M libcxx/docs/Status/Cxx23Issues.csv
M libcxx/docs/Status/Cxx2cIssues.csv
Log Message:
-----------
[libc++] Mark a few LWG issues as complete instead of Nothing To Do
A few LWG issues did require some testing changes and were not just
non-normative wording changes in the spec, so those should be
"Complete" instead of "Nothing to do".
Also mark LWG3987 and LWG4113 as complete:
- LWG3987 was done in https://github.com/llvm/llvm-project/pull/137524
- LWG4113 was done in https://github.com/llvm/llvm-project/pull/138291
Commit: bed9fe77dc690cf0147a0819350f275e65947cbe
https://github.com/llvm/llvm-project/commit/bed9fe77dc690cf0147a0819350f275e65947cbe
Author: Ross Brunton <ross at codeplay.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M offload/unittests/OffloadAPI/device_code/CMakeLists.txt
A offload/unittests/OffloadAPI/device_code/global.c
A offload/unittests/OffloadAPI/device_code/global_ctor.c
A offload/unittests/OffloadAPI/device_code/global_dtor.c
M offload/unittests/OffloadAPI/kernel/olLaunchKernel.cpp
Log Message:
-----------
[Offload] Tests for global memory and constructors (#147537)
Adds two "launch kernel" tests for lib offload, one testing that
global memory works and persists between different kernels, and one
verifying that `[[gnu::constructor]]` works correctly.
Since we now have tests that contain multiple kernels in the same
binary, the test framework has been updated a bit.
Commit: 8905b1c38f15d7f7b31e741222ae1de0a11222d8
https://github.com/llvm/llvm-project/commit/8905b1c38f15d7f7b31e741222ae1de0a11222d8
Author: Ryan Buchner <92571492+bababuck at users.noreply.github.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/zicond-opts.ll
Log Message:
-----------
[RISCV] Efficiently lower (select %cond, andn (f, x), f) using zicond (#147369)
The following case is now optimized:
(select c, (and f, ~x), f) -> (andn f, (czero_eqz x, c))
Commit: 92fbfc22c1c560e4484d4260a8ed7747f6b75476
https://github.com/llvm/llvm-project/commit/92fbfc22c1c560e4484d4260a8ed7747f6b75476
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp
Log Message:
-----------
[LLDB] Fix build after TargetInfo::adjust signature change (#147727)
Fixes buildbot failure on lldb-x86_64-debian due to
https://github.com/llvm/llvm-project/pull/146620
https://lab.llvm.org/buildbot/#/builders/162/builds/26414
Update LLDB calls to TargetInfo::adjust() to use the new 3-parameter
signature introduced in beea2a941470368a87b1816e455b1db366c1bbb9. Pass
nullptr for AuxTarget since LLDB doesn't use auxiliary targets in these
contexts.
Commit: 1770e9b5c6f9e95f253b0d8619de6f3a4290c96e
https://github.com/llvm/llvm-project/commit/1770e9b5c6f9e95f253b0d8619de6f3a4290c96e
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIROps.td
M mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrOps.td
M mlir/include/mlir/Dialect/SMT/IR/SMTIntOps.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/test/lib/Dialect/Test/TestOps.td
Log Message:
-----------
[mlir] remove dangling builders from td (#147619)
These are "dangling" builders (decls are emitted but there are no defns
anywhere).
Commit: 2d030b0ecdb32b7b6b9d47f66182db7e2dafa026
https://github.com/llvm/llvm-project/commit/2d030b0ecdb32b7b6b9d47f66182db7e2dafa026
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp
Log Message:
-----------
[lldb][Expression][NFC] Run clang-format on ClangExpressionParser.cpp and ClangModulesDeclVendor.cpp
This wasn't addressed as part of https://github.com/llvm/llvm-project/pull/147727
Commit: 18ea6fcb23ff77362008a8e1ae8671d5d6f019fe
https://github.com/llvm/llvm-project/commit/18ea6fcb23ff77362008a8e1ae8671d5d6f019fe
Author: Bruno Cardoso Lopes <bruno.cardoso at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M clang/Maintainers.rst
Log Message:
-----------
Propose new ClangIR Maintainer (#147365)
@xlauko is an active PR reviewer, contributing to ClangIR/MLIR
discussion for years now, and has been effectively overseeing the
quality of CIR dialect (the MLIR part). I'd like to nominate him to join
the list of maintainers.
---------
Co-authored-by: Henrich Lauko <xlauko at mail.muni.cz>
Commit: d0caf0d4857c2b00ba988f86703663685ec8697f
https://github.com/llvm/llvm-project/commit/d0caf0d4857c2b00ba988f86703663685ec8697f
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M flang/include/flang/Common/format.h
Log Message:
-----------
[flang] Avoid undefined behaviour when parsing format expressions (#147539)
The test flang/test/Semantics/io08.f90 was failing when UBSAN was
enabled:
```
/home/david.spickett/llvm-project/flang/include/flang/Common/format.h:224:26: runtime error: signed integer overflow: 10 * 987654321098765432 cannot be represented in type 'int64_t' (aka 'long')
SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior /home/david.spickett/llvm-project/flang/include/flang/Common/format.h:224:26
```
This is because the code was effectively:
* Take the risk of UB happening
* Check whether it happened or not
Which UBSAN is obviously not going to like. Instead of checking after
the fact, use llvm's helpers that catch overflow without actually doing
it.
Commit: 44d37695a5e158afdd9d3f9805d4a4a04cfc270a
https://github.com/llvm/llvm-project/commit/44d37695a5e158afdd9d3f9805d4a4a04cfc270a
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M libcxx/docs/ReleaseNotes/21.rst
M libcxx/include/__config
M libcxx/include/__locale
M libcxx/include/__locale_dir/locale_base_api.h
M libcxx/include/__locale_dir/support/bsd_like.h
M libcxx/include/__locale_dir/support/linux.h
M libcxx/include/__locale_dir/support/no_locale/characters.h
M libcxx/include/__locale_dir/support/windows.h
M libcxx/lib/abi/CHANGELOG.TXT
M libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.noexceptions.nonew.abilist
M libcxx/src/locale.cpp
A libcxx/test/benchmarks/locale/ctype.bench.cpp
Log Message:
-----------
[libc++] Optimize ctype::to{lower,upper} (#145344)
```
----------------------------------------------
Benchmark old new
--------------------------- ------------------
BM_tolower_char<char> 1.64 ns 1.41 ns
BM_tolower_char<wchar_t> 1.64 ns 1.41 ns
BM_tolower_string<char> 32.4 ns 12.8 ns
BM_tolower_string<wchar_t> 32.9 ns 15.1 ns
BM_toupper_char<char> 1.63 ns 1.64 ns
BM_toupper_char<wchar_t> 1.63 ns 1.41 ns
BM_toupper_string<char> 32.2 ns 12.7 ns
BM_toupper_string<wchar_t> 33.0 ns 15.1 ns
```
Commit: e8e5d07767c444913f837dd35846a92fcf520eab
https://github.com/llvm/llvm-project/commit/e8e5d07767c444913f837dd35846a92fcf520eab
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M flang/include/flang/Common/format.h
Log Message:
-----------
Revert "[flang] Avoid undefined behaviour when parsing format expressions (#147539)"
This reverts commit d0caf0d4857c2b00ba988f86703663685ec8697f.
MathExtras.h is not found in some builds.
Commit: 9f6784cc1fe40429bcab90540adabe870a78772c
https://github.com/llvm/llvm-project/commit/9f6784cc1fe40429bcab90540adabe870a78772c
Author: Ye Luo <yeluo at anl.gov>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M offload/test/offloading/disable_default_device.c
Log Message:
-----------
[libomptarget] fix test offloading/disable_default_device.c
Fixes the incorrect lit command line introduced in 536ba87726d8dea862d964678dbb761ca32e21fb
Commit: 3640a5842be1bf9dcdad72eb1fca97bc66f5b444
https://github.com/llvm/llvm-project/commit/3640a5842be1bf9dcdad72eb1fca97bc66f5b444
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
Log Message:
-----------
[RISCV] Add Commutable flag to XNOR. (#147654)
Commit: 62f8377e4029b2db9b4826431625244c17598019
https://github.com/llvm/llvm-project/commit/62f8377e4029b2db9b4826431625244c17598019
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-decreasing.ll
Log Message:
-----------
[LV] Extend FindFirstIV to unsigned case (#146386)
Extend FindFirstIV vectorization to the unsigned case by introducing and
handling FindFirstIVUMin.
Co-authored-by: Florian Hahn <flo at fhahn.com>
Commit: cd193f4c057ee5005197219df1c646b939a85711
https://github.com/llvm/llvm-project/commit/cd193f4c057ee5005197219df1c646b939a85711
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp
M clang/test/Analysis/NewDelete-checker-test.cpp
Log Message:
-----------
[analyzer] Remove redundant bug type DoubleDelete (#147542)
This commit removes the DoubleDelete bug type from `MallocChecker.cpp`
because it's completely redundant with the `DoubleFree` bug (which is
already used for all allocator families, including new/delete).
This simplifies the code of the checker and prevents the potential
confusion caused by two semantically equivalent and very similar, but
not identical bug report messages.
Commit: 179107997c0a06644aa1f177fbae7ad997457df5
https://github.com/llvm/llvm-project/commit/179107997c0a06644aa1f177fbae7ad997457df5
Author: DeanSturtevant1 <dsturtevant at google.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Update after db7888ca9aef6c203b363bbb395549b4e6cfa9d4 (#146732) (#147726)
Commit: cbb2ef3835df827b2809f4dedce6687626f30f5c
https://github.com/llvm/llvm-project/commit/cbb2ef3835df827b2809f4dedce6687626f30f5c
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/string/TestDataFormatterStdString.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/u8string/TestDataFormatterStdU8String.py
Log Message:
-----------
[lldb][test] Fix MSVC std::string formatter tests
These were mistakenly changed during https://github.com/llvm/llvm-project/pull/147525
Commit: 38cd9033987623a00a144eeb304ccacdb27d116a
https://github.com/llvm/llvm-project/commit/38cd9033987623a00a144eeb304ccacdb27d116a
Author: Jim Lin <jim at andestech.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/xandesvsinload-vln8.ll
M llvm/test/CodeGen/RISCV/rvv/xandesvsinload-vlnu8.ll
Log Message:
-----------
[RISCV] Convert the XAndesVSIntLoad intrinsic tests to opaque pointers. NFC
Commit: 6d7be75e3990e34af8ea6660c92ddca853543006
https://github.com/llvm/llvm-project/commit/6d7be75e3990e34af8ea6660c92ddca853543006
Author: David Green <david.green at arm.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/vecreduce-fadd-strict.ll
M llvm/test/CodeGen/AArch64/vecreduce-fadd.ll
Log Message:
-----------
[AArch64][GISel] Handle small vector fadd reductions.
This adds some test cases for v2 and v3 half vector fadd reductions. In doing
so it appears that GlobalISel was having trouble lowering the smaller vector
sizes. Add some basic handling by widening to a power2 or scalarizing if
necessary. Larger vectors are still having problems as FewerElements currently
requires the number of elements to be modula the vector length.
Commit: b1aa3e45f23a939d6473592a0449f647ca9cbc7b
https://github.com/llvm/llvm-project/commit/b1aa3e45f23a939d6473592a0449f647ca9cbc7b
Author: Ayokunle Amodu <ayokunle321 at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticCommentKinds.td
M clang/lib/AST/CommentSema.cpp
Log Message:
-----------
[clang][diagnostics] Refactor "warn_doc_api_container_decl_mismatch" to use enum_select (#146433)
Related: https://github.com/llvm/llvm-project/issues/123121
This patch refactors the `warn_doc_api_container_decl_mismatch`
diagnostic to use enum_select instead of select. This gets rid of magic
numbers and improves readability in the caller site.
Commit: e7c9f29fc5c44a79de9a64b12a7318c503ebb87d
https://github.com/llvm/llvm-project/commit/e7c9f29fc5c44a79de9a64b12a7318c503ebb87d
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/initializer_list/Makefile
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/initializer_list/TestDataFormatterStdInitializerList.py
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/initializer_list/main.cpp
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/initializerlist/Makefile
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/initializerlist/TestInitializerList.py
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/initializerlist/main.cpp
Log Message:
-----------
[lldb][test] Move std::initializer_list from libcxx to generic directory (#147702)
This just moves the test from `libcxx` to `generic`. There are currently
no `std::initializer_list` formatters for libstdc++ so I didn't add a
test-case for it.
Split out from https://github.com/llvm/llvm-project/pull/146740
Commit: 613a2a1359370bc5ab3fbf71b4e89ae4211467c7
https://github.com/llvm/llvm-project/commit/613a2a1359370bc5ab3fbf71b4e89ae4211467c7
Author: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.h
M llvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll
M llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll
M llvm/test/CodeGen/AArch64/sign-return-address-tailcall.ll
M llvm/test/CodeGen/AArch64/sign-return-address.ll
Log Message:
-----------
[AArch64][PAC] Protect the entire function if pac-ret+leaf is requested (#140895)
Normally, pac-ret hardening is emitted as part of function prologues and
epilogues, thus it is affected by the shrink-wrapping optimization.
As protecting LR when it is spilled to the stack is already handled by
regular -mbranch-protection=pac-ret option, it is reasonable to assume
that pac-ret+leaf option means the user wants to apply pac-ret hardening
to as much code as possible. For that reason, if pac-ret+leaf hardening
mode is requested, this patch moves the emission of PAUTH_PROLOGUE (or
PAUTH_EPILOGUE) pseudos from emitPrologue (emitEpilogue) methods of the
AArch64FrameLowering class to processFunctionBeforeFrameIndicesReplaced.
This change does not currently affect targets that emit WinCFI unwind
information.
This commit only affects where LR is signed and authenticated, but does
not otherwise prevents the shrink-wrapping optimization. Moreover,
without "+leaf" modifier PAUTH_(PROLOGUE|EPILOGUE) pseudos respect the
shrink-wrapping optimization just as any other prologue/epilogue code.
Commit: 8438c7ddbde6a31dc0e5df688046319837bfd8bd
https://github.com/llvm/llvm-project/commit/8438c7ddbde6a31dc0e5df688046319837bfd8bd
Author: James Y Knight <jyknight at google.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Update after db7888ca9aef6c203b363bbb395549b4e6cfa9d4
Commit: f92420078e6d0c1dcef0e13cc821dd57759d6663
https://github.com/llvm/llvm-project/commit/f92420078e6d0c1dcef0e13cc821dd57759d6663
Author: Mohammadreza Ameri Mahabadian <mohammadreza.amerimahabadian at arm.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
Log Message:
-----------
[mlir][spirv] TableGen definition SPIRV_Composite to include SPIRV_AnyTensorArm (#147567)
SPIRV_AnyTensorArm is a recently added composite type. This patch adds
to the list of composite type represented by SPIRV_Composite. This was
missing from a previous
[patch](https://github.com/llvm/llvm-project/pull/144667) where
SPIRV_AnyTensorArm was introduced.
Signed-off-by: Mohammadreza Ameri Mahabadian <mohammadreza.amerimahabadian at arm.com>
Commit: c22352175ef29c141de27485286275434c58e88a
https://github.com/llvm/llvm-project/commit/c22352175ef29c141de27485286275434c58e88a
Author: MaheshRavishankar <1663364+MaheshRavishankar at users.noreply.github.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
M mlir/lib/Dialect/Tensor/Transforms/SwapExtractSliceWithProducerPatterns.cpp
M mlir/test/Dialect/Linalg/transform-tile-reduction.mlir
A mlir/test/Interfaces/TilingInterface/tile-and-fuse-with-reduction-tiling.mlir
M mlir/test/lib/Interfaces/TilingInterface/TestTilingInterfaceTransformOps.cpp
M mlir/test/lib/Interfaces/TilingInterface/TestTilingInterfaceTransformOps.td
Log Message:
-----------
[mlir][TilingInterface] Allow tile and fuse to work with `ReductionTilingStrategy::PartialReductionOuterParallelStrategy`. (#147593)
Since `scf::tileUsingSCF` is the core method used for tiling the root
operation within the `scf::tileConsumersAndFuseProducersUsingSCF`, the
latter can fuse into any tiled loop generated using `scf::tileUsingSCF`.
This patch adds a test for tiling a root operation using
`ReductionTilingStrategy::PartialReductionOuterParallelStrategy` and
fusing producers with it.
Since this strategy generates a rank-reducing extract slice
`tensor::replaceExtractSliceWithTiledProducer` which is the core method
used for the fusion was extended to handle the rank-reducing slices.
Also fix a small bug in the computation of the reduction induction
variable (which needs to use `floorDiv` instead of `ceilDiv`)
Signed-off-by: MaheshRavishankar <mahesh.ravishankar at gmail.com>
Commit: 668c964282f0850a07976f46182efe745f77b789
https://github.com/llvm/llvm-project/commit/668c964282f0850a07976f46182efe745f77b789
Author: Daniel Hernandez-Juarez <danherna at amd.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp
A mlir/test/Conversion/AMDGPUToROCDL/load_lds-gfx950.mlir
M mlir/test/Conversion/AMDGPUToROCDL/load_lds.mlir
M mlir/test/Conversion/AMDGPUToROCDL/transpose_load.mlir
Log Message:
-----------
[AMDGPU] [MLIR] Add 96 and 128 bit GatherToLDS for gfx950 (#147496)
This PR adds 96 and 128 gather_to_lds support for gfx950. Updating
lowering, verifier and tests.
Commit: 23b4f4eb9b15e0c3a8d86d9c0857075afcfc7fe3
https://github.com/llvm/llvm-project/commit/23b4f4eb9b15e0c3a8d86d9c0857075afcfc7fe3
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[NFC][TableGen] Change DecoderEmitter `insertBits` to use integer types only (#147613)
The `insertBits` templated function generated by DecoderEmitter is
called with variable `tmp` of type `TmpType` which is:
```
using TmpType = std::conditional_t<std::is_integral<InsnType>::value, InsnType, uint64_t>;
```
That is, `TmpType` is always an integral type. Change the generated
`insertBits` to be valid only for integer types, and eliminate the
unused `insertBits` function from `DecoderUInt128` in
AMDGPUDisassembler.h
Additionally, drop some of the requirements `InsnType` must support as
they no longer seem to be required.
Commit: 896d900c9b71f8b11bcacc8ead56f15c8a16155b
https://github.com/llvm/llvm-project/commit/896d900c9b71f8b11bcacc8ead56f15c8a16155b
Author: LU-JOHN <John.Lu at amd.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
A llvm/test/CodeGen/AMDGPU/ashr64_reduce_flags.ll
A llvm/test/CodeGen/AMDGPU/neg_ashr64_reduce.ll
Log Message:
-----------
[AMDGPU] Create hi-half of 64-bit ashr with mov of -1 (#146569)
When performing a 64-bit sra of a negative value with a shift range from
[32-63], create the hi-half with a move of -1.
Alive verification: https://alive2.llvm.org/ce/z/kXd7Ac
Also, preserve exact flag. Alive verification:
https://alive2.llvm.org/ce/z/L86tXf.
---------
Signed-off-by: John Lu <John.Lu at amd.com>
Commit: 56679a8414f460eb44ac5721bca332bb40d11e91
https://github.com/llvm/llvm-project/commit/56679a8414f460eb44ac5721bca332bb40d11e91
Author: higher-performance <higher.performance.github at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaInit.cpp
M clang/test/Sema/uninit-variables.c
M clang/test/SemaCXX/uninitialized.cpp
Log Message:
-----------
Include [[clang::require_explicit_initialization]] warnings in system headers (#141133)
Fixes #141103
Commit: 66316657ab36e4a262c9a2fe378d25421e116487
https://github.com/llvm/llvm-project/commit/66316657ab36e4a262c9a2fe378d25421e116487
Author: Baranov Victor <bar.victor.2002 at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M clang-tools-extra/clang-tidy/modernize/PassByValueCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/modernize/pass-by-value.cpp
Log Message:
-----------
[clang-tidy] properly handle private move constructors in `modernize-pass-by-value` check (#141304)
Fixed false positives when class passed by const-reference had a private
move constructor, which could not be used for a fix-it.
Closes https://github.com/llvm/llvm-project/issues/140236.
Commit: d59d2652c8724b0039249929f5bb5c38bcecc0da
https://github.com/llvm/llvm-project/commit/d59d2652c8724b0039249929f5bb5c38bcecc0da
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
M llvm/lib/Target/RISCV/RISCVSchedAndes45.td
M llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td
M llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
M llvm/lib/Target/RISCV/RISCVSchedRocket.td
M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
M llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
M llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td
M llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td
M llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
M llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
M llvm/lib/Target/RISCV/RISCVScheduleXSf.td
A llvm/test/tools/llvm-mca/RISCV/SiFive7/xsfvfnrclip.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveX390/xsfvfnrclip.s
Log Message:
-----------
[RISCV] Add scheduling info for XSfvfnrclipxfqf instructions (#147586)
This patch adds scheduling data for the XSfvfnrclipxfqf instruction,
which narrows / clips FP32 data to INT8 according to value range
specified by a scalar register. Three new SchedReadWrites are
introduced.
Commit: 7c6edf4a058b957adce1596def56b64e07edf850
https://github.com/llvm/llvm-project/commit/7c6edf4a058b957adce1596def56b64e07edf850
Author: Callum Fare <callum at codeplay.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M offload/liboffload/API/Event.td
M offload/liboffload/API/Queue.td
M offload/liboffload/src/OffloadImpl.cpp
M offload/unittests/OffloadAPI/CMakeLists.txt
M offload/unittests/OffloadAPI/common/Fixtures.hpp
A offload/unittests/OffloadAPI/event/olGetEventInfo.cpp
A offload/unittests/OffloadAPI/event/olGetEventInfoSize.cpp
A offload/unittests/OffloadAPI/queue/olGetQueueInfo.cpp
A offload/unittests/OffloadAPI/queue/olGetQueueInfoSize.cpp
Log Message:
-----------
[Offload] Implement olGetQueueInfo, olGetEventInfo (#142947)
Add info queries for queues and events.
`olGetQueueInfo` only supports getting the associated device. We were
already tracking this so we can implement this for free. We will likely
add other queries to it in the future (whether the queue is empty, what
flags it was created with, etc)
`olGetEventInfo` only supports getting the associated queue. This is
another thing we were already storing in the handle. We'll be able to
add other queries in future (the event type, status, etc)
Commit: f71b188fbb256ab84aebfba9f7870c04b3a3d44d
https://github.com/llvm/llvm-project/commit/f71b188fbb256ab84aebfba9f7870c04b3a3d44d
Author: James Y Knight <jyknight at google.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M utils/bazel/llvm_configs/abi-breaking.h.cmake
Log Message:
-----------
[bazel] Update after 24475409e4eac6fd60e2111424a4bef3452c8f21
Commit: e7ab9209b1b6145629e73e1fc81cf9f4a4610e9c
https://github.com/llvm/llvm-project/commit/e7ab9209b1b6145629e73e1fc81cf9f4a4610e9c
Author: James Y Knight <jyknight at google.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel] Fix after db03408b24459f0ba9f320509c7f8b3ec128e4b4
Commit: 820a48523b0804ddc77fe08fba738b3ca2aeb8e2
https://github.com/llvm/llvm-project/commit/820a48523b0804ddc77fe08fba738b3ca2aeb8e2
Author: James Y Knight <jyknight at google.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Update after 6f291cb099e54af8ebcb68a622c81206ba94abe5
Commit: 2756ba57f1541d63af0fd01f9fda773d88dcc3b5
https://github.com/llvm/llvm-project/commit/2756ba57f1541d63af0fd01f9fda773d88dcc3b5
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M lldb/bindings/python/CMakeLists.txt
Log Message:
-----------
[lldb] Enable SWIG Doxygen Translation (#147617)
Enable SWIG support for translating Doxygen comments found in interface
and header files into a target language's normal documentation language.
This feature was introduced in SWIG 4.0 and currently only supports
Python (and Java). Hand-written documentation still takes precedence.
SWIG documentation: https://www.swig.org/Doc4.0/Doxygen.html
Commit: afc82ce3aa56670101495d7f328d938f55ccaf8b
https://github.com/llvm/llvm-project/commit/afc82ce3aa56670101495d7f328d938f55ccaf8b
Author: Chelsea Cassanova <chelsea_cassanova at apple.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M lldb/cmake/modules/LLDBConfig.cmake
M lldb/test/CMakeLists.txt
A lldb/test/Shell/RPC/Generator/Inputs/SBDummy.h
A lldb/test/Shell/RPC/Generator/Tests/CheckRPCGenToolByproducts.test
A lldb/test/Shell/RPC/Generator/lit.local.cfg
M lldb/test/Shell/helper/toolchain.py
M lldb/test/Shell/lit.site.cfg.py.in
M lldb/tools/CMakeLists.txt
A lldb/tools/lldb-rpc/CMakeLists.txt
A lldb/tools/lldb-rpc/LLDBRPCGeneration.cmake
A lldb/tools/lldb-rpc/LLDBRPCHeaders.cmake
A lldb/tools/lldb-rpc/lldb-rpc-gen/CMakeLists.txt
A lldb/tools/lldb-rpc/lldb-rpc-gen/RPCCommon.cpp
A lldb/tools/lldb-rpc/lldb-rpc-gen/RPCCommon.h
M lldb/tools/lldb-rpc/lldb-rpc-gen/lldb-rpc-gen.cpp
Log Message:
-----------
Reland "[lldb][RPC] Upstream lldb-rpc-gen tool" (#146969) (#147417)
Relands the commit to upstream the lldb-rpc-gen tool in order to fix a
build failure on the linux remote bots. The reland adds the Clang
resource dir unconditionally to the invocation for the tool instead of
only adding it in the event that we're using a standalone build.
Original PR description:
This commit upstreams the lldb-rpc-gen tool, a ClangTool that generates
the LLDB RPC client and server interfaces. This tool, as well as LLDB
RPC itself is built by default. If it needs to be disabled, put
-DLLDB_BUILD_LLDBRPC=OFF in your CMake invocation.
https://discourse.llvm.org/t/rfc-upstreaming-lldb-rpc/85804
Original PR Link:
https://github.com/llvm/llvm-project/pull/138031
Commit: 9b5959dd9a0eb0fc005b92be7ef7f3a5e3377b81
https://github.com/llvm/llvm-project/commit/9b5959dd9a0eb0fc005b92be7ef7f3a5e3377b81
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M libclc/cmake/modules/AddLibclc.cmake
Log Message:
-----------
[libclc] Change symlinks to copies on Windows (#147759)
This mirrors how other LLVM libraries handle symlinks
Commit: ddfc13c191c3f73d66bd01b97a2005edeb672fa1
https://github.com/llvm/llvm-project/commit/ddfc13c191c3f73d66bd01b97a2005edeb672fa1
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/test/CIR/CodeGen/complex-builtins.cpp
Log Message:
-----------
[CIR] Upstream __builtin_creal for ComplexType (#146927)
Upstream `__builtin_creal` support for ComplexType
https://github.com/llvm/llvm-project/issues/141365
Commit: 080ade03ac21f493f6bacb27021bf708a4554891
https://github.com/llvm/llvm-project/commit/080ade03ac21f493f6bacb27021bf708a4554891
Author: Andrew Rogers <andrurogerz at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/unittests/TableGen/CMakeLists.txt
Log Message:
-----------
[llvm] statically link TableGenTests (#147577)
## Purpose
Statically link `TableGenTests` so it can still build when linked
against an LLVM Windows DLL.
## Background
The effort to build LLVM as a WIndows DLL is tracked in #109483.
Additional context is provided in [this
discourse](https://discourse.llvm.org/t/psa-annotating-llvm-public-interface/85307).
If `TableGenTests` is linked against LLVM built as a DLL on Windows, it
will fail due to a large number of duplicate symbols found in both the
LLVM DLL and TableGen libraries. This is because `LLVMTableGenBasic` and
`LLVMTableGenCommon` are linked statically against LLVM (using
`DISABLE_LLVM_LINK_LLVM_DYLIB`) so already contain a sub-set of symbols
also exported from the LLVM DLL.
This patch was originally part of #145448.
Commit: c2a818f48bb5a1cda6d94f5e1956019678c67d89
https://github.com/llvm/llvm-project/commit/c2a818f48bb5a1cda6d94f5e1956019678c67d89
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
M llvm/lib/Target/RISCV/RISCVSchedAndes45.td
M llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td
M llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
M llvm/lib/Target/RISCV/RISCVSchedRocket.td
M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
M llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
M llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td
M llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td
M llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
M llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
M llvm/lib/Target/RISCV/RISCVScheduleXSf.td
A llvm/test/tools/llvm-mca/RISCV/SiFive7/xsfvfwmacc.s
A llvm/test/tools/llvm-mca/RISCV/SiFive7/xsfvqmacc.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveX390/xsfvfwmacc.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveX390/xsfvqmacc.s
Log Message:
-----------
[RISCV] Add scheduling info for XSfvqmaccdod/qoq and XSfvfwmaccqqq instructions (#147626)
XSfvqmaccdod/qoq and XSfvfwmaccqqq are SiFive's small-size matrix
multiplication extensions. This patches add scheduling info for their
instructions along with six new SchedReadWrite.
Commit: 76a841a5e6f696890ce6abf6f11bd9915f1d77d9
https://github.com/llvm/llvm-project/commit/76a841a5e6f696890ce6abf6f11bd9915f1d77d9
Author: Chelsea Cassanova <chelsea_cassanova at apple.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M lldb/cmake/modules/LLDBConfig.cmake
M lldb/test/CMakeLists.txt
R lldb/test/Shell/RPC/Generator/Inputs/SBDummy.h
R lldb/test/Shell/RPC/Generator/Tests/CheckRPCGenToolByproducts.test
R lldb/test/Shell/RPC/Generator/lit.local.cfg
M lldb/test/Shell/helper/toolchain.py
M lldb/test/Shell/lit.site.cfg.py.in
M lldb/tools/CMakeLists.txt
R lldb/tools/lldb-rpc/CMakeLists.txt
R lldb/tools/lldb-rpc/LLDBRPCGeneration.cmake
R lldb/tools/lldb-rpc/LLDBRPCHeaders.cmake
R lldb/tools/lldb-rpc/lldb-rpc-gen/CMakeLists.txt
R lldb/tools/lldb-rpc/lldb-rpc-gen/RPCCommon.cpp
R lldb/tools/lldb-rpc/lldb-rpc-gen/RPCCommon.h
M lldb/tools/lldb-rpc/lldb-rpc-gen/lldb-rpc-gen.cpp
Log Message:
-----------
Revert "Reland "[lldb][RPC] Upstream lldb-rpc-gen tool" (#146969)" (#147779)
Reverts llvm/llvm-project#147417. Failing an assert:
`lldb-rpc-gen:
../llvm-project/lldb/tools/lldb-rpc/lldb-rpc-gen/server/RPCServerSourceEmitter.cpp:361:
void lldb_rpc_gen::RPCServerSourceEmitter::EmitMethodCallAndEncode(const
Method &): Assertion `Pos != MethodsWithPointerReturnTypes.end() &&
"Unable to determine the size of the return buffer"' failed.`
Commit: 4a66ba2a4d9b0b95051e807f0659991a7e529874
https://github.com/llvm/llvm-project/commit/4a66ba2a4d9b0b95051e807f0659991a7e529874
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
Log Message:
-----------
[IA] Support deinterleave intrinsics w/ fewer than N extracts (#147572)
For the fixed vector cases, we already support this, but the
deinterleave intrinsic cases (primary used by scalable vectors) didn't.
Supporting it requires plumbing through the Factor separately from the
extracts, as there can now be fewer extracts than the Factor. Note that
the fixed vector path handles this slightly differently - it uses the
shuffle and indices scheme to achieve the same thing.
Commit: 3e4e5dbc2599e08fb2cadc3829869b18a7c17667
https://github.com/llvm/llvm-project/commit/3e4e5dbc2599e08fb2cadc3829869b18a7c17667
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll
Log Message:
-----------
[AMDGPU] shl_add_ptr.ll - regenerate test checks
Commit: 1431f8f76fa2270cedc88efdebcc236bf374b144
https://github.com/llvm/llvm-project/commit/1431f8f76fa2270cedc88efdebcc236bf374b144
Author: Hervé Poussineau <hpoussin at reactos.org>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M libcxx/include/__cxx03/__thread/support/windows.h
M libcxx/include/__thread/support/windows.h
Log Message:
-----------
[libc++] Simplify definition of __libcpp_recursive_mutex_t (#147385)
As it only depends of pointer size, use `_WIN64` define to simplify conditions.
Commit: 30a2b8bacaf6069718243d22af2a12a418e5e9ec
https://github.com/llvm/llvm-project/commit/30a2b8bacaf6069718243d22af2a12a418e5e9ec
Author: Petr Hosek <phosek at google.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M clang/cmake/caches/Fuchsia-stage2.cmake
Log Message:
-----------
[CMake][Fuchsia] Switch to RUNTIMES_USE_LIBC option (#147776)
LIBCXX_LIBC was renamed to RUNTIMES_USE_LIBC in #134893.
Commit: 8c32f9517a1207e899ae5276838eb1670e605cba
https://github.com/llvm/llvm-project/commit/8c32f9517a1207e899ae5276838eb1670e605cba
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M .ci/monolithic-windows.sh
M .github/workflows/premerge.yaml
Log Message:
-----------
[CI][Github] Remove MAX_PARALLEL_*_JOBS Args from Windows Runs (#147770)
This patch removes setting the MAX_PARLLEL_COMPILE_JOBS and
MAX_PARALLEL_LINK_JOBS env variables in the windows runs. These were
originally used to control the parallelism on the old infrastructure and
we set them on the new infrastructure explicitly so that we could
maintain both at the same time. Now it does not make sense to keep them
explicitly set that we do not need to explicitly control the parallelism
given the amount of RAM we have on the machines. This also adds a
maintnenace cost as evidenced by the fact that these have been incorrect
(64 instead of 32) for quite a while.
Commit: 64453c802eca9bd839e2fb43d1a6a1b0e7c83e58
https://github.com/llvm/llvm-project/commit/64453c802eca9bd839e2fb43d1a6a1b0e7c83e58
Author: Justin King <jcking at google.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
M compiler-rt/test/sanitizer_common/TestCases/Linux/free_aligned_sized.c
M compiler-rt/test/sanitizer_common/TestCases/Linux/free_sized.c
Log Message:
-----------
rtsan: Support free_sized and free_aligned_sized from C23 (#145085)
Adds support to RTSan for `free_sized` and `free_aligned_sized` from
C23.
Other sanitizers will be handled with their own separate PRs.
For https://github.com/llvm/llvm-project/issues/144435
Signed-off-by: Justin King <jcking at google.com>
Commit: c57fe2f6caf9fe4818addde1f311209e79481d10
https://github.com/llvm/llvm-project/commit/c57fe2f6caf9fe4818addde1f311209e79481d10
Author: James Y Knight <jyknight at google.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/llvm-config.h
M utils/bazel/llvm_configs/llvm-config.h.cmake
Log Message:
-----------
[bazel] Update after 058056329982db13d513bc05d3c98f6558418242
Commit: a63846b475bacfda49eb00016e0dc43c9ab1aa7d
https://github.com/llvm/llvm-project/commit/a63846b475bacfda49eb00016e0dc43c9ab1aa7d
Author: Leandro Lupori <leandro.lupori at linaro.org>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
M flang/test/HLFIR/opt-scalar-assign.fir
Log Message:
-----------
[flang] Fix array assignment regression introduced by #147371 (#147761)
In some cases fixed shape arrays can be fir.heap/fir.ptr, even
after hlfir::derefPointersAndAllocatables() is called.
Commit: cd9236d78833a3f312d0a38e53e3f12e9926bcf3
https://github.com/llvm/llvm-project/commit/cd9236d78833a3f312d0a38e53e3f12e9926bcf3
Author: Rahman Lavaee <rahmanl at google.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/Analysis/InlineCost.cpp
A llvm/test/Transforms/Inline/inline-call-with-asm-call.ll
Log Message:
-----------
Account for inline assembly instructions in inlining cost. (#146628)
Inliner currently treats every "call asm" IR instruction as a single
instruction regardless of how many instructions the inline assembly may
contain. This may underestimate the cost of inlining for a callee
containing long inline assembly. Besides, we may need to assign a higher
cost to instructions in inline assembly since they cannot be analyzed
and optimized by the compiler.
This PR introduces a new option `-inline-asm-instr-cost` -- set zero by
default, which can control the cost of inline assembly instructions in
inliner's cost-benefit analysis.
Commit: 4c27279ec4c255b93a4cb3f044509121ebf01f10
https://github.com/llvm/llvm-project/commit/4c27279ec4c255b93a4cb3f044509121ebf01f10
Author: jyli0116 <yu.li at arm.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/docs/GlobalISel/GenericOpcode.rst
M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
M llvm/include/llvm/Support/TargetOpcodes.def
M llvm/include/llvm/Target/GenericOpcodes.td
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
M llvm/test/MC/ELF/mc-dump.s
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-cxx.td
M llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
Log Message:
-----------
[GlobalISel] Add Saturated Truncate Instructions (#147526)
Introduces saturated truncate instructions to Global ISel:
G_TRUNC_SSAT_S, G_TRUNC_SSAT_U, G_TRUNC_USAT_U. These were previously
introduced to SDAG to reduce redundant code.
The patch only initially introduces the instruction, a later patch will
follow to add combines and legalization for each instruction.
Commit: fcecf177c1052815f0bd9d7159dd406e96bb6f62
https://github.com/llvm/llvm-project/commit/fcecf177c1052815f0bd9d7159dd406e96bb6f62
Author: Rahman Lavaee <rahmanl at google.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/docs/Extensions.rst
M llvm/include/llvm/CodeGen/AsmPrinter.h
M llvm/include/llvm/MC/MCContext.h
M llvm/include/llvm/Object/ELFTypes.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/test/CodeGen/X86/basic-block-address-map-empty-function.ll
M llvm/test/CodeGen/X86/basic-block-address-map-function-sections.ll
M llvm/test/CodeGen/X86/basic-block-address-map-pgo-features.ll
M llvm/test/CodeGen/X86/basic-block-address-map-with-basic-block-sections.ll
M llvm/test/CodeGen/X86/basic-block-address-map-with-mfs.ll
M llvm/test/CodeGen/X86/basic-block-address-map.ll
Log Message:
-----------
[SHT_LLVM_BB_ADDR_MAP] Emit callsite offsets in the `SHT_LLVM_BB_ADDR_MAP` section. (#146563)
Callsite offsets will help map addresses to the right position in the
basic block (before or after a callsite).
This PR also bumps the BBAddrMap version to 3.
The encoding/decoding ability is already pushed upstream
8d7a8fcc3ab9f6d4c4a7e4312876fe94ed3d6c4f.
Commit: a57aaedc35a39bd1f573929d5c2cb56fd1cccab4
https://github.com/llvm/llvm-project/commit/a57aaedc35a39bd1f573929d5c2cb56fd1cccab4
Author: ganenkokb-yandex <160136233+ganenkokb-yandex at users.noreply.github.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M clang/include/clang/AST/ExprConcepts.h
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/lib/AST/ASTConcept.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ASTStructuralEquivalence.cpp
M clang/lib/ASTMatchers/ASTMatchersInternal.cpp
M clang/unittests/AST/ASTImporterTest.cpp
Log Message:
-----------
Ast importer visitors (#138838)
I've rebased commit from
[Evianaive](https://github.com/Evianaive/llvm-project/commits?author=Evianaive)
and compiled it.
I hope it will speed up fix for #129393.
---------
Co-authored-by: Evianaive <153540933 at qq.com>
Commit: b44c50d41626b7b81da7cdfb2292a0b58fcc838f
https://github.com/llvm/llvm-project/commit/b44c50d41626b7b81da7cdfb2292a0b58fcc838f
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
M llvm/lib/Target/NVPTX/NVPTX.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
M llvm/test/CodeGen/NVPTX/atomics-sm70.ll
M llvm/test/CodeGen/NVPTX/atomics-sm90.ll
M llvm/test/CodeGen/NVPTX/atomics.ll
M llvm/test/CodeGen/NVPTX/bf16-instructions.ll
M llvm/test/CodeGen/NVPTX/branch-fold.mir
M llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
M llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
M llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
M llvm/test/CodeGen/NVPTX/cmpxchg.ll
M llvm/test/CodeGen/NVPTX/compare-int.ll
M llvm/test/CodeGen/NVPTX/distributed-shared-cluster.ll
M llvm/test/CodeGen/NVPTX/extractelement.ll
M llvm/test/CodeGen/NVPTX/f16-instructions.ll
M llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/fast-math.ll
M llvm/test/CodeGen/NVPTX/i1-select.ll
M llvm/test/CodeGen/NVPTX/i128.ll
M llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test1.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test3.ll
M llvm/test/CodeGen/NVPTX/jump-table.ll
M llvm/test/CodeGen/NVPTX/load-with-non-coherent-cache.ll
M llvm/test/CodeGen/NVPTX/lower-aggr-copies.ll
M llvm/test/CodeGen/NVPTX/math-intrins.ll
M llvm/test/CodeGen/NVPTX/sext-setcc.ll
M llvm/test/CodeGen/NVPTX/tid-range.ll
Log Message:
-----------
[NVPTX] Rework and cleanup FTZ ISel (#146410)
This change cleans up DAG-to-DAG instruction selection around FTZ and
SETP comparison mode. Largely these changes do not impact functionality
though support for `{sin.cos}.approx.ftz.f32` is added.
Commit: bdc0119e1b6001be813a540134bd1772b4d9c4dc
https://github.com/llvm/llvm-project/commit/bdc0119e1b6001be813a540134bd1772b4d9c4dc
Author: Matthias Braun <matze at braunis.de>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/Support/ErrorHandling.cpp
Log Message:
-----------
ErrorHandling: Check for EINTR and partial writes (#147595)
Calls to the posix `write` function can return -1 and set errno to
`EINTR` or perform partial writes when interrupted by signals. In those
cases applications are supposed to just try again. See for example the
documentation in glibc:
https://sourceware.org/glibc/manual/latest/html_node/I_002fO-Primitives.html#index-write
This fixes the uses in `ErrorHandling.cpp` to retry as needed.
Commit: 85cc4afdefee251b38d711f3922eac6fba84d5f8
https://github.com/llvm/llvm-project/commit/85cc4afdefee251b38d711f3922eac6fba84d5f8
Author: LU-JOHN <John.Lu at amd.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
Log Message:
-----------
[NFC][AMDGPU] Do not hardcode minimum instruction alignment (#147785)
Use symbolic value for minimum instruction alignment.
Signed-off-by: John Lu <John.Lu at amd.com>
Commit: dd54b8e462aa7dfa414ad88baa2f1bc3635022b1
https://github.com/llvm/llvm-project/commit/dd54b8e462aa7dfa414ad88baa2f1bc3635022b1
Author: MangalaPG <Mangala.P.G at ibm.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
Log Message:
-----------
Clang-Tidy issues in fixed in file SystemZISelLowering.cpp (#147251)
Corrected variable names corrections according to the clang-tidy
standards.
---------
Signed-off-by: MangalaPG <mangala.P.G at ibm.com>
Commit: d5da826159bdae439c194f20ab2cdb63d9f52169
https://github.com/llvm/llvm-project/commit/d5da826159bdae439c194f20ab2cdb63d9f52169
Author: Lei Huang <lei at ca.ibm.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsPPC.def
Log Message:
-----------
[PowerPC][NFC] Define new alias for mma accumulate builtins (#147382)
Move documentation for macros up to where the macros are initially defined and
add new custom MMA builtin macro in prep for adding more accumulate builtins to clang.
---------
Co-authored-by: Amy Kwan <amy.kwan1 at ibm.com>
Commit: 420e2f584de21385f07965f78458119ede6768d8
https://github.com/llvm/llvm-project/commit/420e2f584de21385f07965f78458119ede6768d8
Author: Finn Plummer <finn.c.plum at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/include/llvm/Frontend/HLSL/RootSignatureValidations.h
M llvm/lib/Frontend/HLSL/RootSignatureValidations.cpp
M llvm/lib/Target/DirectX/DXILRootSignature.cpp
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-AllValidFlagCombinationsV1.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-Invalid-Flag.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-Invalid-NumDescriptors.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-Invalid-RangeType.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-Invalid-RegisterSpace.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Parameters.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor-Invalid-Flags.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor-Invalid-Multiple-Flags.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor_V1.ll
Log Message:
-----------
[DirectX] Add missing verifications during `validate` of `DXILRootSignature` (#147111)
This pr resolves some discrepancies in verification during `validate` in
`DXILRootSignature.cpp`.
Note: we don't add a backend test for version 1.0 flag values because it
treats the struct as though there is no flags value. However, this will
be used when we use the verifications in the frontend.
- Updates `verifyDescriptorFlag` to check for valid flags based on
version, as reflected [here](https://github.com/llvm/wg-hlsl/pull/297)
- Add test to demonstrate updated flag verifications
- Adds `verifyNumDescriptors` to the validation of `DescriptorRange`s
- Add a test to demonstrate `numDescriptors` verification
- Updates a number of tests that mistakenly had an invalid
`numDescriptors` specified
Resolves: https://github.com/llvm/llvm-project/issues/147107
Commit: 7bf439d2607e636ada7e0bafda0fae447ec36002
https://github.com/llvm/llvm-project/commit/7bf439d2607e636ada7e0bafda0fae447ec36002
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
Log Message:
-----------
[IA] Partially revert interface change from 4a66ba
As noted in post commit review, the API change here was not required.
I'd apparently confused myself when teasing apart patches from my
development branch.
Commit: 61d52ea7648e6a060a4eb40cac1569dcf8e954b4
https://github.com/llvm/llvm-project/commit/61d52ea7648e6a060a4eb40cac1569dcf8e954b4
Author: Thurston Dang <thurston at google.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
Log Message:
-----------
[NFCI][msan] Refactor to use 'isFixedIntVector' etc. (#147789)
Inspired by a suggestion from Florian Google in
https://github.com/llvm/llvm-project/pull/147606#discussion_r2193548994
Commit: 889ac879ce46e99533c8400e093645741cddbd3e
https://github.com/llvm/llvm-project/commit/889ac879ce46e99533c8400e093645741cddbd3e
Author: Diego Caballero <dieg0ca6aller0 at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M mlir/include/mlir/Dialect/Vector/Transforms/VectorRewritePatterns.h
M mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorDistribute.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransferOpTransforms.cpp
M mlir/test/Conversion/VectorToSCF/vector-to-scf.mlir
M mlir/test/Dialect/Vector/scalar-vector-transfer-to-memref.mlir
M mlir/test/Dialect/Vector/vector-warp-distribute.mlir
Log Message:
-----------
[mlir][Vector] Remove usage of `vector.insertelement/extractelement` from Vector (#144413)
This PR is part of the last step to remove `vector.extractelement` and `vector.insertelement` ops.
RFC: https://discourse.llvm.org/t/rfc-psa-remove-vector-extractelement-and-vector-insertelement-ops-in-favor-of-vector-extract-and-vector-insert-ops
It removes instances of `vector.extractelement` and `vector.insertelement` from the Vector dialect layer.
Commit: aa27d4e0c3aef8047828aa453f2943730aa779c6
https://github.com/llvm/llvm-project/commit/aa27d4e0c3aef8047828aa453f2943730aa779c6
Author: Eli Friedman <efriedma at quicinc.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/AST/ExprConstant.cpp
M clang/test/SemaCXX/cxx1z-constexpr-lambdas.cpp
Log Message:
-----------
[clang] Implement consteval for captured structured bindings. (#147615)
127bf44385424891eb04cff8e52d3f157fc2cb7c implemented most of the
infrastructure for capturing structured bindings in lambdas, but missed
one piece: constant evaluation of such lambdas. Refactor the code to
handle this case.
Fixes #145956.
Commit: 23665736796e61ece80ca7b7203c16489cf37341
https://github.com/llvm/llvm-project/commit/23665736796e61ece80ca7b7203c16489cf37341
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/include/llvm/ADT/StringMapEntry.h
M llvm/include/llvm/TableGen/StringToOffsetTable.h
M llvm/lib/TableGen/StringToOffsetTable.cpp
M llvm/test/TableGen/MixedCasedMnemonic.td
M llvm/test/TableGen/SDNodeInfoEmitter/basic.td
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
M llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
M llvm/utils/TableGen/OptionParserEmitter.cpp
Log Message:
-----------
[TableGen] Minor cleanup in `StringToOffsetTable` (#147712)
Make `AppendZero` a class member instead of an argument to
`GetOrAddStringOffset` to reflect the intended usage that for a given
`StringToOffsetTable`, all strings must use the same value of
`AppendZero`.
Modify `EmitStringTableDef` to drop the `Indent` argument as its always
set to `""`, and to fail if it's called for a table with
non-null-terminated strings.
Commit: ff365ce1d71df6231a4b9d37f8d4bfc6d35a2a34
https://github.com/llvm/llvm-project/commit/ff365ce1d71df6231a4b9d37f8d4bfc6d35a2a34
Author: enh-google <enh at google.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M libc/src/wchar/wcpncpy.cpp
M libc/test/src/wchar/wcpncpy_test.cpp
Log Message:
-----------
Reland "Fix wcpncpy() return value; add test." (#146753)
Reverts llvm/llvm-project#146752, which was a revert of my accidental
push, so we can actually review and presubmit this time.
Commit: bb7cea06378286a9c09553c67962d29bec529770
https://github.com/llvm/llvm-project/commit/bb7cea06378286a9c09553c67962d29bec529770
Author: Krishna Pandey <kpandey81930 at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M libc/src/__support/CPP/type_traits/is_floating_point.h
M libc/src/__support/FPUtil/CMakeLists.txt
M libc/src/__support/FPUtil/FPBits.h
A libc/src/__support/FPUtil/bfloat16.h
M libc/src/__support/FPUtil/cast.h
M libc/src/__support/FPUtil/dyadic_float.h
M libc/src/__support/macros/properties/types.h
M libc/test/src/__support/FPUtil/CMakeLists.txt
A libc/test/src/__support/FPUtil/bfloat16_test.cpp
M libc/test/src/math/exhaustive/CMakeLists.txt
A libc/test/src/math/exhaustive/bfloat16_test.cpp
M libc/utils/MPFRWrapper/CMakeLists.txt
M libc/utils/MPFRWrapper/MPCommon.cpp
M libc/utils/MPFRWrapper/MPCommon.h
Log Message:
-----------
[libc][math][c++23] Add bfloat16 support in LLVM libc (#144463)
This PR enables support for BFloat16 type in LLVM libc along with
support for testing BFloat16 functions via MPFR.
---------
Signed-off-by: krishna2803 <kpandey81930 at gmail.com>
Signed-off-by: Krishna Pandey <kpandey81930 at gmail.com>
Co-authored-by: OverMighty <its.overmighty at gmail.com>
Commit: 8f8b1b0402ede9bee4225bfde18ea1be8158dba2
https://github.com/llvm/llvm-project/commit/8f8b1b0402ede9bee4225bfde18ea1be8158dba2
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCTypeInterfaces.td
Log Message:
-----------
[mlir][acc][nfc] Update type interface descriptions (#147807)
PointerLikeType and MappableType interfaces are now described with more
detail.
Commit: fc9dd587347ee2708ac1eff2716d3edd6b08a873
https://github.com/llvm/llvm-project/commit/fc9dd587347ee2708ac1eff2716d3edd6b08a873
Author: Andre Kuhlenschmidt <andre.kuhlenschmidt at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M flang/include/flang/Frontend/CompilerInvocation.h
M flang/include/flang/Parser/message.h
M flang/include/flang/Semantics/semantics.h
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Frontend/FrontendAction.cpp
M flang/lib/Parser/message.cpp
M flang/lib/Semantics/semantics.cpp
A flang/test/Driver/fatal-errors-parsing.f90
A flang/test/Driver/fatal-errors-semantics.f90
Log Message:
-----------
[flang][driver] add -Wfatal-errors (#147614)
Adds the flag `-Wfatal-errors` which truncates the error messages at 1 error.
Commit: 44582c9f088c17f75d0b728e4b410e661b608359
https://github.com/llvm/llvm-project/commit/44582c9f088c17f75d0b728e4b410e661b608359
Author: OverMighty <its.overmighty at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M libc/src/__support/FPUtil/dyadic_float.h
Log Message:
-----------
[libc] Fix DyadicFloat::generic_as() requiring LIBC_TYPES_HAS_FLOAT16 (#147811)
See https://lab.llvm.org/buildbot/#/builders/215/builds/710.
Commit: 8b9bbd9ed6f8267ad1e5aa76a8a96b8749cf16d9
https://github.com/llvm/llvm-project/commit/8b9bbd9ed6f8267ad1e5aa76a8a96b8749cf16d9
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/MachineLICM.cpp
A llvm/test/CodeGen/AArch64/mlicm-implicit-defs.mir
M llvm/test/CodeGen/AMDGPU/copy-to-reg-frameindex.ll
M llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
M llvm/test/CodeGen/X86/ins_subreg_coalesce-3.ll
Log Message:
-----------
MachineLICM: Merge logic for implicit and explicit definitions.
Anatoly Trosinenko found that when hasSideEffect was set to 0 in the
definition of LOADgotAUTH, MultiSource/Benchmarks/Ptrdist/ks/ks test
from llvm-test-suite started to crash. The issue was traced down to
MachineLICM pass placing LOADgotAUTH right after an unrelated copy to
x16 like rewriting this code:
````
bb.0:
renamable $x16 = COPY renamable $x12
B %bb.1
bb.1:
...
/* use $x16 */
...
renamable $x20 = LOADgotAUTH target-flags(aarch64-got) @some_variable, implicit-def dead $x16, implicit-def dead $x17, implicit-def dead $nzcv
/* use $x20 */
...
````
like the following:
````
bb.0:
renamable $x16 = COPY renamable $x12
renamable $x20 = LOADgotAUTH target-flags(aarch64-got) @some_variable, implicit-def dead $x16, implicit-def dead $x17, implicit-def dead $nzcv
B %bb.1
bb.1:
...
/* use $x16 */
...
/* use $x20 */
...
```
The issue was caused by inconsistent logic between implicit and explicit
operand definitions, where the implicit side was incorrectly skipping
checking RUDefs for dead operands, leading to RuledOut not being set
for the X16 operand.
Because there isn't really a semantic difference between implicit and
explicit operands at this point, let's remove the isImplicit check and
adjust the logic to do the same thing in both cases:
- For implicit operands, we now check and update RUDefs in the same way
as explicit operands.
- For explicit operands, we now allow dead operands to be skipped.
Reviewers: arsenm, s-barannikov, atrosinenko
Reviewed By: arsenm, s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/147624
Commit: 702784ca7661fe1d0bc9dc81c0ceabfa82e4a37e
https://github.com/llvm/llvm-project/commit/702784ca7661fe1d0bc9dc81c0ceabfa82e4a37e
Author: Thurston Dang <thurston at google.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512-intrinsics.ll
Log Message:
-----------
[msan] Check mask and rounding mode in handleAVX512VectorConvertFPToInt (#147782)
The checks were missing in "Add handler for
llvm.x86.avx512.mask.cvtps2dq.512
(https://github.com/llvm/llvm-project/pull/147377)
Commit: 0d2b47ae4a01fd97fe479806a45a535ad347eb63
https://github.com/llvm/llvm-project/commit/0d2b47ae4a01fd97fe479806a45a535ad347eb63
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
M llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/function-returns.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
Log Message:
-----------
[AMDGPU][True16][CodeGen] stop emitting spgr_lo16 from isel (#144819)
When true16 is enabled, isel start to emit sgpr_lo16 register when a
trunc/sext i16/i32 is generated, or a salu32 is used by vgpr16 or vice
versa. And this causes a problem as sgpr_lo16 is not fully supported in
the pipeline.
True16 mode works fine in -O3 mode since folding pass remove sgpr_lo16
from the pipeline. However it hit a problem in -O0 mode as folding pass
is skipped.
This patch did:
1. stop emitting sgpr_lo16 from isel
2. update codegen pattern to split uniformed/divergent pattern for
i16/i32 conversion
3. update fix-sgpr-copy pass to address legalization requirement in
true16 mode, update fix-sgpr-copies-f16-true16.mir
test to include all possible combinations
This patch is tested with cts and downstream repo with -O0 testing
Commit: d193a586c0b41192b031ce6a858bec0f855560ad
https://github.com/llvm/llvm-project/commit/d193a586c0b41192b031ce6a858bec0f855560ad
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M lldb/include/lldb/Breakpoint/BreakpointLocation.h
M lldb/source/API/SBBreakpointLocation.cpp
M lldb/source/Breakpoint/Breakpoint.cpp
M lldb/source/Breakpoint/BreakpointLocation.cpp
M lldb/source/Breakpoint/BreakpointLocationList.cpp
M lldb/source/Breakpoint/BreakpointResolverAddress.cpp
M lldb/source/Breakpoint/BreakpointSite.cpp
M lldb/source/Commands/CommandObjectBreakpoint.cpp
M lldb/source/Commands/CommandObjectProcess.cpp
Log Message:
-----------
[lldb] Change breakpoint interfaces for error handling (#146972)
This RP changes some Breakpoint-related interfaces to return errors. On
its own these improvements are small, but they encourage better error
handling going forward. There are a bunch of other candidates, but these
were the functions that I touched while working on #146602.
Commit: 76b1dcfac5da469ca198efcfe0c256ada0b7f0cb
https://github.com/llvm/llvm-project/commit/76b1dcfac5da469ca198efcfe0c256ada0b7f0cb
Author: Santhosh Kumar Ellendula <quic_sellendu at quicinc.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/lldbdap_testcase.py
M lldb/test/API/tools/lldb-dap/memory/TestDAP_memory.py
M lldb/test/API/tools/lldb-dap/memory/main.cpp
M lldb/tools/lldb-dap/CMakeLists.txt
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
A lldb/tools/lldb-dap/Handler/WriteMemoryRequestHandler.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
Log Message:
-----------
[lldb][lldb-dap] Added support for "WriteMemory" request. (#131820)
Added debug adapter support for write memory.
---------
Co-authored-by: Santhosh Kumar Ellendula <sellendu at hu-sellendu-hyd.qualcomm.com>
Co-authored-by: Santhosh Kumar Ellendula <sellendu at hu-sellendu-lv.qualcomm.com>
Commit: 253f8b687344afee77cbc9d49c882c411ee3b414
https://github.com/llvm/llvm-project/commit/253f8b687344afee77cbc9d49c882c411ee3b414
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory.ll
Log Message:
-----------
[VPlan] Support single-scalar VPReplicateRecipes when narrowing IGs.
When narrowing interleave groups, we can treat single scalar
VPReplicateRecipes as already narrowed.
Commit: 06ae0c2a10864e8029ea52b83c46c1839ddb0c1b
https://github.com/llvm/llvm-project/commit/06ae0c2a10864e8029ea52b83c46c1839ddb0c1b
Author: Adam Siemieniuk <adam.siemieniuk at intel.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
M mlir/test/Conversion/VectorToXeGPU/contract-to-xegpu.mlir
Log Message:
-----------
[mlir][xegpu] Remove vector contract to dpas size restriction (#147470)
Removes contraction shape check to allow representing large
workgroup-level workloads in preparation for distribution.
Commit: 4ea0ef2e944762c67395de080f1bc6fe06a0c66b
https://github.com/llvm/llvm-project/commit/4ea0ef2e944762c67395de080f1bc6fe06a0c66b
Author: ChiaHungDuan <chiahungduan at google.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M compiler-rt/lib/scudo/standalone/primary32.h
M compiler-rt/lib/scudo/standalone/primary64.h
Log Message:
-----------
[scudo] Move out the definitions of member functions in primary allocators (#147601)
This greatly improves the readability so that we are able to tell the
design by the concise class definition.
Commit: 2197671109815ed42661fadf5d38f9e510d310c6
https://github.com/llvm/llvm-project/commit/2197671109815ed42661fadf5d38f9e510d310c6
Author: Peter Collingbourne <pcc at google.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/test/CodeGen/AArch64/ptrauth-call.ll
M llvm/test/CodeGen/AArch64/ptrauth-fpac.ll
M llvm/test/CodeGen/AArch64/ptrauth-intrinsic-auth-resign-with-blend.ll
M llvm/test/CodeGen/AArch64/ptrauth-intrinsic-auth-resign.ll
Log Message:
-----------
AArch64: Relax x16/x17 constraint on AUT in certain cases.
On most operating systems, the x16 and x17 registers are not special,
so there is no benefit, and only a code size cost, to constraining AUT to
only using them. Therefore, adjust the backend to only use the AUT pseudo
(renamed AUTx16x17 for clarity) on Darwin platforms. All other platforms
use an unconstrained variant of the pseudo, AUTxMxN, for selection.
Reviewers: ahmedbougacha, kovdan01, atrosinenko
Reviewed By: atrosinenko
Pull Request: https://github.com/llvm/llvm-project/pull/132857
Commit: c4138a24dc254783697f512f053e794fb1c68f88
https://github.com/llvm/llvm-project/commit/c4138a24dc254783697f512f053e794fb1c68f88
Author: Vijay Kandiah <vkandiah at nvidia.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M flang/include/flang/Lower/OpenACC.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-loop.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
Log Message:
-----------
[mlir][acc][flang] Lower nested ACC loops with tile clause as collapsed loops (#147801)
In the case of nested loops, `acc.loop` is meant to subsume all of the
loops that it applies to (when explicitly described as doing so in the
OpenACC specification). So when there is a `acc loop tile(...)` present
on nested Fortran DO loops, `acc.loop` should apply to the `n` loops
that `tile` applies to. This change lowers such nested Fortran loops
with tile clause into a collapsed `acc.loop` with `n` IVs, loop bounds,
and step, in a similar fashion to the current lowering for acc loops
with `collapse` clause.
Commit: 9c4e2dcb56eeb82619762ecfe4ae69ec479de4b3
https://github.com/llvm/llvm-project/commit/9c4e2dcb56eeb82619762ecfe4ae69ec479de4b3
Author: Tomohiro Kashiwada <kikairoya at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M clang/tools/libclang/CMakeLists.txt
Log Message:
-----------
[libclang][Cygwin] Use LLVM_EXPORTED_SYMBOL_FILE (*.def file) for Cygwin (#147278)
This is not mandatory but recommended for completeness and consistency
with MinGW.
Commit: d2adfcaa9e78dd67643601184d18174ab586c176
https://github.com/llvm/llvm-project/commit/d2adfcaa9e78dd67643601184d18174ab586c176
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M flang/lib/Parser/openmp-parsers.cpp
Log Message:
-----------
[flang][OpenMP] Handle multiple spellings in OmpDirectiveNameParser (#147722)
Collect all spellings from all supported OpenMP versions before parsing.
Break up the list of spellings by the initial letter to speed up parsing
a little.
Commit: 2546c6d3f7393f6e2f706de3e9cf539dbc37dfad
https://github.com/llvm/llvm-project/commit/2546c6d3f7393f6e2f706de3e9cf539dbc37dfad
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M flang/lib/Parser/openmp-parsers.cpp
A flang/test/Parser/OpenMP/openmp6-directive-spellings.f90
Log Message:
-----------
[flang][OpenMP] Recognize remaining OpenMP 6.0 spellings in parser (#147723)
Parse OpenMP 6.0 spellings for directives that don't use
OmpDirectiveNameParser.
Commit: 7563531fc935a3e07824c29cd9c870dcdd0621b0
https://github.com/llvm/llvm-project/commit/7563531fc935a3e07824c29cd9c870dcdd0621b0
Author: Andres-Salamanca <andrealebarbaritos at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/test/CIR/CodeGen/bitfields.c
M clang/test/CIR/CodeGen/bitfields.cpp
A clang/test/CIR/IR/bitfield_info.cir
Log Message:
-----------
[CIR] Add test for parsing bitfield_info attribute (#147628)
This PR adds a test for parsing the bitfield_info attribute.
Additionally, it updates the `storage_type` and `is_signed` fields to
match the style used in the incubator ASM format guide.
Commit: 2fc6c73b39a92fda954bb6f4c8e1482502e0eeee
https://github.com/llvm/llvm-project/commit/2fc6c73b39a92fda954bb6f4c8e1482502e0eeee
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
Log Message:
-----------
[LegalizeTypes] Preserve disjoint flag when expanding OR. (#147640)
Commit: 9d8058e3b8287968330383700c49b954518b4daa
https://github.com/llvm/llvm-project/commit/9d8058e3b8287968330383700c49b954518b4daa
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/function/Makefile
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/function/TestDataFormatterStdFunction.py
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/function/main.cpp
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/function/Makefile
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/function/TestLibCxxFunction.py
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/function/main.cpp
Log Message:
-----------
[lldb][test] Move std::function from libcxx to generic directory (#147701)
This just moves the test from `libcxx` to `generic`. There are currently
no `std::function` formatters for libstdc++ so I didn't add a test-case
for it.
Split out from https://github.com/llvm/llvm-project/pull/146740
Commit: 16f046281bf1a11d344eac1bc44d11f3e50e3b5d
https://github.com/llvm/llvm-project/commit/16f046281bf1a11d344eac1bc44d11f3e50e3b5d
Author: sribee8 <sriya.pratipati at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/wchar.yaml
M libc/src/wchar/CMakeLists.txt
A libc/src/wchar/wcslcpy.cpp
A libc/src/wchar/wcslcpy.h
M libc/test/src/wchar/CMakeLists.txt
A libc/test/src/wchar/wcslcpy_test.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/wchar/BUILD.bazel
Log Message:
-----------
[libc] wcslcpy implementation (#146571)
Implemented wcslcpy and tests.
---------
Co-authored-by: Sriya Pratipati <sriyap at google.com>
Commit: 6d00c4297f6714c03ab10f57c10063ebd79264a1
https://github.com/llvm/llvm-project/commit/6d00c4297f6714c03ab10f57c10063ebd79264a1
Author: Corentin Jabot <corentinjabot at gmail.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/Sema/SemaLambda.cpp
M clang/test/CodeGenCXX/mangle-requires.cpp
M clang/test/CodeGenCXX/ms-mangle-requires.cpp
M clang/test/SemaTemplate/concepts-lambda.cpp
Log Message:
-----------
[Clang] Do not skip over `RequiresExprBodyDecl` when creating lambdas (#147764)
When we create a lambda, we would skip over declaration contexts
representing a require expression body, which would lead to wrong
lookup.
Note that I wasn't able to establish why the code
in `Sema::createLambdaClosureType` was there to begin with (it's not
exactly recent)
The changes to mangling only ensure the status quo is preserved and do
not attempt to address the known issues of
mangling lambdas in require clauses.
In particular the itanium mangling is consistent with Clang before this
patch but differs from GCC's.
Fixes #147650
Commit: 9337594e3346e15b5bc90b5372b8b482aa5af37f
https://github.com/llvm/llvm-project/commit/9337594e3346e15b5bc90b5372b8b482aa5af37f
Author: Alex Langford <alangford at apple.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/Support/Unix/Signals.inc
Log Message:
-----------
[Support] Don't re-raise signals sent from kernel (#145759)
When an llvm tool crashes (e.g. from a segmentation fault),
SignalHandler will re-raise the signal. The effect is that crash reports
now contain SignalHandler in the stack trace. The crash reports are
still useful, but the presence of SignalHandler can confuse tooling and
automation that deduplicate or analyze crash reports.
rdar://150464802
Commit: 2fc4a4a9d3a87a9e11c48ef25522aa17c2a71003
https://github.com/llvm/llvm-project/commit/2fc4a4a9d3a87a9e11c48ef25522aa17c2a71003
Author: Nilanjana Basu <nilanjana.basu87 at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/pgo-sample-use-profi.c
Log Message:
-----------
[Driver][SamplePGO] Enable -fsample-profile-use-profi (#146795)
Since profile inference improves sample coverage, it should be turned on by default.
Commit: b12fcff4ffd74a37eea7877ff42d0990c07a19ab
https://github.com/llvm/llvm-project/commit/b12fcff4ffd74a37eea7877ff42d0990c07a19ab
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M libcxx/utils/ci/docker-compose.yml
Log Message:
-----------
[libcxx] Bump Container Runner Version (#147831)
This patch bumps the runner version from v3.222.0 to v3.226.0 as
v3.222.0 is too old at this point to connect to Github. This is needed
for the new premerge system given we are directly using this container.
This did not impact the existing libc++ CI as the runner was contained
in a separate container image.
Commit: f1acd69bfed039e8fc0e5e5cc44e3111b8081ad2
https://github.com/llvm/llvm-project/commit/f1acd69bfed039e8fc0e5e5cc44e3111b8081ad2
Author: sribee8 <sriya.pratipati at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M libc/src/__support/wctype_utils.h
Log Message:
-----------
[libc] Added internal wctype functions (#147798)
Copy pasted the ctype equivalents
---------
Co-authored-by: Sriya Pratipati <sriyap at google.com>
Commit: 071e30220db187c47131a02ce36c3697f61ce393
https://github.com/llvm/llvm-project/commit/071e30220db187c47131a02ce36c3697f61ce393
Author: Bogdan Vetrenko <68546200+b0gdnv at users.noreply.github.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M libc/src/__support/CPP/atomic.h
Log Message:
-----------
[libc][NFC] fix comment typo ("documentation") (#147836)
Commit: 7f3afab9181d83f92771293ad3b6c00ac62800fd
https://github.com/llvm/llvm-project/commit/7f3afab9181d83f92771293ad3b6c00ac62800fd
Author: Peter Collingbourne <pcc at google.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/Support/CMakeLists.txt
M llvm/lib/Support/SipHash.cpp
M llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn
A third-party/siphash/include/siphash/SipHash.h
Log Message:
-----------
Extract SipHash implementation into a header.
This is so that we'll be able to use it in compiler-rt as well.
Dependencies on LLVM Support were removed from the header by restoring
code from the original SipHash implementation.
Reviewers: kuhar, dwblaikie, ahmedbougacha
Reviewed By: dwblaikie
Pull Request: https://github.com/llvm/llvm-project/pull/134197
Commit: ddf9b91f9fed8654c4649881f7db51f1e474701f
https://github.com/llvm/llvm-project/commit/ddf9b91f9fed8654c4649881f7db51f1e474701f
Author: Diego Caballero <dieg0ca6aller0 at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M mlir/include/mlir/Dialect/Vector/Transforms/LoweringPatterns.h
M mlir/include/mlir/Dialect/Vector/Transforms/Passes.h
M mlir/include/mlir/Dialect/Vector/Transforms/Passes.td
M mlir/lib/Dialect/Vector/Transforms/CMakeLists.txt
A mlir/lib/Dialect/Vector/Transforms/LowerVectorToFromElementsToShuffleTree.cpp
A mlir/test/Dialect/Vector/vector-tofrom-elements-to-shuffle-tree-transforms.mlir
Log Message:
-----------
[mlir][Vector] Add `vector.shuffle` tree transformation (#145740)
This PR adds a new transformation that turns sequences of `vector.to_elements` and `vector.from_elements` into a binary tree of `vector.shuffle` operations.
(Related RFC:
https://discourse.llvm.org/t/rfc-adding-vector-to-elements-op-to-the-vector-dialect/86779).
Example:
```
%0:4 = vector.to_elements %a : vector<4xf32>
%1:4 = vector.to_elements %b : vector<4xf32>
%2:4 = vector.to_elements %c : vector<4xf32>
%3 = vector.from_elements %0#0, %0#1, %0#2, %0#3,
%1#0, %1#1, %1#2, %1#3,
%2#0, %2#1, %2#2, %2#3 : vector<12xf32>
==>
%0 = vector.shuffle %a, %b [0, 1, 2, 3, 4, 5, 6, 7] : vector<4xf32>, vector<4xf32>
%1 = vector.shuffle %c, %c [0, 1, 2, 3, -1, -1, -1, -1] : vector<4xf32>, vector<4xf32>
%2 = vector.shuffle %0, %1 [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11] : vector<8xf32>, vector<8xf32>
```
The algorithm leverages the structured extraction/insertion information
of `vector.to_elements` and `vector.from_elements` operations and builds
a set of intervals to determine the vector length that should be used at
each level of the tree to combine the level inputs in pairs.
There are a few improvements that can be implemented in the future, such
as shuffle mask compression to avoid unnecessarily large vector lengths
with poison values, but I decided to keep things "simpler" and spend
more time documenting the different steps of the algorithm so that
people can follow along.
Commit: 7c16a31aa593b9cc750e61b260c27ade74edb1dd
https://github.com/llvm/llvm-project/commit/7c16a31aa593b9cc750e61b260c27ade74edb1dd
Author: Alex Sepkowski <alexsepkowski at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Format/Format.cpp
M clang/lib/Lex/Lexer.cpp
M clang/lib/Sema/SemaExpr.cpp
Log Message:
-----------
Address a handful of C4146 compiler warnings where literals can be replaced with std::numeric_limits (#147623)
This PR addresses instances of compiler warning C4146 that can be
replaced with std::numeric_limits. Specifically, these are cases where a
literal such as '-1ULL' was used to assign a value to a uint64_t
variable. The intent is much cleaner if we use the appropriate
std::numeric_limits value<Type>::max() for these cases.
Addresses #147439
Commit: 20a68c6179da4bc1899e71809ff45e9dce5dd150
https://github.com/llvm/llvm-project/commit/20a68c6179da4bc1899e71809ff45e9dce5dd150
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
Log Message:
-----------
[RISCV] Remove BREV8 and ORC_B from hasAllNBitUsers in RISCVOptWInstrs. (#147830)
These instructions operate on bytes so we need to round the demanded
bits up to the nearest byte which we aren't doing. I think we forgot to
update this when we changed from hasAllWUsers to hasNBitUsers.
We don't have any test case for these instruction so remove them until
we can put together a test.
Commit: 5b1db59fb87b4146f827d17396f54ef30ae0dc40
https://github.com/llvm/llvm-project/commit/5b1db59fb87b4146f827d17396f54ef30ae0dc40
Author: Peter Collingbourne <pcc at google.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
M compiler-rt/cmake/builtin-config-ix.cmake
M compiler-rt/lib/builtins/CMakeLists.txt
A compiler-rt/lib/builtins/aarch64/emupac.cpp
A compiler-rt/test/builtins/Unit/aarch64/emupac.c
M llvm/utils/gn/secondary/compiler-rt/lib/builtins/BUILD.gn
M llvm/utils/gn/secondary/compiler-rt/lib/builtins/sources.gni
M llvm/utils/gn/secondary/compiler-rt/test/builtins/BUILD.gn
Log Message:
-----------
compiler-rt: Introduce runtime functions for emulated PAC.
The emulated PAC runtime functions emulate the ARMv8.3a pointer
authentication instructions and are intended for use in heterogeneous
testing environments. For more information, see the associated RFC:
https://discourse.llvm.org/t/rfc-emulated-pac/85557
Reviewers: llvm-beanz, petrhosek
Pull Request: https://github.com/llvm/llvm-project/pull/133530
Commit: 574b66f2412f2466e1bd5e4d195f856a87c5ded0
https://github.com/llvm/llvm-project/commit/574b66f2412f2466e1bd5e4d195f856a87c5ded0
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll
Log Message:
-----------
[RISCV] Use Selection::haveNoCommonBitsSet in RISCVDAGToDAGISel::orDisjoint. (#147838)
Commit: a37f0a00a2edb0696f1055222610dc246f49b892
https://github.com/llvm/llvm-project/commit/a37f0a00a2edb0696f1055222610dc246f49b892
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
A llvm/utils/gn/secondary/llvm/lib/DWARFCFIChecker/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-mc/BUILD.gn
Log Message:
-----------
gn build: Port db03408b2445
Commit: cd65f8bf17ecfc9896fd9913905f182ad7ce1446
https://github.com/llvm/llvm-project/commit/cd65f8bf17ecfc9896fd9913905f182ad7ce1446
Author: Kazu Hirata <kazu at google.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/LowerVectorToFromElementsToShuffleTree.cpp
Log Message:
-----------
[mlir] Fix a warning
This patch fixes:
mlir/lib/Dialect/Vector/Transforms/LowerVectorToFromElementsToShuffleTree.cpp:42:20:
error: unused variable 'kIndScale' [-Werror,-Wunused-const-variable]
Commit: 20daa73a0962efd22cee3bbf327ee35b22add39d
https://github.com/llvm/llvm-project/commit/20daa73a0962efd22cee3bbf327ee35b22add39d
Author: Mingming Liu <mingmingl at google.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/include/llvm/ProfileData/SampleProf.h
M llvm/lib/ProfileData/SampleProf.cpp
M llvm/lib/ProfileData/SampleProfReader.cpp
M llvm/lib/ProfileData/SampleProfWriter.cpp
Log Message:
-----------
[NFC]Codestyle changes for SampleFDO library (#147840)
* Introduce an error code for illegal_line_offset in sampleprof_error
namespace, and use it for line offset parsing error.
* Add `const` for `LineLocation::serialize`.
* Use structured binding, make_first/second_range in loops.
I'm working on a [sample-profile format
change](https://github.com/llvm/llvm-project/compare/users/mingmingl-llvm/samplefdo-profile-format)
to extend SampleFDO profile with vtable profiles. And this change splits
the non-functional changes.
Commit: ac4a38e9bd573a173432b89cbef7cce7a48e7907
https://github.com/llvm/llvm-project/commit/ac4a38e9bd573a173432b89cbef7cce7a48e7907
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/commute.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/reduce-fadd.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/slp-fma-loss.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/revec.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/X86/dot-product.ll
M llvm/test/Transforms/SLPVectorizer/extracts-with-undefs.ll
Log Message:
-----------
[SLP] Emit reduction instead of 2 extracts + scalar op, when vectorizing operands (#147583)
Added emission of the 2-element reduction instead of 2 extracts + scalar
op, when trying to vectorize operands of the instruction, if it is more
profitable.
Commit: d5436b0b951abe5ee724bed6617e76e736376e09
https://github.com/llvm/llvm-project/commit/d5436b0b951abe5ee724bed6617e76e736376e09
Author: sribee8 <sriya.pratipati at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/wchar.yaml
M libc/src/wchar/CMakeLists.txt
A libc/src/wchar/wcslcat.cpp
A libc/src/wchar/wcslcat.h
M libc/test/src/wchar/CMakeLists.txt
A libc/test/src/wchar/wcslcat_test.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/wchar/BUILD.bazel
Log Message:
-----------
[libc] wcslcat implementation (#146588)
implemented wcslcat and tests.
---------
Co-authored-by: Sriya Pratipati <sriyap at google.com>
Commit: 03b0ae8da8c4df28ad197ef21619288ead085687
https://github.com/llvm/llvm-project/commit/03b0ae8da8c4df28ad197ef21619288ead085687
Author: Vincent Lee <leevince at meta.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
A llvm/utils/mlgo-utils/combine_training_corpus.py
A llvm/utils/mlgo-utils/extract_ir.py
A llvm/utils/mlgo-utils/make_corpus.py
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[mlgo-utils] Create symlinked entrypoints in root directory (#146981)
These scripts belong in the `mlgo-utils` directory when directly used
with python3. But since they are also used to package with pip, symlink
the entrypoint scripts to mlgo-utils directory. Adjust the bazel paths
to account for this as well. This loosely follows the same structure as lit.
Verified that I was also able to build the package successfully and use
the script.
Commit: 28aa5a64efcb34fa2814fb87ee191514157af186
https://github.com/llvm/llvm-project/commit/28aa5a64efcb34fa2814fb87ee191514157af186
Author: Wenju He <wenju.he at intel.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
A libclc/clc/include/clc/workitem/clc_get_global_id.h
A libclc/clc/include/clc/workitem/clc_get_global_offset.h
A libclc/clc/include/clc/workitem/clc_get_global_size.h
A libclc/clc/include/clc/workitem/clc_get_group_id.h
A libclc/clc/include/clc/workitem/clc_get_local_id.h
A libclc/clc/include/clc/workitem/clc_get_local_linear_id.h
A libclc/clc/include/clc/workitem/clc_get_local_size.h
A libclc/clc/include/clc/workitem/clc_get_max_sub_group_size.h
A libclc/clc/include/clc/workitem/clc_get_num_groups.h
A libclc/clc/include/clc/workitem/clc_get_num_sub_groups.h
A libclc/clc/include/clc/workitem/clc_get_sub_group_id.h
A libclc/clc/include/clc/workitem/clc_get_sub_group_local_id.h
A libclc/clc/include/clc/workitem/clc_get_sub_group_size.h
A libclc/clc/include/clc/workitem/clc_get_work_dim.h
M libclc/clc/lib/amdgcn/SOURCES
A libclc/clc/lib/amdgcn/workitem/clc_get_global_offset.cl
A libclc/clc/lib/amdgcn/workitem/clc_get_global_size.cl
A libclc/clc/lib/amdgcn/workitem/clc_get_group_id.cl
A libclc/clc/lib/amdgcn/workitem/clc_get_local_id.cl
A libclc/clc/lib/amdgcn/workitem/clc_get_work_dim.cl
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/workitem/clc_get_local_linear_id.cl
A libclc/clc/lib/generic/workitem/clc_get_num_sub_groups.cl
A libclc/clc/lib/generic/workitem/clc_get_sub_group_id.cl
A libclc/clc/lib/generic/workitem/clc_get_sub_group_size.cl
A libclc/clc/lib/ptx-nvidiacl/SOURCES
A libclc/clc/lib/ptx-nvidiacl/workitem/clc_get_global_id.cl
A libclc/clc/lib/ptx-nvidiacl/workitem/clc_get_group_id.cl
A libclc/clc/lib/ptx-nvidiacl/workitem/clc_get_local_id.cl
A libclc/clc/lib/ptx-nvidiacl/workitem/clc_get_local_size.cl
A libclc/clc/lib/ptx-nvidiacl/workitem/clc_get_max_sub_group_size.cl
A libclc/clc/lib/ptx-nvidiacl/workitem/clc_get_num_groups.cl
A libclc/clc/lib/ptx-nvidiacl/workitem/clc_get_sub_group_local_id.cl
A libclc/opencl/include/clc/opencl/workitem/get_local_linear_id.h
A libclc/opencl/include/clc/opencl/workitem/get_max_sub_group_size.h
A libclc/opencl/include/clc/opencl/workitem/get_num_sub_groups.h
A libclc/opencl/include/clc/opencl/workitem/get_sub_group_id.h
A libclc/opencl/include/clc/opencl/workitem/get_sub_group_local_id.h
A libclc/opencl/include/clc/opencl/workitem/get_sub_group_size.h
M libclc/opencl/lib/amdgcn/workitem/get_global_offset.cl
M libclc/opencl/lib/amdgcn/workitem/get_global_size.cl
M libclc/opencl/lib/amdgcn/workitem/get_group_id.cl
M libclc/opencl/lib/amdgcn/workitem/get_local_id.cl
M libclc/opencl/lib/amdgcn/workitem/get_work_dim.cl
M libclc/opencl/lib/ptx-nvidiacl/SOURCES
M libclc/opencl/lib/ptx-nvidiacl/workitem/get_global_id.cl
M libclc/opencl/lib/ptx-nvidiacl/workitem/get_group_id.cl
M libclc/opencl/lib/ptx-nvidiacl/workitem/get_local_id.cl
A libclc/opencl/lib/ptx-nvidiacl/workitem/get_local_linear_id.cl
M libclc/opencl/lib/ptx-nvidiacl/workitem/get_local_size.cl
A libclc/opencl/lib/ptx-nvidiacl/workitem/get_max_sub_group_size.cl
M libclc/opencl/lib/ptx-nvidiacl/workitem/get_num_groups.cl
A libclc/opencl/lib/ptx-nvidiacl/workitem/get_num_sub_groups.cl
A libclc/opencl/lib/ptx-nvidiacl/workitem/get_sub_group_id.cl
A libclc/opencl/lib/ptx-nvidiacl/workitem/get_sub_group_local_id.cl
A libclc/opencl/lib/ptx-nvidiacl/workitem/get_sub_group_size.cl
Log Message:
-----------
[libclc] Declare workitem built-ins in clc, move ptx-nvidiacl workitem built-ins into clc (#144333)
Changes in this PR:
* Declare most of workitem functions in clc and opencl folders.
* Call clc workitem function in corresponding OpenCL workitem function.
* Move ptx-nvidiacl workitem built-in implementations into clc.
* Move a few amdgcn workitem built-in implementations into clc.
* Include only needed headers in OpenCL workitem functions.
* Implement get_local_linear_id, get_max_sub_group_size,
get_num_sub_groups,
get_sub_group_id, get_sub_group_local_id, get_sub_group_size for
ptx-nvidiacl.
llvm-diff shows this PR adds a few new symbols to nvptx64--nvidiacl.bc.
llvm-diff shows no change to amdgcn--amdhsa.bc, nvptx--.bc and
nvptx64--.bc.
Commit: d286540734fe03232d971d0e7c52f88464e98928
https://github.com/llvm/llvm-project/commit/d286540734fe03232d971d0e7c52f88464e98928
Author: Jake Egan <Jake.egan at ibm.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M compiler-rt/lib/asan/asan_allocator.h
M compiler-rt/lib/lsan/lsan_allocator.h
M compiler-rt/lib/msan/msan_allocator.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_allocator_internal.h
M compiler-rt/lib/sanitizer_common/sanitizer_platform.h
M compiler-rt/lib/tsan/rtl/tsan_rtl.h
Log Message:
-----------
[sanitizer_common] Introduce SANITIZER_MMAP_BEGIN macro (#147645)
To prepare for other platforms, such as 64-bit AIX, that have a non-zero
mmap beginning address.
---------
Co-authored-by: David Justo <david.justo.1996 at gmail.com>
Commit: 75524dee18c34496b427060a5c394287f2327ddf
https://github.com/llvm/llvm-project/commit/75524dee18c34496b427060a5c394287f2327ddf
Author: Chao Chen <chao.chen at intel.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
M mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp
M mlir/test/Conversion/VectorToXeGPU/load-to-xegpu.mlir
M mlir/test/Conversion/VectorToXeGPU/store-to-xegpu.mlir
M mlir/test/Conversion/VectorToXeGPU/transfer-read-to-xegpu.mlir
M mlir/test/Conversion/VectorToXeGPU/transfer-write-to-xegpu.mlir
M mlir/test/Dialect/XeGPU/invalid.mlir
M mlir/test/Dialect/XeGPU/ops.mlir
M mlir/test/Dialect/XeGPU/xegpu-blocking.mlir
M mlir/test/lib/Dialect/XeGPU/TestXeGPUTransforms.cpp
Log Message:
-----------
[mlir][xegpu] Relax rank restriction of TensorDescType (#145916)
Commit: 7c66099545e84374d1df18da168ac12a4a9422cb
https://github.com/llvm/llvm-project/commit/7c66099545e84374d1df18da168ac12a4a9422cb
Author: Thurston Dang <thurston at google.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/X86/avx-intrinsics-x86.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512-intrinsics-upgrade.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512bw-intrinsics-upgrade.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512bw-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512vl-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/x86-vpermi2.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/avx-intrinsics-i386.ll
Log Message:
-----------
[msan] Simplify 'maskedCheckAVXIndexShadow' (#147839)
The current instrumentation has more or and element extraction than a
coal mine:
```
[[TMP10:%.*]] = extractelement <16 x i32> [[TMP9]], i64 0
[[TMP11:%.*]] = and i32 [[TMP10]], 15
[[TMP43:%.*]] = or i32 [[TMP10]], [[TMP11]]
[[TMP12:%.*]] = extractelement <16 x i32> [[TMP9]], i64 1
[[TMP13:%.*]] = and i32 [[TMP12]], 15
[[TMP44:%.*]] = or i32 [[TMP12]], [[TMP13]]
...
[[TMP40:%.*]] = extractelement <16 x i32> [[TMP9]], i64 15
[[TMP41:%.*]] = and i32 [[TMP40]], 15
[[TMP57:%.*]] = or i32 [[TMP40]], [[TMP41]]
[[_MSCMP:%.*]] = icmp ne i32 [[TMP57]], 0
br i1 [[_MSCMP]], label [[TMP102:%.*]], label [[TMP103:%.*]], !prof [[PROF1]]
```
Simplify it to:
```
[[TMP10:%.*]] = trunc <16 x i32> [[T]] to <16 x i4>
[[TMP12:%.*]] = bitcast <16 x i4> [[TMP10]] to i64
[[_MSCMP:%.*]] = icmp ne i64 [[TMP12]], 0
br i1 [[_MSCMP]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]
```
Commit: e8a50a2568bf7c8d97f06290e03db3ca8eb2f2d3
https://github.com/llvm/llvm-project/commit/e8a50a2568bf7c8d97f06290e03db3ca8eb2f2d3
Author: A. Jiang <de34 at live.cn>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M libcxx/docs/Status/Cxx2cIssues.csv
M libcxx/docs/Status/Cxx2cPapers.csv
Log Message:
-----------
[libc++][docs] Update paper & LWG issue lists after 2025-06 meeting (#147668)
CWG papers requiring library support are also listed.
Commit: 84eeb2348440f448c4dc9582237d1612c950572e
https://github.com/llvm/llvm-project/commit/84eeb2348440f448c4dc9582237d1612c950572e
Author: Jim Lin <jim at andestech.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M clang/include/clang/Basic/riscv_andes_vector.td
A clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c
A clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c
A clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c
A clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c
A clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c
A clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c
A clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c
A clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c
Log Message:
-----------
[RISCV] Implement intrinsics for XAndesVSIntLoad (#147767)
This patch implements clang intrinsic support for XAndesVSIntLoad.
The document for the intrinsics can be found at:
https://github.com/andestech/andes-vector-intrinsic-doc/blob/ast-v5_4_0-release-v5/auto-generated/andes-v5/intrinsic_funcs/04_andes_vector_int4_load_extension.adoc
Co-authored-by: Lino Hsing-Yu Peng <linopeng at andestech.com>
Commit: 2eab6f9bb2b3dd0cf05021939accca75cfb79994
https://github.com/llvm/llvm-project/commit/2eab6f9bb2b3dd0cf05021939accca75cfb79994
Author: Jim Lin <jim at andestech.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
R clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvtbf16.c
R clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvtbf16.c
R clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvtbf16.c
R clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvtbf16.c
R clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvtbf16.c
R clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvtbf16.c
R clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvtbf16.c
R clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c
Log Message:
-----------
[RISCV] Move the intrinsic tests for vfwcvtbf16 and vfncvtbf16 to zvfbfmin directory. NFC.
A follow-up commit for #147644.
Commit: 1ae99f5894d70d11545f3a657665e5a3b8437d9a
https://github.com/llvm/llvm-project/commit/1ae99f5894d70d11545f3a657665e5a3b8437d9a
Author: Fangrui Song <i at maskray.me>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
Log Message:
-----------
[msan] Fix -Wunused-but-set-variable after #147839
Commit: f1c4df5b7bb79efb3e9be7fa5f8176506499d0a6
https://github.com/llvm/llvm-project/commit/f1c4df5b7bb79efb3e9be7fa5f8176506499d0a6
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M compiler-rt/lib/builtins/int_types.h
Log Message:
-----------
builtins: Speculative MSVC fix.
Attempt to fix these build failures:
https://lab.llvm.org/buildbot/#/builders/107/builds/12601
The suspected cause is that #133530 caused us to start
passing -std:c11 to MSVC, which activated this code path
that uses _Complex, which MSVC does not support. See:
https://learn.microsoft.com/en-us/cpp/c-runtime-library/complex-math-support
Fix it by also checking _MSC_VER.
Commit: c86c815fc57c098ba14576fe2bb189da1dfc820d
https://github.com/llvm/llvm-project/commit/c86c815fc57c098ba14576fe2bb189da1dfc820d
Author: Marco Vitale <53484928+mrcvtl at users.noreply.github.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/Decl.h
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/lib/Sema/SemaStmt.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/test/SemaCXX/attr-lifetimebound.cpp
A clang/test/SemaCXX/range-for-lifetime-cxx23.cpp
Log Message:
-----------
[Sema] Fix lifetime extension for temporaries in range-based for loops in C++23 (#145164)
C++23 mandates that temporaries used in range-based for loops are
lifetime-extended
to cover the full loop. This patch adds a check for loop variables and
compiler-
generated `__range` bindings to apply the correct extension.
Includes test cases based on examples from CWG900/P2644R1.
Fixes https://github.com/llvm/llvm-project/issues/109793
Commit: 697beb3f174c530de2af7124cfe2dcedea11c487
https://github.com/llvm/llvm-project/commit/697beb3f174c530de2af7124cfe2dcedea11c487
Author: Boyao Wang <wangboyao at bytedance.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/BPF/BPFISelLowering.h
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.h
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsISelLowering.h
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.h
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
Log Message:
-----------
[TargetLowering] Change getOptimalMemOpType and findOptimalMemOpLowering to take LLVM Context (#147664)
Add LLVM Context to getOptimalMemOpType and findOptimalMemOpLowering. So
that we can use EVT::getVectorVT to generate EVT type in
getOptimalMemOpType.
Related to [#146673](https://github.com/llvm/llvm-project/pull/146673).
Commit: 831b198c65ced51e084baf92e4e6de911e000857
https://github.com/llvm/llvm-project/commit/831b198c65ced51e084baf92e4e6de911e000857
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/docs/RISCV/RISCVVectorExtension.rst
Log Message:
-----------
[RISCV][Docs] Add bfloat types to RISCVVectorExtension.rst. NFC (#147867)
Commit: c4f18d6874df380eda3be224eaae6c24e996bbdf
https://github.com/llvm/llvm-project/commit/c4f18d6874df380eda3be224eaae6c24e996bbdf
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/utils/remote-exec.py
Log Message:
-----------
remote-exec: Only copy command line arguments which name files that exist.
Speculative fix for failing buildbot:
https://lab.llvm.org/buildbot/#/builders/193/builds/8961
Commit: 378e9bb7e06c67d8235a8cb5bfb325b63d2ba319
https://github.com/llvm/llvm-project/commit/378e9bb7e06c67d8235a8cb5bfb325b63d2ba319
Author: darkbuck <michael.hliao at gmail.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M clang/test/CIR/Lowering/select.cir
M clang/tools/cir-translate/cir-translate.cpp
Log Message:
-----------
[cir-translate] Fix crash issue where the data layout string is missing (#147209)
- Targets like 'aarch64' or 'arm' only populate the data layout string
after the constructor. Need to call 'CreateTargetInfo' to setup them
properly.
Commit: 617af3cc50c48ec71889b893dd2658764f19abce
https://github.com/llvm/llvm-project/commit/617af3cc50c48ec71889b893dd2658764f19abce
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
A llvm/test/CodeGen/AArch64/exception-handling-windows-elf.ll
M llvm/unittests/TargetParser/TripleTest.cpp
Log Message:
-----------
AArch64: Base MCAsmInfo type on binary format before OS (#147875)
Fixes asserting with windows-elf triples. Should fix regression
reported in https://github.com/llvm/llvm-project/pull/147225#issuecomment-3054190938
I'm not sure this is a valid triple, but I'm guessing the MCJIT usage
is an accident. This does change the behavior from trying to use WinEH
to DwarfCFI; however the backend crashes with WinEH so I'm assuming following
ELF is the more correct option.
Commit: fd894f6e9ed069a8baf0fc694f4063585fab9ae1
https://github.com/llvm/llvm-project/commit/fd894f6e9ed069a8baf0fc694f4063585fab9ae1
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt
Log Message:
-----------
[AMDGPU] gfx1250 MC support for v_mov_b64 (#147859)
It is incomplete in terms of the DPP diagnistics, that is much
more involved change.
Commit: 69ff8537296339babc72ae075f3e78a68d1b6816
https://github.com/llvm/llvm-project/commit/69ff8537296339babc72ae075f3e78a68d1b6816
Author: Jim Lin <jim at andestech.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
R clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmaccbf16.c
R clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmaccbf16.c
R clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmaccbf16.c
R clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmaccbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c
Log Message:
-----------
[RISCV] Move the intrinsic tests for vfwmaccbf16 to zvfbfwma directory. NFC.
A follow-up commit for #147644.
Commit: 00a85e57049ee637a6089b2c696d5e37db8cd47b
https://github.com/llvm/llvm-project/commit/00a85e57049ee637a6089b2c696d5e37db8cd47b
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
A llvm/test/MC/AMDGPU/gfx1250_asm_salu_lit64.s
A llvm/test/MC/AMDGPU/gfx1250_asm_valu_lit64.s
A llvm/test/MC/AMDGPU/gfx1250_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_salu_lit64.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_valu_lit64.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
Log Message:
-----------
[AMDGPU] gfx1250: MC support for 64-bit literals (#147861)
Commit: 36cbd43ae8d5a5274ae3193b6383fff2ba9671f4
https://github.com/llvm/llvm-project/commit/36cbd43ae8d5a5274ae3193b6383fff2ba9671f4
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/AST/ByteCode/new-delete.cpp
Log Message:
-----------
[clang][bytecode] Check new/delete mismatch earlier (#147732)
This fixes a mismatch in diagnostic output with the current intepreter.
Commit: 10f782456eabbe8d36632e3ecb93436bd7ab8385
https://github.com/llvm/llvm-project/commit/10f782456eabbe8d36632e3ecb93436bd7ab8385
Author: David Green <david.green at arm.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/cmp.ll
M llvm/test/Analysis/CostModel/AArch64/select.ll
M llvm/test/Analysis/CostModel/AArch64/vector-select.ll
Log Message:
-----------
[AArch64] Enable other cost kinds for getCmpSelInstrCost. (#144375)
This removes the CostKind == TCK_RecipThroughput limitation from
getCmpSelInstrCost, allowing it to return more accurate costs for CodeSize and
Lat / SizeLat. Especially for larger vectors under CodeSize, the returned costs
are currently 1, not the legalization cost.
Commit: b57df56b48145f0985c5cab4e4f282e512c89546
https://github.com/llvm/llvm-project/commit/b57df56b48145f0985c5cab4e4f282e512c89546
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSchedAndes45.td
M llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td
M llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
M llvm/lib/Target/RISCV/RISCVSchedRocket.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
M llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
M llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td
M llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td
M llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
M llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
M llvm/lib/Target/RISCV/RISCVSchedule.td
Log Message:
-----------
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
There will be more schedule definitions for vendor extentions and
we need to add these `UnsupportedSchedXXX` to exsiting models every
time we add new schedule definitions.
The fact is that each vendor will barely implement other vendors'
extensions, so we can package these definitions into one.
Commit: d72d84cb0df40019a0a5abaf836b38c8e46e4827
https://github.com/llvm/llvm-project/commit/d72d84cb0df40019a0a5abaf836b38c8e46e4827
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/test/Sema/constant_builtins_vector.cpp
Log Message:
-----------
[clang][bytecode] Implement missing elementwise builtins (#147892)
Commit: 20becf373edcf9d568f8904c2b473e6b48500787
https://github.com/llvm/llvm-project/commit/20becf373edcf9d568f8904c2b473e6b48500787
Author: Luke Lau <luke at igalia.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
Log Message:
-----------
[TTI] Move vp.{select,merge} costing from RISCV to BasicTTIImpl. NFC (#147870)
Move the costing to the generic implementation in BasicTTIImpl since it
just falls back to the non-vp costing.
Also pass through the OperandValueInfo if using value based costing, but
I don't believe this affects the result for any in-tree target
currently.
Commit: 213735487ea0c682a3e8c3d5a78a034e50fd5a0a
https://github.com/llvm/llvm-project/commit/213735487ea0c682a3e8c3d5a78a034e50fd5a0a
Author: Elvis Wang <elvis.wang at sifive.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
A llvm/test/Analysis/CostModel/RISCV/cast-sat.ll
Log Message:
-----------
[TTI] Check type legalization of both src and result for fpto{u|s}i.sat. (#147657)
For the cast instructions such ass `fptoui.sat`, `fptosi.sat`, need to
check
both type of the source and the result type can be lowering legally. If
one of them is invalid, return invalid cost.
--
Fixes https://github.com/llvm/llvm-project/issues/142973.
---------
Co-authored-by: Craig Topper <craig.topper at sifive.com>
Commit: 8b171a08db946ad382a3726d9deb9420d43a59ee
https://github.com/llvm/llvm-project/commit/8b171a08db946ad382a3726d9deb9420d43a59ee
Author: A. Jiang <de34 at live.cn>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M libcxx/docs/ReleaseNotes/21.rst
M libcxx/include/future
R libcxx/test/libcxx/thread/futures/futures.task/type.depr.verify.cpp
R libcxx/test/libcxx/thread/futures/futures.task/types.pass.cpp
A libcxx/test/std/thread/futures/futures.task/futures.task.members/type.verify.cpp
Log Message:
-----------
[libc++] Remove the `packaged_task::result_type` extension (#147671)
No escape hatch added, as there doesn't seem anyone critically relying
on this.
Commit: c8fbcb659051288adbf29aa6be43f4980b22ceb2
https://github.com/llvm/llvm-project/commit/c8fbcb659051288adbf29aa6be43f4980b22ceb2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
A llvm/test/CodeGen/Hexagon/llvm.sincos.ll
Log Message:
-----------
Hexagon: Add sincos intrinsic test (#147474)
Commit: 28f093517232fd3c1dff6103e7cc944a8e8253bc
https://github.com/llvm/llvm-project/commit/28f093517232fd3c1dff6103e7cc944a8e8253bc
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M libcxx/include/__node_handle
Log Message:
-----------
[libc++][NFC] Remove special handling for __hash_value_type in <__node_handle> (#147271)
We're not instantiating `__hash_value_type` anymore, so we don't need
any special handling of it here.
Commit: 30f8c64b1d14269fef5d11c1be69315426025dfe
https://github.com/llvm/llvm-project/commit/30f8c64b1d14269fef5d11c1be69315426025dfe
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M libcxx/include/__memory/construct_at.h
Log Message:
-----------
[libc++][NFC] Simplify std::__destroy_at a bit (#147025)
Commit: 9052977c35832776f3154bdb7a4976a253bd3fb6
https://github.com/llvm/llvm-project/commit/9052977c35832776f3154bdb7a4976a253bd3fb6
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M libcxx/include/__type_traits/invoke.h
Log Message:
-----------
[libc++] Implement the public invoke API in terms of the libc++-internal API (#146334)
This adds one additional variable template to the libc++-internal API.
This allows us to implement the public API once instead of twice.
Commit: afcf76bda18c09cffd88cb562768385f97ebf894
https://github.com/llvm/llvm-project/commit/afcf76bda18c09cffd88cb562768385f97ebf894
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M libcxx/include/__hash_table
M libcxx/include/__tree
M libcxx/include/ext/hash_map
M libcxx/include/ext/hash_set
M libcxx/include/map
M libcxx/include/set
M libcxx/include/unordered_map
M libcxx/include/unordered_set
M libcxx/test/std/containers/map_allocator_requirement_test_templates.h
M libcxx/test/std/containers/set_allocator_requirement_test_templates.h
Log Message:
-----------
[libc++] Fix insert() calling incorrect constructors (#146231)
This fixes `insert()` calling the wrong `allocator_traits::construct` in
the associative containers by removing the special handling that lead to
the inconsistencty inside `__tree` and `__hash_table`.
Commit: cebfb75c9f02e2ef0d4deadf606299f87ec252cc
https://github.com/llvm/llvm-project/commit/cebfb75c9f02e2ef0d4deadf606299f87ec252cc
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M libcxx/test/std/utilities/meta/meta.unary/meta.unary.prop/has_unique_object_representations.compile.pass.cpp
Log Message:
-----------
[libc++] Temporarily disable failing test for Android CI runners
This test is currently failing in the Android CI, since the compiler
used there is too old. Once the Clang version is updated this XFAIL
should be removed again.
Commit: ed87f0afba24d56b509dfc21298b2700d886912b
https://github.com/llvm/llvm-project/commit/ed87f0afba24d56b509dfc21298b2700d886912b
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
A llvm/test/CodeGen/AMDGPU/amdgpu-late-codegenprepare-crash-splat.ll
Log Message:
-----------
[AMDGPU] Visit all PHIs in each call to optimizeLiveType (#147522)
Make the Visited set a local variable, otherwise we can reject a PHI
(those that do not have a zeroinitializer constant) but mark it as
visited,
and the rest of the function thinks the PHI is ok when it isn't.
This is a bit crude but it's the only fix that consistently worked in my
testing.
Fixes SWDEV-541767
Commit: fcd4a2fe7adfd0a58029583350692f3627d396e4
https://github.com/llvm/llvm-project/commit/fcd4a2fe7adfd0a58029583350692f3627d396e4
Author: Vikram Hegde <115221833+vikramRH at users.noreply.github.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
A llvm/include/llvm/CodeGen/PostRAMachineSink.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/test/CodeGen/AArch64/bisect-post-ra-machine-sink.mir
M llvm/test/CodeGen/AArch64/post-ra-machine-sink.mir
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/postra-machine-sink.mir
M llvm/test/CodeGen/AMDGPU/postra-sink-update-dependency.mir
M llvm/test/CodeGen/AMDGPU/sink-after-control-flow-postra.mir
M llvm/test/CodeGen/SystemZ/no-postra-sink.mir
M llvm/test/CodeGen/X86/postra-ignore-dbg-instrs.mir
M llvm/test/CodeGen/X86/pr38952.mir
M llvm/test/DebugInfo/MIR/X86/postra-subreg-sink.mir
Log Message:
-----------
[CodeGen][NewPM] Port "PostRAMachineSink" pass to NPM (#129690)
Commit: 60c14ac582bc0843df1790e0410ba41ac66393f5
https://github.com/llvm/llvm-project/commit/60c14ac582bc0843df1790e0410ba41ac66393f5
Author: Jim Lin <jim at andestech.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c
Log Message:
-----------
[RISCV] +zve64x is sufficient for the zvfbfmin and zvfbfwma intrinsic tests. NFC.
Commit: da8d7f49fff7dd59ee42682ddf0a386ef5a54d81
https://github.com/llvm/llvm-project/commit/da8d7f49fff7dd59ee42682ddf0a386ef5a54d81
Author: Luke Lau <luke at igalia.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/fround.ll
Log Message:
-----------
[RISCV] Unify non-vp and vp rounding intrinsic costing (#147872)
Currently we have slightly different costing for the vp and non-vp
version of the rounding intrinsics.
We can delete this code and use the generic BasicTTIImpl code for the vp
intrinsics which falls back to the non-vp versions.
I'm not sure if the zvfh costing is correct, this should probably be
fixed in a follow up patch. At the moment the non-vp cost is more
important since it is what the loop vectorizer will use.
Commit: f573f6b886a013c25509d86d8dfd18d378ecc309
https://github.com/llvm/llvm-project/commit/f573f6b886a013c25509d86d8dfd18d378ecc309
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/test/CodeGen/Inputs/stack-guard-reassign.ll
Log Message:
-----------
CodeGen: Convert test to opaque pointers (#147886)
Apparently we have this weird CodeGen/Inputs directory which
got missed
Commit: 1ccd7793247139e55aec986e6d86c50d97f9a755
https://github.com/llvm/llvm-project/commit/1ccd7793247139e55aec986e6d86c50d97f9a755
Author: Vikram Hegde <115221833+vikramRH at users.noreply.github.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/include/llvm/Passes/TargetPassRegistry.inc
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
M llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp
M llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
Log Message:
-----------
[AMDGPU][NewPM] Port "AMDGPUResourceUsageAnalysis" to NPM (#130959)
Commit: adcd1bb32a050ced58584882b405f04f42c6009b
https://github.com/llvm/llvm-project/commit/adcd1bb32a050ced58584882b405f04f42c6009b
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/test/SemaTemplate/concepts-lambda.cpp
Log Message:
-----------
[Clang] Fix the template argument collection after CWG2369 (#147894)
Since the function template isn't instantiated before constraint
checking, we'll not be able to find the outer template arguments through
function specialization when evaluating the inner constraint that is
nested within a larger constraint expression.
The only practical solution is to get them back through the code
synthesis context, which also allows us to eliminate an overload of
getTemplateInstantiationArgs.
No release note because it's a regression on trunk.
Fixes https://github.com/llvm/llvm-project/issues/147772
Commit: 8055c0f380323fe9e1398dcb88276fd6c92ffa5d
https://github.com/llvm/llvm-project/commit/8055c0f380323fe9e1398dcb88276fd6c92ffa5d
Author: Urvi Rav <94829943+ravurvi20 at users.noreply.github.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/lib/Parse/ParseOpenMP.cpp
M clang/test/OpenMP/Inputs/declare_target_include.h
M clang/test/OpenMP/declare_target_ast_print.cpp
M clang/test/OpenMP/declare_target_messages.cpp
M clang/test/OpenMP/target_ast_print.cpp
Log Message:
-----------
[OpenMP-5.2] deprecate delimited form of 'declare target' (#145854)
According to OpenMP 5.2 (Section 7.8.2), the directive name `declare
target` may be used as a synonym for `begin declare target` only when no
clauses are specified. This clause-less delimited form is now deprecated
and should emit a deprecation warning.
```
// Deprecated usage (should trigger warning):
#pragma omp declare target // deprecated in OpenMP 5.2
void foo1() {
}
#pragma omp end declare target
// Valid usage with clause (should not trigger warning):
#pragma omp declare target enter(foo2)
void foo2() {
}
```
```
// Recommended replacement for deprecated delimited form:
#pragma omp begin declare target
void foo() {
}
#pragma omp end declare target
```
---------
Co-authored-by: urvi-rav <urvi.rav at hpe.com>
Commit: 75656d8c1118ee96f09b88b1c635a5a2d4ca27e6
https://github.com/llvm/llvm-project/commit/75656d8c1118ee96f09b88b1c635a5a2d4ca27e6
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
A llvm/test/CodeGen/X86/pr147781.ll
Log Message:
-----------
[X86] combineStore - remove rangedata when converting 64-bit copies to f64 load/store (#147904)
We're changing from i64 to f64 - we can't retain any range metadata
Fixes #147781
Commit: 63f19f1c5c5fbf539d993adeb70a531af3a1241d
https://github.com/llvm/llvm-project/commit/63f19f1c5c5fbf539d993adeb70a531af3a1241d
Author: Wendi <uwendi at gmail.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/docs/GettingInvolved.rst
M llvm/docs/QualGroup.rst
M llvm/docs/index.rst
A llvm/docs/qual-wg/slides/202507_llvm_qual_wg.pdf
Log Message:
-----------
[QualGroup] Add slides and documentation updates after July 2025 sync-up (#147196)
This patch updates the Qualification Working Group documentation with
improvements based on our first sync-up meeting in July 2025:
- Added July 2025 meeting slides to `qual-wg/slides/`
- Updated Participation section to include clickable links to Discourse
and Discord
- Clarified contributor recognition to include async contributors
- Added new sections for Meeting Minutes and Presentation Slides
- Linked to the initial RFC and Discord channel in the Contact section
- Added Code of Conduct section
- Minor formatting consistency fixes across the document
This change also updates `GettingInvolved.rst` to add the Qualification
WG with calendar links and Discourse minutes.
These updates aim to improve clarity, traceability, and contributor
onboarding.
---------
Co-authored-by: Wendi Urribarri (Woven by Toyota <wendi.urribarri at woven-planet.global>
Commit: 2e38beebcf3766200e4b0c435a5729eea347b9bf
https://github.com/llvm/llvm-project/commit/2e38beebcf3766200e4b0c435a5729eea347b9bf
Author: Christian Sigg <csigg at google.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/__support/FPUtil/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/utils/MPFRWrapper/BUILD.bazel
Log Message:
-----------
[libc][bazel] Port bb7cea0
Commit: cff4a00d3f7d91c0dd3a93eb81db66be178273d3
https://github.com/llvm/llvm-project/commit/cff4a00d3f7d91c0dd3a93eb81db66be178273d3
Author: macurtis-amd <macurtis at amd.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
A llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-runtime.ll
Log Message:
-----------
AMDGPU: Fix runtime unrolling when cascaded GEPs present (#147700)
Cascaded GEP (i.e. GEP of GEP) are not handled when determining if it is
ok to runtime unroll loops.
This change simply uses `getUnderlyingObjects` to look through cascaded
GEPs.
Commit: a709621cd545b061782b03136286227867b452a6
https://github.com/llvm/llvm-project/commit/a709621cd545b061782b03136286227867b452a6
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M clang/include/clang/Lex/TokenLexer.h
Log Message:
-----------
[Lex] Use SourceLocation::UIntTy for the MacroDefStart, NFC
Avoid using the underlying type, and be more consistent -- MacroDefStart stores
the result of SourceManager::getNextLocalOffset() which returns the
SourceLocation::UIntTy.
Commit: 96e4b50ffea9dc23d43d9ddb679acb3afae3ad14
https://github.com/llvm/llvm-project/commit/96e4b50ffea9dc23d43d9ddb679acb3afae3ad14
Author: Christian Sigg <csigg at google.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
A utils/bazel/llvm-project-overlay/third-party/siphash/BUILD.bazel
Log Message:
-----------
[llvm][bazel] Port 7f3afab
Commit: f7cdff7bddcb168094b569b15d2bfaef0526c244
https://github.com/llvm/llvm-project/commit/f7cdff7bddcb168094b569b15d2bfaef0526c244
Author: Takuto Ikuta <tikuta at google.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M compiler-rt/lib/fuzzer/FuzzerDriver.cpp
M compiler-rt/lib/fuzzer/FuzzerIOPosix.cpp
M compiler-rt/lib/fuzzer/FuzzerRandom.h
Log Message:
-----------
[compiler-rt] Include missing headers for libFuzzer (#146828)
This is to fix modules build errors in chromium like
*
https://ci.chromium.org/ui/p/chromium/builders/try/linux-libfuzzer-asan-rel/2292144/overview
*
https://ci.chromium.org/ui/p/chromium/builders/try/linux-libfuzzer-asan-rel/2292444/overview
---------
Co-authored-by: Petr Hosek <phosek at google.com>
Commit: 8fb1699972629e899504e4d62ab79992817eadda
https://github.com/llvm/llvm-project/commit/8fb1699972629e899504e4d62ab79992817eadda
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/include/llvm/Transforms/Utils/LowerMemIntrinsics.h
Log Message:
-----------
[NFC] Fix typo in comment in LowerMemIntrinsics.h (#147903)
Commit: 0f29e7dadc26a2cd41e0bc55a379049b5efd039c
https://github.com/llvm/llvm-project/commit/0f29e7dadc26a2cd41e0bc55a379049b5efd039c
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
Log Message:
-----------
Fix MSVC warning - "'llvm::AMDGPUResourceUsageAnalysis': type name first seen using 'class' now seen using 'struct'". NFC.
Commit: d844384ad90aac733d0429dd25b6640570599caa
https://github.com/llvm/llvm-project/commit/d844384ad90aac733d0429dd25b6640570599caa
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/fneg-combines.ll
Log Message:
-----------
[AMDGPU] fneg-combines.ll - regenerate test checks
Commit: d7859ed047c99561424dfe235733bb36e2b3c738
https://github.com/llvm/llvm-project/commit/d7859ed047c99561424dfe235733bb36e2b3c738
Author: Mariusz Sikora <mariusz.sikora at amd.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
Log Message:
-----------
[AMDGPU][NFC] Remove unused return (#147912)
Commit: 19c2fb2325b034c743004315167e2fa202d8a5e9
https://github.com/llvm/llvm-project/commit/19c2fb2325b034c743004315167e2fa202d8a5e9
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lround.ll
A llvm/test/CodeGen/RISCV/rvv/llround-sdnode.ll
A llvm/test/CodeGen/RISCV/rvv/lround-sdnode.ll
Log Message:
-----------
[ISel/RISCV] Custom-lower vector [l]lround (#147713)
Lower it just like the vector [l]lrint, using vfcvt, with the right
rounding mode. Updating costs to account for this custom-lowering is
left to a companion patch.
Commit: 361a659796b2baa4f1479980a46c56777fad7619
https://github.com/llvm/llvm-project/commit/361a659796b2baa4f1479980a46c56777fad7619
Author: Christian Sigg <csigg at google.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] Port ddf9b91
Commit: a446300d1bd0b97b400b2f246f1aa861d62115e6
https://github.com/llvm/llvm-project/commit/a446300d1bd0b97b400b2f246f1aa861d62115e6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/lib/CodeGen/TargetLoweringBase.cpp
Log Message:
-----------
TargetLowering: Avoid a use of PointerType::getUnqual (#147884)
Use the default globals address space
Commit: 71150f23103a7ac5b9c2ca6d1a3ac082dcd1506a
https://github.com/llvm/llvm-project/commit/71150f23103a7ac5b9c2ca6d1a3ac082dcd1506a
Author: Ricardo Jesus <rjj at nvidia.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/test/CodeGen/AArch64/bsl.ll
M llvm/test/CodeGen/AArch64/eor3.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop.ll
M llvm/test/CodeGen/AArch64/sve2-bsl.ll
Log Message:
-----------
[AArch64] Use SVE2 bit-sel instructions for some binary patterns. (#147544)
We can use NBSL/BSL2N to implement the following operations via the
corresponding identities:
* EON(a, b) = BSL2N(a, a, b) = BSL2N(b, b, a)
* NAND(a, b) = NBSL(a, b, b) = NBSL(b, a, a)
* NOR(a, b) = NBSL(a, b, a) = NBSL(b, a, b)
* ORN(a, b) = BSL2N(a, b, a)
Most of these operations are currently lowered into at least two
instructions because we don't have dedicated Neon/SVE instructions
for them. With the appropriate pattern of NBSL/BSL2N we can lower
them in a single instruction.
We could also use NBSL to implement an unpredicated NOT(a) =
NBSL(a, a, a), but because of the tied register constraint, this
may not always be profitable.
Commit: 953416ae40b4d81896f5f353dc96725f8b64eb10
https://github.com/llvm/llvm-project/commit/953416ae40b4d81896f5f353dc96725f8b64eb10
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.h
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/test/TableGen/RuntimeLibcallEmitter-calling-conv.td
M llvm/test/TableGen/RuntimeLibcallEmitter.td
M llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp
Log Message:
-----------
ARM: Start moving runtime libcalls into tablegen (#146084)
We still need to manually set the calling conventions of
some libcalls until the lowering is separated out.
Commit: 56a8655f4a9c3992fd401dcf12b956f24f0e2606
https://github.com/llvm/llvm-project/commit/56a8655f4a9c3992fd401dcf12b956f24f0e2606
Author: Tcc100 <Tcc100 at users.noreply.github.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/docs/WritingAnLLVMPass.rst
A llvm/include/llvm/Target/RegisterTargetPassConfigCallback.h
M llvm/lib/CodeGen/CodeGenTargetMachineImpl.cpp
M llvm/lib/Target/CMakeLists.txt
A llvm/lib/Target/RegisterTargetPassConfigCallback.cpp
A llvm/test/Other/codegen-plugin-loading.ll
A llvm/unittests/CodeGen/CGPluginTest/CMakeLists.txt
A llvm/unittests/CodeGen/CGPluginTest/Plugin/CMakeLists.txt
A llvm/unittests/CodeGen/CGPluginTest/Plugin/CodeGenTestPass.cpp
A llvm/unittests/CodeGen/CGPluginTest/Plugin/CodeGenTestPass.h
A llvm/unittests/CodeGen/CGPluginTest/Plugin/Plugin.cpp
A llvm/unittests/CodeGen/CGPluginTest/PluginTest.cpp
M llvm/unittests/CodeGen/CMakeLists.txt
Log Message:
-----------
[CodeGen] Expose the extensibility of PassConfig to plugins (#139059)
This PR exposes the backend pass config to plugins via a callback.
Plugin authors can register a callback that is being triggered before
the target backend adds their passes to the pipeline. In the callback
they then get access to the `TargetMachine`, the `PassManager`, and the
`TargetPassConfig`. This allows plugins to call
`TargetPassConfig::insertPass`, which is honored in the subsequent
`addPass` of the main backend. We implemented this using the legacy pass
manager since backends still use it as the default.
Commit: cea33304c0ea7fdcd40c7ad6cfeef813d3c9f5e5
https://github.com/llvm/llvm-project/commit/cea33304c0ea7fdcd40c7ad6cfeef813d3c9f5e5
Author: Kenneth Benzie (Benie) <k.benzie83 at gmail.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M offload/CMakeLists.txt
A offload/docs/.gitignore
A offload/docs/CMakeLists.txt
A offload/docs/conf.py
A offload/docs/index.rst
M offload/liboffload/API/Common.td
M offload/tools/offload-tblgen/APIGen.cpp
M offload/tools/offload-tblgen/CMakeLists.txt
A offload/tools/offload-tblgen/DocGen.cpp
M offload/tools/offload-tblgen/GenCommon.hpp
M offload/tools/offload-tblgen/Generators.hpp
M offload/tools/offload-tblgen/offload-tblgen.cpp
Log Message:
-----------
[Offload] Add Offload API Sphinx documentation (#147323)
* Add spec generation to offload-tblgen tool
* This patch adds generation of Sphinx compatible reStructuedText
utilizing the C domain to document the Offload API directly from the
spec definition `.td` files.
* Add Sphinx HTML documentation target
* Introduces the `docs-offload-html` target when CMake is configured
with `LLVM_ENABLE_SPHINX=ON` and `SPHINX_OUTPUT_HTML=ON`. Utilized
`offload-tblgen -gen-spen` to generate Offload API specification docs.
Commit: d3ea7f29ec50937242ae12c8cd5ce1c3f0667204
https://github.com/llvm/llvm-project/commit/d3ea7f29ec50937242ae12c8cd5ce1c3f0667204
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/mad-combine.ll
Log Message:
-----------
[AMDGPU] mad-combine.ll - regenerate test checks and remove duplicate safe/unsafe RUN line
Commit: 628c7350108dbf207e22489ab2cd0324277afb2b
https://github.com/llvm/llvm-project/commit/628c7350108dbf207e22489ab2cd0324277afb2b
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M mlir/include/mlir/Dialect/OpenMP/OpenMPDialect.h
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpBase.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
A mlir/test/Dialect/OpenMP/cli-canonical_loop-invalid.mlir
A mlir/test/Dialect/OpenMP/cli-canonical_loop.mlir
A mlir/test/Dialect/OpenMP/cli-unroll-heuristic.mlir
Log Message:
-----------
[MLIR][OpenMP] Add canonical loop operations (#147061)
Add the supporting OpenMP Dialect operations, types, and interfaces for
modelling
MLIR Operations:
* omp.newcli
* omp.canonical_loop
MLIR Types:
* !omp.cli
MLIR Interfaces:
* LoopTransformationInterface
As a first loop transformations to be able to use these new operation in
follow-up PRs (#144785)
* omp.unroll_heuristic
Commit: 343e3c6bb827fb2c969f7399bef448bd58e1e43f
https://github.com/llvm/llvm-project/commit/343e3c6bb827fb2c969f7399bef448bd58e1e43f
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/test/CodeGen/AArch64/sve-bf16-arith.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith.ll
M llvm/test/CodeGen/AArch64/sve-merging-unary.ll
Log Message:
-----------
[LLVM][CodeGen][SVE] Make bf16 fabs/fneg isel consistent with fp16. (#147543)
Whilst at first glance there appears to be no native bfloat instructions
to modify the sign bit, this is only the case when FEAT_AFP is
implemented. Without this feature vector FABS/FNEG does not care about
the floating point format beyond needing to know the position of the
sign bit. From what I can see LLVM has no support for FEAT_AFP in terms
of feature detection or ACLE builtins and so I believe the compiler can
work under the assumption the feature is not enabled. In fact, if
FEAT_AFP is enabled then I believe the current isel is likely broken for
half, float and double anyway.
Commit: abb878438ae853fc068aa16e862b30c8d9ae04e1
https://github.com/llvm/llvm-project/commit/abb878438ae853fc068aa16e862b30c8d9ae04e1
Author: Ross Brunton <ross at codeplay.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
M offload/plugins-nextgen/common/include/GlobalHandler.h
M offload/plugins-nextgen/cuda/src/rtl.cpp
Log Message:
-----------
[Offload] Allow querying the size of globals (#147698)
The `GlobalTy` helper has been extended to make both the Size and Ptr be
optional. Now `getGlobalMetadataFromDevice`/`Image` is able to write the
size of the global to the struct, instead of just verifying it.
Commit: 2052d7bf9ad5f7e9fd4d2dc5bee5e6647bc58f77
https://github.com/llvm/llvm-project/commit/2052d7bf9ad5f7e9fd4d2dc5bee5e6647bc58f77
Author: David Green <david.green at arm.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
A llvm/test/Analysis/CostModel/AArch64/fcmp.ll
A llvm/test/Analysis/CostModel/AArch64/sve-fcmp.ll
Log Message:
-----------
[AArch64] Expand fcmp cost model tests. NFC
Commit: 59a99c6f2c80af9186bedbf9a5ab997453035f6d
https://github.com/llvm/llvm-project/commit/59a99c6f2c80af9186bedbf9a5ab997453035f6d
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/AArch64/gather-cost.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/getelementptr.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/getelementptr2.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vectorizable-selects-min-max.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vectorizable-selects-uniform-cmps.ll
Log Message:
-----------
[SLP] Drop unnecessary '' from around -passes=... arg lists to appease update_test_checks.py when run on DOS. NFC.
Commit: 75f81ded8f9d558c92d92641bce3cf7ef8e13e9c
https://github.com/llvm/llvm-project/commit/75f81ded8f9d558c92d92641bce3cf7ef8e13e9c
Author: agozillon <Andrew.Gozillon at amd.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M flang-rt/include/flang-rt/runtime/format.h
M flang-rt/include/flang-rt/runtime/internal-unit.h
M flang-rt/include/flang-rt/runtime/io-stmt.h
M flang-rt/include/flang-rt/runtime/non-tbp-dio.h
M flang-rt/include/flang-rt/runtime/work-queue.h
M flang-rt/lib/runtime/edit-input.h
M flang-rt/lib/runtime/edit-output.h
M flang-rt/lib/runtime/unit.h
M flang/include/flang/Decimal/decimal.h
Log Message:
-----------
[Flang][FlangRT][Runtime] Add RT_OFFLOAD_API_GROUP_BEGIN to missing symbols on AMDGPU (#147612)
After the recent move to work queues, in certain cases when linking in
the fortran runtime built for offload on AMDGPU as required in certain
cases, we'll get missing symbols when linking. This PR tries to address
this issue by encompassing more of the library in
RT_OFFLOAD_API_GROUP_BEGIN, which has the affect of compiling these
functions for AMDGPU, resolving the missing symbols.
This PR should address the following issue:
https://github.com/llvm/llvm-project/issues/145888
Commit: d0a038296ea7037454a0b1414aa38f56fbcdc759
https://github.com/llvm/llvm-project/commit/d0a038296ea7037454a0b1414aa38f56fbcdc759
Author: Shashi Shankar <shashishankar1687 at gmail.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Parse/ParseDeclCXX.cpp
A clang/test/SemaCXX/invalid-base-inheritance.cpp
Log Message:
-----------
[Clang] Ignore invalid base classes (#147213)
When building a RecordDecl, ignore invalid base classes. This solves crashes later on and leads to better recovery.
Fixes #147186
Commit: 1d8b51667ab3b8be039d616341470613325971f3
https://github.com/llvm/llvm-project/commit/1d8b51667ab3b8be039d616341470613325971f3
Author: Luke Lau <luke at igalia.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
Log Message:
-----------
[TTI] Don't drop VP intrinsic args when delegating to non-vp equivalent (#147677)
Previously we only carried the type arguments which caused value-based
costs to be inadvertantly changed into type-based costs.
I'm just using vp.is.fpclass as an example intrinsic for now since the
type based cost seems to differ from the value based cost, and most
normal intrinsics e.g. min/max have the same value + type based cost.
We still need to handle the cost properly for is.fpclass in a second
patch.
This is needed for an upcoming patch to handle the cost of
llvm.experimental.vp.reverse which suffers from the same problem.
Commit: 0481d2a1614d011db022abb896eace626acd37ab
https://github.com/llvm/llvm-project/commit/0481d2a1614d011db022abb896eace626acd37ab
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/docs/WritingAnLLVMPass.rst
R llvm/include/llvm/Target/RegisterTargetPassConfigCallback.h
M llvm/lib/CodeGen/CodeGenTargetMachineImpl.cpp
M llvm/lib/Target/CMakeLists.txt
R llvm/lib/Target/RegisterTargetPassConfigCallback.cpp
R llvm/test/Other/codegen-plugin-loading.ll
R llvm/unittests/CodeGen/CGPluginTest/CMakeLists.txt
R llvm/unittests/CodeGen/CGPluginTest/Plugin/CMakeLists.txt
R llvm/unittests/CodeGen/CGPluginTest/Plugin/CodeGenTestPass.cpp
R llvm/unittests/CodeGen/CGPluginTest/Plugin/CodeGenTestPass.h
R llvm/unittests/CodeGen/CGPluginTest/Plugin/Plugin.cpp
R llvm/unittests/CodeGen/CGPluginTest/PluginTest.cpp
M llvm/unittests/CodeGen/CMakeLists.txt
Log Message:
-----------
Revert "[CodeGen] Expose the extensibility of PassConfig to plugins" (#147947)
Reverts llvm/llvm-project#139059
This broke
https://lab.llvm.org/buildbot/#/builders/10/builds/9125/steps/8/logs/stdio
The bot does a SHARED_LIBS=ON build. I can reproduce locally with the
CMake cache file in offload/cmake/caches/AMDGPUBot.cmake as the build
config.
Commit: 39ea9b71d90f95a5d91d72004b37779d1ed6d72e
https://github.com/llvm/llvm-project/commit/39ea9b71d90f95a5d91d72004b37779d1ed6d72e
Author: Corentin Jabot <corentinjabot at gmail.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/test/CXX/drs/cwg26xx.cpp
M clang/test/SemaCXX/cxx2b-deducing-this.cpp
Log Message:
-----------
[Clang] Correctly handle taking the address of an explicit object member function template (#147046)
When implementing #93430, I failed to consider some cases involving
function templates.
```
struct A {
template <typename T>
void a(this T self);
};
(&A::a<A>)(A{});
```
This fixes that
Commit: 78e84e5779f4ed1de9bc29b6aae8609de2b9f8c4
https://github.com/llvm/llvm-project/commit/78e84e5779f4ed1de9bc29b6aae8609de2b9f8c4
Author: Corentin Jabot <corentinjabot at gmail.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Parse/ParseTentative.cpp
M clang/test/Parser/cxx0x-lambda-expressions.cpp
Log Message:
-----------
[Clang] A lone `[` does not an attribute make (#147306)
In some tentative parses, we would always consider `[` as the start of
an attribute - only `[[` should be.
Fixes #63880
Commit: 7a089bc4c00fe35c8f07b7c420be6535ad331161
https://github.com/llvm/llvm-project/commit/7a089bc4c00fe35c8f07b7c420be6535ad331161
Author: Mészáros Gergely <gergely.meszaros at intel.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
R libclc/.gitignore
Log Message:
-----------
[libclc] Delete .gitignore (#147939)
The file is listing build artifacts to ignore, but LLVM has long had the
policy that in-tree builds are not supported, so the ignore rules
shouldn't serve their original purpose anymore.
The rules however are annoying because although they probably intended
only to ignore top-level build artifacts, they lack the leading `/` so
they match any file with the ignored name anywhere under `libclc/`.
Commit: 7bbb65c8fee605d7c875e495d7ce14f7700ce554
https://github.com/llvm/llvm-project/commit/7bbb65c8fee605d7c875e495d7ce14f7700ce554
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.h
Log Message:
-----------
RuntimeLibcalls: Make getLibcallImplName static. NFC. (#147919)
Commit: 130e6121f5bb1a54c591133d050aa1311ce16d7f
https://github.com/llvm/llvm-project/commit/130e6121f5bb1a54c591133d050aa1311ce16d7f
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
Log Message:
-----------
[clang][bytecode][NFC] Move Pointer::StorageKind above the union (#147942)
This is easier to read in debuggers and more common.
Commit: 1585cde21adc8b154255ed5218c8966f543fe493
https://github.com/llvm/llvm-project/commit/1585cde21adc8b154255ed5218c8966f543fe493
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-07-10 (Thu, 10 Jul 2025)
Changed paths:
M .ci/monolithic-windows.sh
M .github/workflows/premerge.yaml
M clang-tools-extra/clang-tidy/modernize/PassByValueCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/modernize/pass-by-value.cpp
M clang/Maintainers.rst
M clang/cmake/caches/Fuchsia-stage2.cmake
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/ExprConcepts.h
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/BuiltinsPPC.def
M clang/include/clang/Basic/BuiltinsSPIRVCL.td
M clang/include/clang/Basic/BuiltinsSPIRVCommon.td
M clang/include/clang/Basic/DiagnosticCommentKinds.td
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/TargetInfo.h
M clang/include/clang/Basic/riscv_andes_vector.td
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/Lex/TokenLexer.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ASTConcept.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ASTStructuralEquivalence.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/CommentSema.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/RecordLayoutBuilder.cpp
M clang/lib/AST/TypePrinter.cpp
M clang/lib/ASTMatchers/ASTMatchersInternal.cpp
M clang/lib/Basic/TargetInfo.cpp
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/Basic/Targets/DirectX.h
M clang/lib/Basic/Targets/PPC.cpp
M clang/lib/Basic/Targets/PPC.h
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/Basic/Targets/WebAssembly.cpp
M clang/lib/Basic/Targets/WebAssembly.h
M clang/lib/Basic/Targets/X86.h
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/TargetBuiltins/SPIR.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Format/Format.cpp
M clang/lib/Frontend/ASTUnit.cpp
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Headers/__clang_spirv_builtins.h
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/Lex/Lexer.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Parse/ParseOpenMP.cpp
M clang/lib/Parse/ParseTentative.cpp
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaLambda.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaStmt.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp
M clang/test/AST/ByteCode/new-delete.cpp
A clang/test/AST/ast-print-cconv-preserve.cpp
M clang/test/Analysis/NewDelete-checker-test.cpp
M clang/test/CIR/CodeGen/bitfields.c
M clang/test/CIR/CodeGen/bitfields.cpp
M clang/test/CIR/CodeGen/complex-builtins.cpp
A clang/test/CIR/IR/bitfield_info.cir
M clang/test/CIR/Lowering/select.cir
M clang/test/CXX/drs/cwg26xx.cpp
A clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c
A clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c
A clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c
A clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c
A clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c
A clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c
A clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c
A clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c
R clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvtbf16.c
R clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvtbf16.c
R clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmaccbf16.c
R clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvtbf16.c
R clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvtbf16.c
R clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmaccbf16.c
R clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvtbf16.c
R clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvtbf16.c
R clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmaccbf16.c
R clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvtbf16.c
R clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvtbf16.c
R clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmaccbf16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c
M clang/test/CodeGenCXX/mangle-requires.cpp
M clang/test/CodeGenCXX/ms-mangle-requires.cpp
M clang/test/CodeGenHLSL/semantics/DispatchThreadID.hlsl
M clang/test/CodeGenHLSL/semantics/SV_GroupID.hlsl
M clang/test/CodeGenHLSL/semantics/SV_GroupThreadID.hlsl
A clang/test/CodeGenSPIRV/Builtins/ids_and_ranges.c
M clang/test/Driver/pgo-sample-use-profi.c
A clang/test/Headers/spirv_ids.cpp
M clang/test/Layout/ms-x86-declspec-empty_bases.cpp
M clang/test/OpenMP/Inputs/declare_target_include.h
M clang/test/OpenMP/declare_target_ast_print.cpp
M clang/test/OpenMP/declare_target_messages.cpp
M clang/test/OpenMP/target_ast_print.cpp
M clang/test/Parser/cxx0x-lambda-expressions.cpp
M clang/test/Sema/constant_builtins_vector.cpp
M clang/test/Sema/preserve-call-conv.c
M clang/test/Sema/preserve-none-call-conv.c
M clang/test/Sema/uninit-variables.c
M clang/test/SemaCXX/attr-lifetimebound.cpp
M clang/test/SemaCXX/cxx1z-constexpr-lambdas.cpp
M clang/test/SemaCXX/cxx2b-deducing-this.cpp
A clang/test/SemaCXX/invalid-base-inheritance.cpp
M clang/test/SemaCXX/lambda-attributes.cpp
M clang/test/SemaCXX/ms-layout_version.cpp
A clang/test/SemaCXX/range-for-lifetime-cxx23.cpp
M clang/test/SemaCXX/uninitialized.cpp
A clang/test/SemaSPIRV/BuiltIns/ids_and_ranges.c
M clang/test/SemaTemplate/concepts-lambda.cpp
M clang/tools/cir-translate/cir-translate.cpp
M clang/tools/clang-import-test/clang-import-test.cpp
M clang/tools/libclang/CMakeLists.txt
M clang/unittests/AST/ASTImporterTest.cpp
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
M compiler-rt/cmake/builtin-config-ix.cmake
M compiler-rt/lib/asan/asan_allocator.h
M compiler-rt/lib/builtins/CMakeLists.txt
A compiler-rt/lib/builtins/aarch64/emupac.cpp
M compiler-rt/lib/builtins/int_types.h
M compiler-rt/lib/fuzzer/FuzzerDriver.cpp
M compiler-rt/lib/fuzzer/FuzzerIOPosix.cpp
M compiler-rt/lib/fuzzer/FuzzerRandom.h
M compiler-rt/lib/lsan/lsan_allocator.h
M compiler-rt/lib/msan/msan_allocator.cpp
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_allocator_internal.h
M compiler-rt/lib/sanitizer_common/sanitizer_platform.h
M compiler-rt/lib/scudo/standalone/primary32.h
M compiler-rt/lib/scudo/standalone/primary64.h
M compiler-rt/lib/tsan/rtl/tsan_rtl.h
A compiler-rt/test/builtins/Unit/aarch64/emupac.c
M compiler-rt/test/sanitizer_common/TestCases/Linux/free_aligned_sized.c
M compiler-rt/test/sanitizer_common/TestCases/Linux/free_sized.c
M flang-rt/include/flang-rt/runtime/format.h
M flang-rt/include/flang-rt/runtime/internal-unit.h
M flang-rt/include/flang-rt/runtime/io-stmt.h
M flang-rt/include/flang-rt/runtime/non-tbp-dio.h
M flang-rt/include/flang-rt/runtime/work-queue.h
M flang-rt/lib/runtime/edit-input.h
M flang-rt/lib/runtime/edit-output.h
M flang-rt/lib/runtime/unit.h
M flang/include/flang/Decimal/decimal.h
M flang/include/flang/Frontend/CompilerInvocation.h
M flang/include/flang/Lower/OpenACC.h
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/include/flang/Parser/message.h
M flang/include/flang/Semantics/semantics.h
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Frontend/FrontendAction.cpp
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
M flang/lib/Parser/message.cpp
M flang/lib/Semantics/semantics.cpp
A flang/test/Driver/fatal-errors-parsing.f90
A flang/test/Driver/fatal-errors-semantics.f90
M flang/test/HLFIR/opt-scalar-assign.fir
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-loop.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/wchar.yaml
M libc/src/__support/CPP/atomic.h
M libc/src/__support/CPP/type_traits/is_floating_point.h
M libc/src/__support/FPUtil/CMakeLists.txt
M libc/src/__support/FPUtil/FPBits.h
A libc/src/__support/FPUtil/bfloat16.h
M libc/src/__support/FPUtil/cast.h
M libc/src/__support/FPUtil/dyadic_float.h
M libc/src/__support/macros/properties/types.h
M libc/src/__support/wctype_utils.h
M libc/src/wchar/CMakeLists.txt
M libc/src/wchar/wcpncpy.cpp
A libc/src/wchar/wcslcat.cpp
A libc/src/wchar/wcslcat.h
A libc/src/wchar/wcslcpy.cpp
A libc/src/wchar/wcslcpy.h
M libc/test/src/__support/FPUtil/CMakeLists.txt
A libc/test/src/__support/FPUtil/bfloat16_test.cpp
M libc/test/src/math/exhaustive/CMakeLists.txt
A libc/test/src/math/exhaustive/bfloat16_test.cpp
M libc/test/src/wchar/CMakeLists.txt
M libc/test/src/wchar/wcpncpy_test.cpp
A libc/test/src/wchar/wcslcat_test.cpp
A libc/test/src/wchar/wcslcpy_test.cpp
M libc/utils/MPFRWrapper/CMakeLists.txt
M libc/utils/MPFRWrapper/MPCommon.cpp
M libc/utils/MPFRWrapper/MPCommon.h
R libclc/.gitignore
A libclc/clc/include/clc/workitem/clc_get_global_id.h
A libclc/clc/include/clc/workitem/clc_get_global_offset.h
A libclc/clc/include/clc/workitem/clc_get_global_size.h
A libclc/clc/include/clc/workitem/clc_get_group_id.h
A libclc/clc/include/clc/workitem/clc_get_local_id.h
A libclc/clc/include/clc/workitem/clc_get_local_linear_id.h
A libclc/clc/include/clc/workitem/clc_get_local_size.h
A libclc/clc/include/clc/workitem/clc_get_max_sub_group_size.h
A libclc/clc/include/clc/workitem/clc_get_num_groups.h
A libclc/clc/include/clc/workitem/clc_get_num_sub_groups.h
A libclc/clc/include/clc/workitem/clc_get_sub_group_id.h
A libclc/clc/include/clc/workitem/clc_get_sub_group_local_id.h
A libclc/clc/include/clc/workitem/clc_get_sub_group_size.h
A libclc/clc/include/clc/workitem/clc_get_work_dim.h
M libclc/clc/lib/amdgcn/SOURCES
A libclc/clc/lib/amdgcn/workitem/clc_get_global_offset.cl
A libclc/clc/lib/amdgcn/workitem/clc_get_global_size.cl
A libclc/clc/lib/amdgcn/workitem/clc_get_group_id.cl
A libclc/clc/lib/amdgcn/workitem/clc_get_local_id.cl
A libclc/clc/lib/amdgcn/workitem/clc_get_work_dim.cl
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/workitem/clc_get_local_linear_id.cl
A libclc/clc/lib/generic/workitem/clc_get_num_sub_groups.cl
A libclc/clc/lib/generic/workitem/clc_get_sub_group_id.cl
A libclc/clc/lib/generic/workitem/clc_get_sub_group_size.cl
A libclc/clc/lib/ptx-nvidiacl/SOURCES
A libclc/clc/lib/ptx-nvidiacl/workitem/clc_get_global_id.cl
A libclc/clc/lib/ptx-nvidiacl/workitem/clc_get_group_id.cl
A libclc/clc/lib/ptx-nvidiacl/workitem/clc_get_local_id.cl
A libclc/clc/lib/ptx-nvidiacl/workitem/clc_get_local_size.cl
A libclc/clc/lib/ptx-nvidiacl/workitem/clc_get_max_sub_group_size.cl
A libclc/clc/lib/ptx-nvidiacl/workitem/clc_get_num_groups.cl
A libclc/clc/lib/ptx-nvidiacl/workitem/clc_get_sub_group_local_id.cl
M libclc/cmake/modules/AddLibclc.cmake
A libclc/opencl/include/clc/opencl/workitem/get_local_linear_id.h
A libclc/opencl/include/clc/opencl/workitem/get_max_sub_group_size.h
A libclc/opencl/include/clc/opencl/workitem/get_num_sub_groups.h
A libclc/opencl/include/clc/opencl/workitem/get_sub_group_id.h
A libclc/opencl/include/clc/opencl/workitem/get_sub_group_local_id.h
A libclc/opencl/include/clc/opencl/workitem/get_sub_group_size.h
M libclc/opencl/lib/amdgcn/workitem/get_global_offset.cl
M libclc/opencl/lib/amdgcn/workitem/get_global_size.cl
M libclc/opencl/lib/amdgcn/workitem/get_group_id.cl
M libclc/opencl/lib/amdgcn/workitem/get_local_id.cl
M libclc/opencl/lib/amdgcn/workitem/get_work_dim.cl
M libclc/opencl/lib/ptx-nvidiacl/SOURCES
M libclc/opencl/lib/ptx-nvidiacl/workitem/get_global_id.cl
M libclc/opencl/lib/ptx-nvidiacl/workitem/get_group_id.cl
M libclc/opencl/lib/ptx-nvidiacl/workitem/get_local_id.cl
A libclc/opencl/lib/ptx-nvidiacl/workitem/get_local_linear_id.cl
M libclc/opencl/lib/ptx-nvidiacl/workitem/get_local_size.cl
A libclc/opencl/lib/ptx-nvidiacl/workitem/get_max_sub_group_size.cl
M libclc/opencl/lib/ptx-nvidiacl/workitem/get_num_groups.cl
A libclc/opencl/lib/ptx-nvidiacl/workitem/get_num_sub_groups.cl
A libclc/opencl/lib/ptx-nvidiacl/workitem/get_sub_group_id.cl
A libclc/opencl/lib/ptx-nvidiacl/workitem/get_sub_group_local_id.cl
A libclc/opencl/lib/ptx-nvidiacl/workitem/get_sub_group_size.cl
M libcxx/docs/ReleaseNotes/21.rst
M libcxx/docs/Status/Cxx23Issues.csv
M libcxx/docs/Status/Cxx2cIssues.csv
M libcxx/docs/Status/Cxx2cPapers.csv
M libcxx/include/__config
M libcxx/include/__cxx03/__thread/support/windows.h
M libcxx/include/__hash_table
M libcxx/include/__locale
M libcxx/include/__locale_dir/locale_base_api.h
M libcxx/include/__locale_dir/support/bsd_like.h
M libcxx/include/__locale_dir/support/linux.h
M libcxx/include/__locale_dir/support/no_locale/characters.h
M libcxx/include/__locale_dir/support/windows.h
M libcxx/include/__memory/construct_at.h
M libcxx/include/__node_handle
M libcxx/include/__thread/support/windows.h
M libcxx/include/__tree
M libcxx/include/__type_traits/invoke.h
M libcxx/include/ext/hash_map
M libcxx/include/ext/hash_set
M libcxx/include/future
M libcxx/include/map
M libcxx/include/set
M libcxx/include/unordered_map
M libcxx/include/unordered_set
M libcxx/lib/abi/CHANGELOG.TXT
M libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.noexceptions.nonew.abilist
M libcxx/src/locale.cpp
A libcxx/test/benchmarks/locale/ctype.bench.cpp
R libcxx/test/libcxx/thread/futures/futures.task/type.depr.verify.cpp
R libcxx/test/libcxx/thread/futures/futures.task/types.pass.cpp
M libcxx/test/std/containers/map_allocator_requirement_test_templates.h
M libcxx/test/std/containers/set_allocator_requirement_test_templates.h
A libcxx/test/std/thread/futures/futures.task/futures.task.members/type.verify.cpp
M libcxx/test/std/utilities/meta/meta.unary/meta.unary.prop/has_unique_object_representations.compile.pass.cpp
M libcxx/utils/ci/docker-compose.yml
M lldb/bindings/python/CMakeLists.txt
M lldb/include/lldb/Breakpoint/BreakpointLocation.h
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/lldbdap_testcase.py
M lldb/source/API/SBBreakpointLocation.cpp
M lldb/source/Breakpoint/Breakpoint.cpp
M lldb/source/Breakpoint/BreakpointLocation.cpp
M lldb/source/Breakpoint/BreakpointLocationList.cpp
M lldb/source/Breakpoint/BreakpointResolverAddress.cpp
M lldb/source/Breakpoint/BreakpointSite.cpp
M lldb/source/Commands/CommandObjectBreakpoint.cpp
M lldb/source/Commands/CommandObjectProcess.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/function/Makefile
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/function/TestDataFormatterStdFunction.py
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/function/main.cpp
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/initializer_list/Makefile
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/initializer_list/TestDataFormatterStdInitializerList.py
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/initializer_list/main.cpp
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/ranges/ref_view/Makefile
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/ranges/ref_view/TestDataFormatterStdRangesRefView.py
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/ranges/ref_view/main.cpp
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/string/TestDataFormatterStdString.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/string/main.cpp
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/u8string/Makefile
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/u8string/TestDataFormatterStdU8String.py
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/u8string/main.cpp
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/valarray/Makefile
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/valarray/TestDataFormatterStdValarray.py
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/valarray/main.cpp
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/function/Makefile
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/function/TestLibCxxFunction.py
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/function/main.cpp
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/initializerlist/Makefile
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/initializerlist/TestInitializerList.py
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/initializerlist/main.cpp
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/ranges/ref_view/Makefile
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/ranges/ref_view/TestDataFormatterLibcxxRangesRefView.py
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/ranges/ref_view/main.cpp
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/valarray/Makefile
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/valarray/TestDataFormatterLibcxxValarray.py
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/valarray/main.cpp
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/msvcstl/string/Makefile
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/msvcstl/string/TestDataFormatterMsvcStlString.py
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/msvcstl/string/main.cpp
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/msvcstl/u8string/Makefile
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/msvcstl/u8string/TestDataFormatterMsvcStlU8String.py
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/msvcstl/u8string/main.cpp
M lldb/test/API/tools/lldb-dap/memory/TestDAP_memory.py
M lldb/test/API/tools/lldb-dap/memory/main.cpp
M lldb/tools/lldb-dap/CMakeLists.txt
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
A lldb/tools/lldb-dap/Handler/WriteMemoryRequestHandler.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
M llvm/docs/Extensions.rst
M llvm/docs/GettingInvolved.rst
M llvm/docs/GlobalISel/GenericOpcode.rst
M llvm/docs/QualGroup.rst
M llvm/docs/RISCV/RISCVVectorExtension.rst
M llvm/docs/index.rst
A llvm/docs/qual-wg/slides/202507_llvm_qual_wg.pdf
M llvm/include/llvm/ADT/StringMapEntry.h
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/include/llvm/CodeGen/AsmPrinter.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
A llvm/include/llvm/CodeGen/PostRAMachineSink.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/Frontend/HLSL/RootSignatureValidations.h
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/IR/RuntimeLibcalls.h
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/MC/MCContext.h
M llvm/include/llvm/Object/ELFTypes.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/Passes/TargetPassRegistry.inc
M llvm/include/llvm/ProfileData/SampleProf.h
M llvm/include/llvm/Support/TargetOpcodes.def
M llvm/include/llvm/TableGen/StringToOffsetTable.h
M llvm/include/llvm/Target/GenericOpcodes.td
M llvm/include/llvm/Transforms/Utils/LowerMemIntrinsics.h
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/Analysis/InlineCost.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/CodeGen.cpp
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Frontend/HLSL/RootSignatureValidations.cpp
M llvm/lib/IR/Intrinsics.cpp
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/ProfileData/SampleProf.cpp
M llvm/lib/ProfileData/SampleProfReader.cpp
M llvm/lib/ProfileData/SampleProfWriter.cpp
M llvm/lib/Support/CMakeLists.txt
M llvm/lib/Support/ErrorHandling.cpp
M llvm/lib/Support/SipHash.cpp
M llvm/lib/Support/Unix/Signals.inc
M llvm/lib/TableGen/StringToOffsetTable.cpp
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.h
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp
M llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/BPF/BPFISelLowering.h
M llvm/lib/Target/DirectX/DXILRootSignature.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.h
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsISelLowering.h
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
M llvm/lib/Target/NVPTX/NVPTX.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
M llvm/lib/Target/RISCV/RISCVSchedAndes45.td
M llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td
M llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
M llvm/lib/Target/RISCV/RISCVSchedRocket.td
M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
M llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
M llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td
M llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td
M llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
M llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
M llvm/lib/Target/RISCV/RISCVSchedule.td
M llvm/lib/Target/RISCV/RISCVScheduleXSf.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.h
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Analysis/CostModel/AArch64/cmp.ll
A llvm/test/Analysis/CostModel/AArch64/fcmp.ll
M llvm/test/Analysis/CostModel/AArch64/select.ll
A llvm/test/Analysis/CostModel/AArch64/sve-fcmp.ll
M llvm/test/Analysis/CostModel/AArch64/vector-select.ll
A llvm/test/Analysis/CostModel/RISCV/cast-sat.ll
M llvm/test/Analysis/CostModel/RISCV/fround.ll
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/AArch64/bisect-post-ra-machine-sink.mir
M llvm/test/CodeGen/AArch64/bsl.ll
M llvm/test/CodeGen/AArch64/eor3.ll
A llvm/test/CodeGen/AArch64/exception-handling-windows-elf.ll
A llvm/test/CodeGen/AArch64/mlicm-implicit-defs.mir
M llvm/test/CodeGen/AArch64/post-ra-machine-sink.mir
M llvm/test/CodeGen/AArch64/ptrauth-call.ll
M llvm/test/CodeGen/AArch64/ptrauth-fpac.ll
M llvm/test/CodeGen/AArch64/ptrauth-intrinsic-auth-resign-with-blend.ll
M llvm/test/CodeGen/AArch64/ptrauth-intrinsic-auth-resign.ll
M llvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll
M llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll
M llvm/test/CodeGen/AArch64/sign-return-address-tailcall.ll
M llvm/test/CodeGen/AArch64/sign-return-address.ll
M llvm/test/CodeGen/AArch64/sve-bf16-arith.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith.ll
M llvm/test/CodeGen/AArch64/sve-merging-unary.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop.ll
M llvm/test/CodeGen/AArch64/sve2-bsl.ll
M llvm/test/CodeGen/AArch64/vecreduce-fadd-strict.ll
M llvm/test/CodeGen/AArch64/vecreduce-fadd.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-late-codegenprepare-crash-splat.ll
A llvm/test/CodeGen/AMDGPU/ashr64_reduce_flags.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/copy-to-reg-frameindex.ll
M llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
M llvm/test/CodeGen/AMDGPU/fneg-combines.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/function-returns.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/mad-combine.ll
M llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
A llvm/test/CodeGen/AMDGPU/neg_ashr64_reduce.ll
M llvm/test/CodeGen/AMDGPU/postra-machine-sink.mir
M llvm/test/CodeGen/AMDGPU/postra-sink-update-dependency.mir
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll
M llvm/test/CodeGen/AMDGPU/sink-after-control-flow-postra.mir
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-AllValidFlagCombinationsV1.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-Invalid-Flag.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-Invalid-NumDescriptors.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-Invalid-RangeType.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-Invalid-RegisterSpace.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Parameters.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor-Invalid-Flags.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor-Invalid-Multiple-Flags.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor_V1.ll
A llvm/test/CodeGen/Hexagon/llvm.sincos.ll
M llvm/test/CodeGen/Inputs/stack-guard-reassign.ll
M llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
M llvm/test/CodeGen/NVPTX/atomics-sm70.ll
M llvm/test/CodeGen/NVPTX/atomics-sm90.ll
M llvm/test/CodeGen/NVPTX/atomics.ll
M llvm/test/CodeGen/NVPTX/bf16-instructions.ll
M llvm/test/CodeGen/NVPTX/branch-fold.mir
M llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
M llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
M llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
M llvm/test/CodeGen/NVPTX/cmpxchg.ll
M llvm/test/CodeGen/NVPTX/compare-int.ll
M llvm/test/CodeGen/NVPTX/distributed-shared-cluster.ll
M llvm/test/CodeGen/NVPTX/extractelement.ll
M llvm/test/CodeGen/NVPTX/f16-instructions.ll
M llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/fast-math.ll
M llvm/test/CodeGen/NVPTX/i1-select.ll
M llvm/test/CodeGen/NVPTX/i128.ll
M llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test1.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test3.ll
M llvm/test/CodeGen/NVPTX/jump-table.ll
M llvm/test/CodeGen/NVPTX/load-with-non-coherent-cache.ll
M llvm/test/CodeGen/NVPTX/lower-aggr-copies.ll
M llvm/test/CodeGen/NVPTX/math-intrins.ll
M llvm/test/CodeGen/NVPTX/sext-setcc.ll
M llvm/test/CodeGen/NVPTX/tid-range.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lround.ll
A llvm/test/CodeGen/RISCV/rvv/llround-sdnode.ll
A llvm/test/CodeGen/RISCV/rvv/lround-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
M llvm/test/CodeGen/RISCV/rvv/xandesvsinload-vln8.ll
M llvm/test/CodeGen/RISCV/rvv/xandesvsinload-vlnu8.ll
M llvm/test/CodeGen/RISCV/zicond-opts.ll
A llvm/test/CodeGen/SPIRV/builtin_intrinsics_32.ll
A llvm/test/CodeGen/SPIRV/builtin_intrinsics_64.ll
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_DispatchThreadID.ll
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_GroupID.ll
M llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_GroupThreadID.ll
M llvm/test/CodeGen/SystemZ/no-postra-sink.mir
M llvm/test/CodeGen/X86/basic-block-address-map-empty-function.ll
M llvm/test/CodeGen/X86/basic-block-address-map-function-sections.ll
M llvm/test/CodeGen/X86/basic-block-address-map-pgo-features.ll
M llvm/test/CodeGen/X86/basic-block-address-map-with-basic-block-sections.ll
M llvm/test/CodeGen/X86/basic-block-address-map-with-mfs.ll
M llvm/test/CodeGen/X86/basic-block-address-map.ll
M llvm/test/CodeGen/X86/ins_subreg_coalesce-3.ll
M llvm/test/CodeGen/X86/postra-ignore-dbg-instrs.mir
A llvm/test/CodeGen/X86/pr147781.ll
M llvm/test/CodeGen/X86/pr38952.mir
M llvm/test/DebugInfo/MIR/X86/postra-subreg-sink.mir
M llvm/test/Instrumentation/MemorySanitizer/X86/avx-intrinsics-x86.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512-intrinsics-upgrade.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512bw-intrinsics-upgrade.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512bw-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512vl-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/x86-vpermi2.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/avx-intrinsics-i386.ll
A llvm/test/MC/AMDGPU/gfx1250_asm_salu_lit64.s
A llvm/test/MC/AMDGPU/gfx1250_asm_valu_lit64.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
A llvm/test/MC/AMDGPU/gfx1250_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_salu_lit64.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_valu_lit64.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
M llvm/test/MC/ELF/mc-dump.s
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-cxx.td
M llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
M llvm/test/TableGen/MixedCasedMnemonic.td
M llvm/test/TableGen/RuntimeLibcallEmitter-calling-conv.td
M llvm/test/TableGen/RuntimeLibcallEmitter.td
M llvm/test/TableGen/SDNodeInfoEmitter/basic.td
A llvm/test/Transforms/Inline/inline-call-with-asm-call.ll
A llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-runtime.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-decreasing.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/commute.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/gather-cost.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/getelementptr.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/getelementptr2.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/reduce-fadd.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/slp-fma-loss.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vectorizable-selects-min-max.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vectorizable-selects-uniform-cmps.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/revec.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/X86/dot-product.ll
M llvm/test/Transforms/SLPVectorizer/extracts-with-undefs.ll
A llvm/test/tools/llvm-mca/RISCV/SiFive7/xsfvfnrclip.s
A llvm/test/tools/llvm-mca/RISCV/SiFive7/xsfvfwmacc.s
A llvm/test/tools/llvm-mca/RISCV/SiFive7/xsfvqmacc.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveX390/xsfvfnrclip.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveX390/xsfvfwmacc.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveX390/xsfvqmacc.s
M llvm/unittests/TableGen/CMakeLists.txt
M llvm/unittests/TargetParser/TripleTest.cpp
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
M llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
M llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp
M llvm/utils/TableGen/DecoderEmitter.cpp
M llvm/utils/TableGen/OptionParserEmitter.cpp
M llvm/utils/gn/secondary/compiler-rt/lib/builtins/BUILD.gn
M llvm/utils/gn/secondary/compiler-rt/lib/builtins/sources.gni
M llvm/utils/gn/secondary/compiler-rt/test/builtins/BUILD.gn
A llvm/utils/gn/secondary/llvm/lib/DWARFCFIChecker/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-mc/BUILD.gn
A llvm/utils/mlgo-utils/combine_training_corpus.py
A llvm/utils/mlgo-utils/extract_ir.py
A llvm/utils/mlgo-utils/make_corpus.py
M llvm/utils/remote-exec.py
M mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCTypeInterfaces.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPDialect.h
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpBase.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrOps.td
M mlir/include/mlir/Dialect/SMT/IR/SMTIntOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/Dialect/Vector/Transforms/LoweringPatterns.h
M mlir/include/mlir/Dialect/Vector/Transforms/Passes.h
M mlir/include/mlir/Dialect/Vector/Transforms/Passes.td
M mlir/include/mlir/Dialect/Vector/Transforms/VectorRewritePatterns.h
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp
M mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
M mlir/lib/Dialect/Tensor/Transforms/SwapExtractSliceWithProducerPatterns.cpp
M mlir/lib/Dialect/Vector/Transforms/CMakeLists.txt
A mlir/lib/Dialect/Vector/Transforms/LowerVectorToFromElementsToShuffleTree.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorDistribute.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransferOpTransforms.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp
A mlir/test/Conversion/AMDGPUToROCDL/load_lds-gfx950.mlir
M mlir/test/Conversion/AMDGPUToROCDL/load_lds.mlir
M mlir/test/Conversion/AMDGPUToROCDL/transpose_load.mlir
M mlir/test/Conversion/VectorToSCF/vector-to-scf.mlir
M mlir/test/Conversion/VectorToXeGPU/contract-to-xegpu.mlir
M mlir/test/Conversion/VectorToXeGPU/load-to-xegpu.mlir
M mlir/test/Conversion/VectorToXeGPU/store-to-xegpu.mlir
M mlir/test/Conversion/VectorToXeGPU/transfer-read-to-xegpu.mlir
M mlir/test/Conversion/VectorToXeGPU/transfer-write-to-xegpu.mlir
M mlir/test/Dialect/Linalg/transform-tile-reduction.mlir
A mlir/test/Dialect/OpenMP/cli-canonical_loop-invalid.mlir
A mlir/test/Dialect/OpenMP/cli-canonical_loop.mlir
A mlir/test/Dialect/OpenMP/cli-unroll-heuristic.mlir
M mlir/test/Dialect/Vector/scalar-vector-transfer-to-memref.mlir
A mlir/test/Dialect/Vector/vector-tofrom-elements-to-shuffle-tree-transforms.mlir
M mlir/test/Dialect/Vector/vector-warp-distribute.mlir
M mlir/test/Dialect/XeGPU/invalid.mlir
M mlir/test/Dialect/XeGPU/ops.mlir
M mlir/test/Dialect/XeGPU/xegpu-blocking.mlir
A mlir/test/Interfaces/TilingInterface/tile-and-fuse-with-reduction-tiling.mlir
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/test/lib/Dialect/XeGPU/TestXeGPUTransforms.cpp
M mlir/test/lib/Interfaces/TilingInterface/TestTilingInterfaceTransformOps.cpp
M mlir/test/lib/Interfaces/TilingInterface/TestTilingInterfaceTransformOps.td
M offload/CMakeLists.txt
A offload/docs/.gitignore
A offload/docs/CMakeLists.txt
A offload/docs/conf.py
A offload/docs/index.rst
M offload/liboffload/API/Common.td
M offload/liboffload/API/Event.td
M offload/liboffload/API/Queue.td
M offload/liboffload/src/OffloadImpl.cpp
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
M offload/plugins-nextgen/common/include/GlobalHandler.h
M offload/plugins-nextgen/cuda/src/rtl.cpp
M offload/test/offloading/disable_default_device.c
M offload/tools/offload-tblgen/APIGen.cpp
M offload/tools/offload-tblgen/CMakeLists.txt
A offload/tools/offload-tblgen/DocGen.cpp
M offload/tools/offload-tblgen/GenCommon.hpp
M offload/tools/offload-tblgen/Generators.hpp
M offload/tools/offload-tblgen/offload-tblgen.cpp
M offload/unittests/OffloadAPI/CMakeLists.txt
M offload/unittests/OffloadAPI/common/Fixtures.hpp
M offload/unittests/OffloadAPI/device_code/CMakeLists.txt
A offload/unittests/OffloadAPI/device_code/global.c
A offload/unittests/OffloadAPI/device_code/global_ctor.c
A offload/unittests/OffloadAPI/device_code/global_dtor.c
A offload/unittests/OffloadAPI/event/olGetEventInfo.cpp
A offload/unittests/OffloadAPI/event/olGetEventInfoSize.cpp
M offload/unittests/OffloadAPI/kernel/olLaunchKernel.cpp
A offload/unittests/OffloadAPI/queue/olGetQueueInfo.cpp
A offload/unittests/OffloadAPI/queue/olGetQueueInfoSize.cpp
A third-party/siphash/include/siphash/SipHash.h
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/__support/FPUtil/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/wchar/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/utils/MPFRWrapper/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/llvm-config.h
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
A utils/bazel/llvm-project-overlay/third-party/siphash/BUILD.bazel
M utils/bazel/llvm_configs/abi-breaking.h.cmake
M utils/bazel/llvm_configs/llvm-config.h.cmake
Log Message:
-----------
Merge branch 'main' into users/kparzysz/spr/v06-omp-future
Compare: https://github.com/llvm/llvm-project/compare/7b42bbe446f3...1585cde21adc
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