[all-commits] [llvm/llvm-project] 343e3c: [LLVM][CodeGen][SVE] Make bf16 fabs/fneg isel cons...

[Paul Walker via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 343e3c6bb827fb2c969f7399bef448bd58e1e43f
      https://github.com/llvm/llvm-project/commit/343e3c6bb827fb2c969f7399bef448bd58e1e43f
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2025-07-10 (Thu, 10 Jul 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    M llvm/test/CodeGen/AArch64/sve-bf16-arith.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith.ll
    M llvm/test/CodeGen/AArch64/sve-merging-unary.ll

  Log Message:
  -----------
  [LLVM][CodeGen][SVE] Make bf16 fabs/fneg isel consistent with fp16. (#147543)

Whilst at first glance there appears to be no native bfloat instructions
to modify the sign bit, this is only the case when FEAT_AFP is
implemented. Without this feature vector FABS/FNEG does not care about
the floating point format beyond needing to know the position of the
sign bit. From what I can see LLVM has no support for FEAT_AFP in terms
of feature detection or ACLE builtins and so I believe the compiler can
work under the assumption the feature is not enabled. In fact, if
FEAT_AFP is enabled then I believe the current isel is likely broken for
half, float and double anyway.



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