[all-commits] [llvm/llvm-project] 71150f: [AArch64] Use SVE2 bit-sel instructions for some b...

[Ricardo Jesus via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 71150f23103a7ac5b9c2ca6d1a3ac082dcd1506a
      https://github.com/llvm/llvm-project/commit/71150f23103a7ac5b9c2ca6d1a3ac082dcd1506a
  Author: Ricardo Jesus <rjj at nvidia.com>
  Date:   2025-07-10 (Thu, 10 Jul 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/bsl.ll
    M llvm/test/CodeGen/AArch64/eor3.ll
    M llvm/test/CodeGen/AArch64/sve-pred-selectop.ll
    M llvm/test/CodeGen/AArch64/sve2-bsl.ll

  Log Message:
  -----------
  [AArch64] Use SVE2 bit-sel instructions for some binary patterns. (#147544)

We can use NBSL/BSL2N to implement the following operations via the
corresponding identities:
* EON(a, b) = BSL2N(a, a, b) = BSL2N(b, b, a)
* NAND(a, b) = NBSL(a, b, b) = NBSL(b, a, a)
* NOR(a, b) = NBSL(a, b, a) = NBSL(b, a, b)
* ORN(a, b) = BSL2N(a, b, a)

Most of these operations are currently lowered into at least two
instructions because we don't have dedicated Neon/SVE instructions
for them. With the appropriate pattern of NBSL/BSL2N we can lower
them in a single instruction.

We could also use NBSL to implement an unpredicated NOT(a) =
NBSL(a, a, a), but because of the tied register constraint, this
may not always be profitable.



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