[all-commits] [llvm/llvm-project] fcd4a2: [CodeGen][NewPM] Port "PostRAMachineSink" pass to ...

[Vikram Hegde via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fcd4a2fe7adfd0a58029583350692f3627d396e4
      https://github.com/llvm/llvm-project/commit/fcd4a2fe7adfd0a58029583350692f3627d396e4
  Author: Vikram Hegde <115221833+vikramRH at users.noreply.github.com>
  Date:   2025-07-10 (Thu, 10 Jul 2025)

  Changed paths:
    A llvm/include/llvm/CodeGen/PostRAMachineSink.h
    M llvm/include/llvm/InitializePasses.h
    M llvm/include/llvm/Passes/CodeGenPassBuilder.h
    M llvm/include/llvm/Passes/MachinePassRegistry.def
    M llvm/lib/CodeGen/CodeGen.cpp
    M llvm/lib/CodeGen/MachineSink.cpp
    M llvm/lib/Passes/PassBuilder.cpp
    M llvm/test/CodeGen/AArch64/bisect-post-ra-machine-sink.mir
    M llvm/test/CodeGen/AArch64/post-ra-machine-sink.mir
    M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
    M llvm/test/CodeGen/AMDGPU/postra-machine-sink.mir
    M llvm/test/CodeGen/AMDGPU/postra-sink-update-dependency.mir
    M llvm/test/CodeGen/AMDGPU/sink-after-control-flow-postra.mir
    M llvm/test/CodeGen/SystemZ/no-postra-sink.mir
    M llvm/test/CodeGen/X86/postra-ignore-dbg-instrs.mir
    M llvm/test/CodeGen/X86/pr38952.mir
    M llvm/test/DebugInfo/MIR/X86/postra-subreg-sink.mir

  Log Message:
  -----------
  [CodeGen][NewPM] Port "PostRAMachineSink" pass to NPM (#129690)



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