[all-commits] [llvm/llvm-project] c2a818: [RISCV] Add scheduling info for XSfvqmaccdod/qoq a...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c2a818f48bb5a1cda6d94f5e1956019678c67d89
      https://github.com/llvm/llvm-project/commit/c2a818f48bb5a1cda6d94f5e1956019678c67d89
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-07-09 (Wed, 09 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
    M llvm/lib/Target/RISCV/RISCVSchedAndes45.td
    M llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td
    M llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
    M llvm/lib/Target/RISCV/RISCVSchedRocket.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
    M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
    M llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
    M llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td
    M llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td
    M llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
    M llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
    M llvm/lib/Target/RISCV/RISCVScheduleXSf.td
    A llvm/test/tools/llvm-mca/RISCV/SiFive7/xsfvfwmacc.s
    A llvm/test/tools/llvm-mca/RISCV/SiFive7/xsfvqmacc.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveX390/xsfvfwmacc.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveX390/xsfvqmacc.s

  Log Message:
  -----------
  [RISCV] Add scheduling info for XSfvqmaccdod/qoq and XSfvfwmaccqqq instructions (#147626)

XSfvqmaccdod/qoq and XSfvfwmaccqqq are SiFive's small-size matrix
multiplication extensions. This patches add scheduling info for their
instructions along with six new SchedReadWrite.



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