[all-commits] [llvm/llvm-project] d59d26: [RISCV] Add scheduling info for XSfvfnrclipxfqf in...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d59d2652c8724b0039249929f5bb5c38bcecc0da
      https://github.com/llvm/llvm-project/commit/d59d2652c8724b0039249929f5bb5c38bcecc0da
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-07-09 (Wed, 09 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
    M llvm/lib/Target/RISCV/RISCVSchedAndes45.td
    M llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td
    M llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
    M llvm/lib/Target/RISCV/RISCVSchedRocket.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
    M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
    M llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
    M llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td
    M llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td
    M llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
    M llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
    M llvm/lib/Target/RISCV/RISCVScheduleXSf.td
    A llvm/test/tools/llvm-mca/RISCV/SiFive7/xsfvfnrclip.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveX390/xsfvfnrclip.s

  Log Message:
  -----------
  [RISCV] Add scheduling info for XSfvfnrclipxfqf instructions (#147586)

This patch adds scheduling data for the XSfvfnrclipxfqf instruction,
which narrows / clips FP32 data to INT8 according to value range
specified by a scalar register. Three new SchedReadWrites are
introduced.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications