[all-commits] [llvm/llvm-project] 962c42: [MLIR][AArch64] Change some tests to ensure SVE ve...

[Momchil Velikov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 962c4217bc68c7b9a138b92dd7a30e2a277e479b
      https://github.com/llvm/llvm-project/commit/962c4217bc68c7b9a138b92dd7a30e2a277e479b
  Author: Momchil Velikov <momchil.velikov at arm.com>
  Date:   2025-07-09 (Wed, 09 Jul 2025)

  Changed paths:
    M mlir/lib/ExecutionEngine/ArmRunnerUtils.cpp
    M mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/pack-scalable-inner-tile.mlir
    M mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/pack-unpack-scalable-inner-tile.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/test-scalable-deinterleave.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/test-setArmVLBits.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/transfer-read-scalable-non-trailing.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/vector-contract-i8mm.mlir

  Log Message:
  -----------
  [MLIR][AArch64] Change some tests to ensure SVE vector length is the same throughout the function (#147506)

This change only applies to functions the can be reasonably expected to
use SVE registers.

Modifying vector length in the middle of a function might cause
incorrect stack deallocation if there are callee-saved SVE registers or
incorrect access to SVE stack slots.

Addresses (non-issue) https://github.com/llvm/llvm-project/issues/143670



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