[all-commits] [llvm/llvm-project] 853e9b: [AMDGPU] Examine instructions in the pending queue...

[Austin Kerbow via All-commits]

  Branch: refs/heads/users/kerbowa/reserved-resource-hazard
  Home:   https://github.com/llvm/llvm-project
  Commit: 853e9bd0151140a5dcbba18d3695d4c5f81559de
      https://github.com/llvm/llvm-project/commit/853e9bd0151140a5dcbba18d3695d4c5f81559de
  Author: Austin Kerbow <Austin.Kerbow at amd.com>
  Date:   2025-07-08 (Tue, 08 Jul 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
    M llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
    M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.large.mir
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.small.mir
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.single.2b.mir
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.single.2c.mir
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
    M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-attr.mir
    M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
    M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
    M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
    M llvm/test/CodeGen/AMDGPU/sched-barrier-pre-RA.mir
    M llvm/test/CodeGen/AMDGPU/sched-group-barrier-pipeline-solver.mir
    M llvm/test/CodeGen/AMDGPU/sched-group-barrier-pre-RA.mir

  Log Message:
  -----------
  [AMDGPU] Examine instructions in the pending queues during pre-RA scheduling

Examine instructions in the pending queue when scheduling. This makes
instructions visible to scheduling heuristics even when they aren't
immediately issuable due to hardware resource constraints.

The scheduler has two hardware resource modeling modes: an in-order mode
where instructions must be ready to issue before scheduling, and
out-of-order models where instructions are always visible to heuristics.
Special handling exists for unbuffered processor resources in
out-of-order models. These resources can cause pipeline stalls when used
back-to-back, so they're typically avoided. However, for AMDGPU targets,
managing register pressure and reducing spilling is critical enough to
justify exceptions to this approach.

This change enables examination of instructions that can't be
immediately issued because they use an already occupied unbuffered
resource. By making these instructions visible to scheduling heuristics
anyway, we gain more flexibility in scheduling decisions, potentially
allowing better register pressure and hardware resouce management.



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