[all-commits] [llvm/llvm-project] 004060: [MLIR][AArch64] Change some tests to ensure SVE ve...

[Momchil Velikov via All-commits]

  Branch: refs/heads/users/momchil-velikov/runner-crash
  Home:   https://github.com/llvm/llvm-project
  Commit: 004060dee229ed3d713ec7f52d2a2f6a65a4bbc8
      https://github.com/llvm/llvm-project/commit/004060dee229ed3d713ec7f52d2a2f6a65a4bbc8
  Author: Momchil Velikov <momchil.velikov at arm.com>
  Date:   2025-07-08 (Tue, 08 Jul 2025)

  Changed paths:
    M mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/pack-scalable-inner-tile.mlir
    M mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/pack-unpack-scalable-inner-tile.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/transfer-read-scalable-non-trailing.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/vector-contract-i8mm.mlir

  Log Message:
  -----------
  [MLIR][AArch64] Change some tests to ensure SVE vector length is the same on function entry/exit

This change only applies to functions the can be reasonable expected to use SVE registers.

Modifying vector length in the middle of a function might cause incorrect stack deallocation
if there are callee-saved SVE registers.



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