[all-commits] [llvm/llvm-project] 884f73: [RISCV] Add compress patterns for Xqcilia instruct...

[Sudharsan Veeravalli via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 884f7382934dba80bac13858940202be7b72e7c4
      https://github.com/llvm/llvm-project/commit/884f7382934dba80bac13858940202be7b72e7c4
  Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
  Date:   2025-07-08 (Tue, 08 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    M llvm/test/MC/RISCV/xqcilia-valid.s

  Log Message:
  -----------
  [RISCV] Add compress patterns for Xqcilia instructions with tied-operands (#147242)

Now that the compress instruction emitter supports source instructions
with tied-operands, add some patterns for such instructions in the
Xqcilia extension.



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