[all-commits] [llvm/llvm-project] 3f33e7: [RISCV] Add Andes XAndesVSIntLoad (Andes Vector IN...

[Jim Lin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3f33e7ba5b08a97939280e539ad20a34d54b2719
      https://github.com/llvm/llvm-project/commit/3f33e7ba5b08a97939280e539ad20a34d54b2719
  Author: Jim Lin <jim at andestech.com>
  Date:   2025-07-07 (Mon, 07 Jul 2025)

  Changed paths:
    M clang/test/Driver/print-supported-extensions-riscv.c
    M clang/test/Preprocessor/riscv-target-features-andes.c
    M llvm/docs/RISCVUsage.rst
    M llvm/docs/ReleaseNotes.md
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/CodeGen/RISCV/features-info.ll
    A llvm/test/MC/RISCV/xandesvsintload-valid.s
    M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

  Log Message:
  -----------
  [RISCV] Add Andes XAndesVSIntLoad (Andes Vector INT4 Load) extension (#147005)

The spec can be found at:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release.

This patch only implements MC support for XAndesVSIntLoad.

---------

Co-authored-by: Lino Hsing-Yu Peng <linopeng at andestech.com>



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