[all-commits] [llvm/llvm-project] 1f3f98: [VPlan] Fix crash when narrowing interleave-groups...

Fri Jul 4 15:46:29 PDT 2025

  Branch: refs/heads/users/MaskRay/spr/mc-centralize-x86-pc-relative-fixup-adjustment-in-mcassembler
  Home:   https://github.com/llvm/llvm-project
  Commit: 1f3f9874b025057add56bfe27e792bcb04bde43e
      https://github.com/llvm/llvm-project/commit/1f3f9874b025057add56bfe27e792bcb04bde43e
  Author: Florian Hahn <flo at fhahn.com>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
    M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-cost.ll

  Log Message:
  -----------
  [VPlan] Fix crash when narrowing interleave-groups with reuse.

If a wide load is used multiple times in an expression, it will be
narrowed the first time. Re-use the already narrowed op in that case to
fix crash.

  Commit: 454e4e3e29d835d4487799c014223a045f3d1d84
      https://github.com/llvm/llvm-project/commit/454e4e3e29d835d4487799c014223a045f3d1d84
  Author: Ivan Butygin <ivan.butygin at gmail.com>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M mlir/lib/IR/AffineExpr.cpp
    M mlir/test/Dialect/Affine/simplify-structures.mlir
    M mlir/test/IR/affine-map.mlir
    M mlir/unittests/IR/AffineExprTest.cpp

  Log Message:
  -----------
  [mlir][AffineExpr] Order arguments in the commutative affine exprs (#146895)

Order symbol/dim arguments by position and put dims before symbols. This
is to help affine simplifications.

  Commit: 6db02dc4311b3ee52ec6e7e5e5cafb2600e7b30f
      https://github.com/llvm/llvm-project/commit/6db02dc4311b3ee52ec6e7e5e5cafb2600e7b30f
  Author: Joseph Huber <huberjn at outlook.com>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M clang/include/clang/Driver/Options.td
    M clang/lib/Driver/Driver.cpp
    M clang/lib/Driver/ToolChain.cpp
    M clang/lib/Driver/ToolChains/CommonArgs.cpp
    M clang/lib/Frontend/CompilerInvocation.cpp
    M clang/test/Driver/amdgpu-openmp-sanitize-options.c
    M clang/test/Driver/hip-options.hip
    M flang/lib/Frontend/CompilerInvocation.cpp
    M flang/test/Driver/omp-driver-offload.f90

  Log Message:
  -----------
  [Clang] Introduce `--offload-targets` for `-fopenmp-targets` (#146594)

Summary:
This patch is mostly an NFC that renames the existing `-fopenmp-targets`
into `--offload-targets`. Doing this early to simplify a follow-up patch
that will hopefully allow this syntax to be used more generically over
the existing `--offload` syntax (which I think is mostly unmaintained
now.). Following in the well-trodden path of trying to pull language
specific offload options into generic ones, but right now this is still
just OpenMP specific.

  Commit: 07286b1fcdecf2aa557ae401946e265c8dab2c68
      https://github.com/llvm/llvm-project/commit/07286b1fcdecf2aa557ae401946e265c8dab2c68
  Author: jjasmine <jjasmine at igalia.com>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M llvm/lib/Analysis/InstructionSimplify.cpp
    M llvm/lib/Analysis/ValueTracking.cpp
    M llvm/test/Transforms/InstSimplify/call.ll
    M llvm/test/Transforms/InstSimplify/fold-intrinsics.ll
    M llvm/test/Transforms/InstSimplify/saturating-add-sub.ll
    M llvm/unittests/Analysis/ValueTrackingTest.cpp

  Log Message:
  -----------
  [InstCombine] Propagate poison pow[i], [us]add, [us]sub and [us]mul (#146750)

Fixes #146560 as well as propagate poison for [us]add, [us]sub and
[us]mul

  Commit: 07ae19c132e1b0adbdb3cc036b9f50624e2ed1b7
      https://github.com/llvm/llvm-project/commit/07ae19c132e1b0adbdb3cc036b9f50624e2ed1b7
  Author: Luke Lau <luke at igalia.com>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
    M llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int.ll
    R llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops-mir.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
    A llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir
    M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll

  Log Message:
  -----------
  [RISCV] Move performCombineVMergeAndVOps to RISCVVectorPeephole (#144076)

This moves the peephole that folds vmerges into its operands into
RISCVVectorPeephole. This will also allow us to eventually commute
instructions to allow folding, see #141885 and #70042

Most of the test diffs are due to the slight change in instruction
ordering.

For now doPeepholeMaskedRVV is kept even though its a duplicate of
RISCVVectorPeephole::convertToUnmasked to minimize the diff, I plan on
removing it in a separate patch as it causes some instructions to be
shuffled around.

Similarly, this runs foldVMergeToMask before the other peepholes to
minimize the diff for now.

rvv-peephole-vmerge-vops-mir.ll was replaced with a dedicated
vmerge-peephole.mir test.

  Commit: eb84af49a1bfd6795b63f46588ab733920c4e43f
      https://github.com/llvm/llvm-project/commit/eb84af49a1bfd6795b63f46588ab733920c4e43f
  Author: Fangrui Song <i at maskray.me>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp

  Log Message:
  -----------
  AArch64MCCodeEmitter: Set PCRel at fixup creation

Avoid reliance on the MCAssembler::evaluateFixup workaround checking
MCFixupKindInfo::FKF_IsPCRel. Remove discouraged MCFixupKind uses.

  Commit: d337e09e73b313ce44cdb8c634e67fd2ae7bd6a8
      https://github.com/llvm/llvm-project/commit/d337e09e73b313ce44cdb8c634e67fd2ae7bd6a8
  Author: Fangrui Song <i at maskray.me>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp

  Log Message:
  -----------
  SystemZMCCodeEmitter: Set PCRel at fixup creation

Avoid reliance on the MCAssembler::evaluateFixup workaround checking
MCFixupKindInfo::FKF_IsPCRel.

  Commit: 83fbd86909111510f973d8e1c4214022368ef810
      https://github.com/llvm/llvm-project/commit/83fbd86909111510f973d8e1c4214022368ef810
  Author: Fangrui Song <i at maskray.me>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp

  Log Message:
  -----------
  SPARCMCCodeEmitter: Set PCRel at fixup creation

  Commit: 7d500b115db5577c206f162b29e90811f1f66a1c
      https://github.com/llvm/llvm-project/commit/7d500b115db5577c206f162b29e90811f1f66a1c
  Author: Fangrui Song <i at maskray.me>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M llvm/lib/MC/MCAssembler.cpp
    M llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
    M llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp

  Log Message:
  -----------
  SPARC: Remove unneeded MCFixupKindInfo::FKF_IsPCRel

SPARC now sets PCRel at fixup creation and no longer needs to the
MCAssembler::evaluateFixup workaround that checks
MCFixupKindInfo::FKF_IsPCRel.

  Commit: a7f6b4148d78aab7c0c016b88c2f86fffbce65fc
      https://github.com/llvm/llvm-project/commit/a7f6b4148d78aab7c0c016b88c2f86fffbce65fc
  Author: Fangrui Song <i at maskray.me>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M clang/include/clang/Driver/Options.td
    M clang/lib/Driver/Driver.cpp
    M clang/lib/Driver/ToolChain.cpp
    M clang/lib/Driver/ToolChains/CommonArgs.cpp
    M clang/lib/Frontend/CompilerInvocation.cpp
    M clang/test/Driver/amdgpu-openmp-sanitize-options.c
    M clang/test/Driver/hip-options.hip
    M flang/lib/Frontend/CompilerInvocation.cpp
    M flang/test/Driver/omp-driver-offload.f90
    M llvm/lib/Analysis/InstructionSimplify.cpp
    M llvm/lib/Analysis/ValueTracking.cpp
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
    M llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
    M llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
    M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
    M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
    M llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int.ll
    R llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops-mir.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
    A llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir
    M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
    M llvm/test/Transforms/InstSimplify/call.ll
    M llvm/test/Transforms/InstSimplify/fold-intrinsics.ll
    M llvm/test/Transforms/InstSimplify/saturating-add-sub.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-cost.ll
    M llvm/unittests/Analysis/ValueTrackingTest.cpp
    M mlir/lib/IR/AffineExpr.cpp
    M mlir/test/Dialect/Affine/simplify-structures.mlir
    M mlir/test/IR/affine-map.mlir
    M mlir/unittests/IR/AffineExprTest.cpp

  Log Message:
  -----------
  rebase

Created using spr 1.3.5-bogner

Compare: https://github.com/llvm/llvm-project/compare/c5eb84e156d5...a7f6b4148d78

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