[all-commits] [llvm/llvm-project] 522d74: [lldb][test] Run generic set formatter test-case o...
Krzysztof Parzyszek via All-commits
all-commits at lists.llvm.org
Thu Jul 3 10:20:57 PDT 2025
Branch: refs/heads/users/kparzysz/spr/d02-clang-parser
Home: https://github.com/llvm/llvm-project
Commit: 522d743545e6e175315f4b96037defbe08fa2338
https://github.com/llvm/llvm-project/commit/522d743545e6e175315f4b96037defbe08fa2338
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/set/TestDataFormatterGenericSet.py
Log Message:
-----------
[lldb][test] Run generic set formatter test-case on specified STL (#146882)
Previously the parameter wasn't respected. So we would only run the test
with whatever stdlib the `Makefile.rules` deduced.
Confirmed that
```
lldb-dotest -p TestDataFormatterGenericSet.py --category libstdcxx
```
passes on my machine.
Commit: 34f124b06ffd3a4e5befafe3cf5daf7753f415ff
https://github.com/llvm/llvm-project/commit/34f124b06ffd3a4e5befafe3cf5daf7753f415ff
Author: Matthias Springer <me at m-sp.org>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M mlir/examples/toy/Ch6/mlir/LowerToLLVM.cpp
M mlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp
Log Message:
-----------
[mlir][toy] Use `make_early_inc_range` when erasing ops during iteration (#146892)
Use `make_early_inc_range` when erasing operations from a block to make
sure that the iterator is not invalidated. The previous implementation
happened to work on a "normal" dialect conversion because some IR
modifications are delayed. It no longer works with a One-Shot Dialect
Conversion. The new One-Shot Dialect Conversion API is more similar to
the normal rewriter API.
Commit: a88e286aefbf25d504239badaa1a908c0a56c78e
https://github.com/llvm/llvm-project/commit/a88e286aefbf25d504239badaa1a908c0a56c78e
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/vector/Makefile
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/vector/TestDataFormatterStdVector.py
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/vector/main.cpp
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/vector/Makefile
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/vector/TestDataFormatterLibcxxVector.py
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/vector/main.cpp
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libstdcpp/vector/Makefile
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libstdcpp/vector/TestDataFormatterStdVector.py
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libstdcpp/vector/main.cpp
Log Message:
-----------
[lldb][test] Consolidate libstdc++ and libc++ vector formatter tests into generic test (#146885)
The libstdc++ test was a subset of the tests in libc++. This test moves
the libc++ test into `generic` and removes the `libstdc++` tests. I
retained the `-D_GLIBCXX_DEBUG` test cases though.
Split out from https://github.com/llvm/llvm-project/pull/146740
Commit: 2b49d36c081f4557cb17d176e17269c2c8843243
https://github.com/llvm/llvm-project/commit/2b49d36c081f4557cb17d176e17269c2c8843243
Author: parabola94 <heavybaby5000 at toki.waseda.jp>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M flang/CMakeLists.txt
Log Message:
-----------
[flang][cmake] Separate FLANG_INCLUDE_TOOLS from FLANG_BUILD_TOOLS (#145005)
If we disable `FLANG_BUILD_TOOLS`, not only building the tools but also
generating the targets for them is skipped now. On the other hand, llvm
separates them into `LLVM_BUILD_TOOLS` and `LLVM_INCLUDE_TOOLS`.
This patch introduces `FLANG_INCLUDE_TOOLS` for the distinction.
Commit: 3ba161bb753000400caeff6e1ca6b8a860d0dacc
https://github.com/llvm/llvm-project/commit/3ba161bb753000400caeff6e1ca6b8a860d0dacc
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
A llvm/test/CodeGen/AArch64/sve-merging-unary.ll
Log Message:
-----------
[NFC][LLVM][CodeGen][SVE] Add merging unary operation tests.
Commit: 23104a74e79f208d467830058111fd883dfcb489
https://github.com/llvm/llvm-project/commit/23104a74e79f208d467830058111fd883dfcb489
Author: Sirui Mu <msrlancern at gmail.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/Interfaces/CIROpInterfaces.td
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenCall.h
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
M clang/test/CIR/CodeGen/builtin_call.cpp
M clang/test/CIR/CodeGen/builtin_printf.cpp
M clang/test/CIR/CodeGen/call.cpp
Log Message:
-----------
[CIR] Add nothrow attribute to the call operation (#145178)
This patch adds extra function attributes to the `cir.call` operation.
The extra attributes now may contain a single `cir.nothrow` attribute
that indicates whether the callee throws.
Commit: a282c685806713321396c4230d32c0e2f79a1e8d
https://github.com/llvm/llvm-project/commit/a282c685806713321396c4230d32c0e2f79a1e8d
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineX86AddSub - pull out repeated getOperand() call. NFC.
Commit: 51ff8f2f7e4c997170be8f3b29f8bdd37d4a2a78
https://github.com/llvm/llvm-project/commit/51ff8f2f7e4c997170be8f3b29f8bdd37d4a2a78
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] foldXor1SetCC - pull out repeated SDLoc. NFC.
Commit: f019c890087a044cef031002e76e7626ff912deb
https://github.com/llvm/llvm-project/commit/f019c890087a044cef031002e76e7626ff912deb
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] foldXorTruncShiftIntoCmp - pull out repeated SDLoc. NFC.
Commit: 4b9f622ca94d8f4c0102560cb15c99f4e0013f99
https://github.com/llvm/llvm-project/commit/4b9f622ca94d8f4c0102560cb15c99f4e0013f99
Author: Sirui Mu <msrlancern at gmail.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
A clang/test/CIR/CodeGen/builtin_bit.cpp
Log Message:
-----------
[CIR] Bit manipulation builtin functions (#146529)
This patch adds CIR support for the following families of bit
manipulation builtin functions:
- `__builtin_clrsb`, represented by the `cir.bit.clrsb` operation
- `__builtin_ctz`, represented by the `cir.bit.clz` operation
- `__builtin_clz`, represented by the `cir.bit.ctz` operation
- `__builtin_parity`, represented by the `cir.bit.parity` operation
- `__builtin_popcount`, represented by the `cir.bit.popcnt` operation
The `__builtin_ffs` builtin function is not included in this patch
because the current CIRGen would emit it as a library call to `@ffs`.
Commit: 6c23e9e82c36afc1e68593cf7e4880612216c790
https://github.com/llvm/llvm-project/commit/6c23e9e82c36afc1e68593cf7e4880612216c790
Author: sc-clulzze <d.marakulin at syntacore.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
Log Message:
-----------
[RISCV] Fix crash when trying to remove segment (#146524)
LiveInterval DefLI can be consisting of multiple segments, and SlotIndex
NewDefSI can be inside any of them. Currenty it is assumed that NewDefSI
belongs to the first segment, and when trying to call removeSegment,
clang crashes since there is no segment containing [DefLI.beginIndex(),
NewDefSI]
FIxes https://github.com/llvm/llvm-project/issues/146518
Commit: 46b4ca8e9869ad6e51b9d22bb08e32b37ccff03a
https://github.com/llvm/llvm-project/commit/46b4ca8e9869ad6e51b9d22bb08e32b37ccff03a
Author: Tony Varghese <tonypalampalliyil at gmail.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
M llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
M llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
M llvm/test/CodeGen/PowerPC/xxeval-vselect-x-or.ll
M llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
Log Message:
-----------
[NFC][PowerPC] Pre-commit testcases for locking down the xxsel instructions for ternary patterns (#146764)
Pre-commit test case for exploitation of `xxsel` for ternary operations
of the pattern. This adds support for `v4i32`, `v2i64`, `v16i8` and
`v8i16` operand types for the following patterns.
```
ternary(A, X, and(B,C))
ternary(A, X, B)
ternary(A, X, C)
ternary(A, X, xor(B,C))
ternary(A,X,or(B,C))
```
Exploitation of xxeval to be added later.
Co-authored-by: Tony Varghese <tony.varghese at ibm.com>
Commit: 0f717044ff1ab3967624807b3e061fb5deaf8c77
https://github.com/llvm/llvm-project/commit/0f717044ff1ab3967624807b3e061fb5deaf8c77
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] lowerX86FPLogicOp - use MVT::changeVectorElementTypeToInteger(). NFC.
Commit: 5df748dd329ea5590f9dcc8e643413d26554be00
https://github.com/llvm/llvm-project/commit/5df748dd329ea5590f9dcc8e643413d26554be00
Author: Kazu Hirata <kazu at google.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M clang/lib/Sema/SemaDeclCXX.cpp
Log Message:
-----------
[Sema] Remove an unnecessary cast (NFC) (#146808)
The only use of BW is to initialize BitWidth. This patch renames BW
to BitWdith while removing the cast statement.
Commit: a244907922354ead70182002af1d10067bd2b8b6
https://github.com/llvm/llvm-project/commit/a244907922354ead70182002af1d10067bd2b8b6
Author: Kazu Hirata <kazu at google.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M clang/include/clang/Sema/DeclSpec.h
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
M clang/lib/Driver/ToolChains/HIPSPV.cpp
M clang/tools/clang-installapi/ClangInstallAPI.cpp
M clang/tools/clang-installapi/Options.cpp
Log Message:
-----------
[clang] Use range-based for loops (NFC) (#146811)
Note that LLVM Coding Standards discourages std::for_each and
llvm::for_each unless the callable object already exists.
Commit: 59d641a2dab475f6ab0ab1308b1d6dd641dccb6a
https://github.com/llvm/llvm-project/commit/59d641a2dab475f6ab0ab1308b1d6dd641dccb6a
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
A clang/test/CIR/CodeGen/non-type-template-param.cpp
Log Message:
-----------
[CIR] Upstream support for SubstNonTypeTemplateParmExpr (#146751)
Upstream support for SubstNonTypeTemplateParmExpr
Commit: e93a34662f1471c17f2afa7461ec71bf7913b984
https://github.com/llvm/llvm-project/commit/e93a34662f1471c17f2afa7461ec71bf7913b984
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp
M clang/test/CIR/CodeGen/complex.cpp
Log Message:
-----------
[CIR] Upstream SubstNonTypeTemplateParmExpr support for ComplexType (#146755)
Upstream SubstNonTypeTemplateParmExpr support for ComplexType
https://github.com/llvm/llvm-project/issues/141365
Commit: 21c4fbd4235a964e87c10b1008c61f9a2e6eb9a9
https://github.com/llvm/llvm-project/commit/21c4fbd4235a964e87c10b1008c61f9a2e6eb9a9
Author: Mikhail R. Gadelha <mikhail at igalia.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
Log Message:
-----------
[RISCV][VLOPT] Pre-commit test for adding support for vfrec7.v
Signed-off-by: Mikhail R. Gadelha <mikhail at igalia.com>
Commit: 61a0653cc6101ca78929482367ef5f2f9f324b2e
https://github.com/llvm/llvm-project/commit/61a0653cc6101ca78929482367ef5f2f9f324b2e
Author: Luke Lau <luke at igalia.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-fixed-order-recurrence.ll
Log Message:
-----------
[VPlan] Fix first-order splices without header mask not using EVL (#146672)
This fixes a buildbot failure with EVL tail folding after #144666:
https://lab.llvm.org/buildbot/#/builders/132/builds/1653
For a first-order recurrence to be correct with EVL tail folding we need
to convert splices to vp splices with the EVL operand.
Originally we did this by looking for users of the header mask and its
users, and converting it in createEVLRecipe.
However after #144666 a FOR splice might not actually use the header
mask if it's based off e.g. an induction variable, and so we wouldn't
pick it up in createEVLRecipe.
This fixes this by converting FOR splices separately in a loop over all
recipes in the plan, regardless of whether or not it uses the header
mask.
I think there was some conflation in createEVLRecipe between what was an
optimisation and what was needed for correctness. Most of the transforms
in it just exist to optimize the mask away and we should still emit
correct code without them. So I've renamed it to make the separation
clearer.
Commit: e8f491fc973e27c657b5de4e8d0b80ac566403ab
https://github.com/llvm/llvm-project/commit/e8f491fc973e27c657b5de4e8d0b80ac566403ab
Author: Kazu Hirata <kazu at google.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M mlir/lib/IR/AffineMap.cpp
M mlir/lib/IR/AsmPrinter.cpp
M mlir/lib/IR/Block.cpp
M mlir/lib/IR/Builders.cpp
M mlir/lib/IR/BuiltinAttributes.cpp
M mlir/lib/IR/BuiltinDialect.cpp
M mlir/lib/IR/BuiltinTypeInterfaces.cpp
M mlir/lib/IR/BuiltinTypes.cpp
M mlir/lib/IR/Dialect.cpp
M mlir/lib/IR/Dominance.cpp
M mlir/lib/IR/MLIRContext.cpp
M mlir/lib/IR/Operation.cpp
M mlir/lib/IR/OperationSupport.cpp
M mlir/lib/IR/TypeRange.cpp
M mlir/lib/IR/Unit.cpp
Log Message:
-----------
[mlir] Remove unused includes (NFC) (#146812)
Commit: b6e113a149bfa196a90a260f69f06b0070bd3670
https://github.com/llvm/llvm-project/commit/b6e113a149bfa196a90a260f69f06b0070bd3670
Author: Bernhard M. Wiedemann <githubbmwprimary2025 at lsmod.de>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M openmp/runtime/tools/message-converter.py
Log Message:
-----------
Drop timestamp in generated source code (#146822)
Fixes #72206
This helps reproducible builds of libomp.so --
probably because LLVM's LTO computed a hash of inputs to generate its
symbol names.
note: if it is desired to keep the timestamp, we could instead use
[`SOURCE_DATE_EPOCH`](https://reproducible-builds.org/docs/source-date-epoch/)
to make it deterministic.
This PR was done while working on [reproducible builds for
openSUSE](https://en.opensuse.org/openSUSE:Reproducible_Builds).
Commit: 8ac7210b7f0ad49ae7809bf6a9faf2f7433384b0
https://github.com/llvm/llvm-project/commit/8ac7210b7f0ad49ae7809bf6a9faf2f7433384b0
Author: alex-t <alex-t at users.noreply.github.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll
A llvm/test/CodeGen/AMDGPU/test_isel_single_lane.ll
M llvm/unittests/CodeGen/SelectionDAGAddressAnalysisTest.cpp
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
Log Message:
-----------
[AMDGPU] SelectionDAG divergence tracking should take into account Target divergency. (#144947)
If a kernel is known to be executing only a single lane, IR
UniformityAnalysis will take note of that (via
GCNTTIImpl::hasBranchDivergence) and report that all values are uniform.
SelectionDAG's built-in divergence tracking should do the same.
Commit: 4cd9c894d1ef27c26a825be5dac2824b7c30659b
https://github.com/llvm/llvm-project/commit/4cd9c894d1ef27c26a825be5dac2824b7c30659b
Author: Kazu Hirata <kazu at google.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M llvm/lib/DebugInfo/PDB/Native/GSIStreamBuilder.cpp
Log Message:
-----------
[DebugInfo] Remove an unnecessary cast (NFC) (#146809)
Mem is already of uint8_t *.
Commit: 77f0f812b4195bfde3b8d2ddb4b85f78f41a628f
https://github.com/llvm/llvm-project/commit/77f0f812b4195bfde3b8d2ddb4b85f78f41a628f
Author: Akira Hatanaka <ahatanak at gmail.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M clang/lib/Basic/DiagnosticIDs.cpp
M clang/test/SemaObjCXX/arc-0x.mm
Log Message:
-----------
[Sema][ObjC] Treat unknown selector messages as unrecoverable errors under ARC (#146803)
Fixes a CodeGen crash observed when C++ auto variable types remained
non-deduced due to a message being sent with an unknown selector under
ARC.
By treating these instances as an unrecoverable error, we prevent the
compiler from proceeding to CodeGen with fundamentally incorrect code.
rdar://144394403
Commit: a695d6b9a726d0059d9bf80341ee567c1153286c
https://github.com/llvm/llvm-project/commit/a695d6b9a726d0059d9bf80341ee567c1153286c
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M llvm/lib/Analysis/HashRecognize.cpp
M llvm/test/Analysis/HashRecognize/cyclic-redundancy-check.ll
Log Message:
-----------
[HashRecognize] Check TC against bitwidth of LHSAux (#144881)
The trip-count of a CRC algorithm can legitimately be greater than the
bitwidth of the result: what it cannot exceed is the bitwidth of the
data, or LHSAux. crc8.le.tc16 is now successfully recognized as a CRC
algorithm.
Commit: 1aa39690aa73ad227ef1fb94ddb340d462cfea01
https://github.com/llvm/llvm-project/commit/1aa39690aa73ad227ef1fb94ddb340d462cfea01
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp
M clang/test/CIR/CodeGen/complex.cpp
Log Message:
-----------
[CIR] Upstream UnaryDeref support for ComplexType (#146757)
Upstream UnaryDeref support for ComplexType
https://github.com/llvm/llvm-project/issues/141365
Commit: 795b17d0b821e44f89d021dec18e9fdb28930ff6
https://github.com/llvm/llvm-project/commit/795b17d0b821e44f89d021dec18e9fdb28930ff6
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
A llvm/include/llvm/Frontend/OpenMP/DirectiveNameParser.h
M llvm/lib/Frontend/OpenMP/CMakeLists.txt
A llvm/lib/Frontend/OpenMP/DirectiveNameParser.cpp
M llvm/unittests/Frontend/CMakeLists.txt
A llvm/unittests/Frontend/OpenMPDirectiveNameParserTest.cpp
Log Message:
-----------
[Frontend][OpenMP] Implement directive name parser (#146776)
Implement a state machine that consumes tokens (words delimited by white
space), and returns the corresponding directive id, or fails if the tokens
did not form a valid name.
Commit: abdf5a22f538caace33b7edd962b5ede4ad20032
https://github.com/llvm/llvm-project/commit/abdf5a22f538caace33b7edd962b5ede4ad20032
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/Interfaces/CIROpInterfaces.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/Sema/DeclSpec.h
M clang/lib/Basic/DiagnosticIDs.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenCall.h
M clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
M clang/lib/Driver/ToolChains/HIPSPV.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
A clang/test/CIR/CodeGen/builtin_bit.cpp
M clang/test/CIR/CodeGen/builtin_call.cpp
M clang/test/CIR/CodeGen/builtin_printf.cpp
M clang/test/CIR/CodeGen/call.cpp
M clang/test/CIR/CodeGen/complex.cpp
A clang/test/CIR/CodeGen/non-type-template-param.cpp
M clang/test/SemaObjCXX/arc-0x.mm
M clang/tools/clang-installapi/ClangInstallAPI.cpp
M clang/tools/clang-installapi/Options.cpp
M flang/CMakeLists.txt
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/set/TestDataFormatterGenericSet.py
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/vector/Makefile
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/vector/TestDataFormatterStdVector.py
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/vector/main.cpp
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/vector/Makefile
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/vector/TestDataFormatterLibcxxVector.py
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/vector/main.cpp
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libstdcpp/vector/Makefile
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libstdcpp/vector/TestDataFormatterStdVector.py
R lldb/test/API/functionalities/data-formatter/data-formatter-stl/libstdcpp/vector/main.cpp
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/lib/Analysis/HashRecognize.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/DebugInfo/PDB/Native/GSIStreamBuilder.cpp
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Analysis/HashRecognize/cyclic-redundancy-check.ll
A llvm/test/CodeGen/AArch64/sve-merging-unary.ll
M llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll
A llvm/test/CodeGen/AMDGPU/test_isel_single_lane.ll
M llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll
M llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
M llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
M llvm/test/CodeGen/PowerPC/xxeval-vselect-x-or.ll
M llvm/test/CodeGen/PowerPC/xxeval-vselect-x-xor.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-fixed-order-recurrence.ll
M llvm/unittests/CodeGen/SelectionDAGAddressAnalysisTest.cpp
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
M mlir/examples/toy/Ch6/mlir/LowerToLLVM.cpp
M mlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp
M mlir/lib/IR/AffineMap.cpp
M mlir/lib/IR/AsmPrinter.cpp
M mlir/lib/IR/Block.cpp
M mlir/lib/IR/Builders.cpp
M mlir/lib/IR/BuiltinAttributes.cpp
M mlir/lib/IR/BuiltinDialect.cpp
M mlir/lib/IR/BuiltinTypeInterfaces.cpp
M mlir/lib/IR/BuiltinTypes.cpp
M mlir/lib/IR/Dialect.cpp
M mlir/lib/IR/Dominance.cpp
M mlir/lib/IR/MLIRContext.cpp
M mlir/lib/IR/Operation.cpp
M mlir/lib/IR/OperationSupport.cpp
M mlir/lib/IR/TypeRange.cpp
M mlir/lib/IR/Unit.cpp
M openmp/runtime/tools/message-converter.py
Log Message:
-----------
Merge branch 'main' into users/kparzysz/spr/d02-clang-parser
Compare: https://github.com/llvm/llvm-project/compare/49ef39329030...abdf5a22f538
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