[all-commits] [llvm/llvm-project] 032966: [RISCV] Added the MIPS prefetch extensions for MIP...

[UmeshKalappa via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 032966ff5679804e826b76beab6306e277ef8d33
      https://github.com/llvm/llvm-project/commit/032966ff5679804e826b76beab6306e277ef8d33
  Author: UmeshKalappa <103930015+ukalappa-mips at users.noreply.github.com>
  Date:   2025-07-03 (Thu, 03 Jul 2025)

  Changed paths:
    M clang/test/Driver/print-supported-extensions-riscv.c
    M clang/test/Driver/riscv-cpus.c
    M llvm/docs/RISCVUsage.rst
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td
    M llvm/lib/Target/RISCV/RISCVProcessors.td
    M llvm/test/CodeGen/RISCV/features-info.ll
    A llvm/test/CodeGen/RISCV/xmips-cbop.ll
    M llvm/test/MC/RISCV/xmips-invalid.s
    M llvm/test/MC/RISCV/xmips-valid.s
    M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

  Log Message:
  -----------
  [RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (#145647)

the extension enabled with xmipscbop.

Please refer "MIPS RV64 P8700/P8700-F Multiprocessing System
Programmer’s Guide" for more info on the extension at
https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf



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