[all-commits] [llvm/llvm-project] 6ff3b4: [TableGen] More generically handle tied source ope...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6ff3b43700175dbff8f2e4b63c6f27835418e20c
      https://github.com/llvm/llvm-project/commit/6ff3b43700175dbff8f2e4b63c6f27835418e20c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-07-02 (Wed, 02 Jul 2025)

  Changed paths:
    M llvm/utils/TableGen/CompressInstEmitter.cpp

  Log Message:
  -----------
  [TableGen] More generically handle tied source operands in CompressInstEmitter. (#146183)

Move the creation of OperandMap from createDagOperandMapping to the loop
in addDagOperandMapping. Expand it to store the DAG operand number and
the MI operand number which will be different when there are tied
operands.

Rename createDagOperandMapping to checkDagOperandMapping to better
describe the remaining code.

I didn't lift the restriction that a source instruction can only have
one tied operand, but we should be able to if we have a use case.

There's a slight difference in the generate output. We now check that
operand 0 and 2 of QC_MVEQI are equal instead of operand 1 and 2. This
should be equivalent since operand 0 and 1 have a tied constraint.



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