[all-commits] [llvm/llvm-project] 3dc09f: [Xtensa] Implement THREADPTR and DFPAccel Xtensa O...

[Andrei Safronov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3dc09fbf29d5527f38b2c3e1c13aedb73c966e48
      https://github.com/llvm/llvm-project/commit/3dc09fbf29d5527f38b2c3e1c13aedb73c966e48
  Author: Andrei Safronov <andrei.safronov at espressif.com>
  Date:   2025-07-02 (Wed, 02 Jul 2025)

  Changed paths:
    M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaELFObjectWriter.cpp
    M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
    M llvm/lib/Target/Xtensa/XtensaFeatures.td
    M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
    M llvm/lib/Target/Xtensa/XtensaISelLowering.h
    M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
    M llvm/lib/Target/Xtensa/XtensaOperators.td
    M llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
    M llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
    M llvm/lib/Target/Xtensa/XtensaSubtarget.h
    A llvm/test/CodeGen/Xtensa/invalid-tls.ll
    A llvm/test/CodeGen/Xtensa/threadptr.ll
    A llvm/test/MC/Disassembler/Xtensa/dfpaccel.txt
    A llvm/test/MC/Disassembler/Xtensa/threadptr.txt
    A llvm/test/MC/Xtensa/dfpaccel.s
    A llvm/test/MC/Xtensa/threadptr.s

  Log Message:
  -----------
  [Xtensa] Implement THREADPTR and DFPAccel Xtensa Options. (#145543)

Implment base support of the TLS functionality using Xtensa THREADPTR
Option. Implement basic functionality of the DFPAccel Option(registers
support).



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