[all-commits] [llvm/llvm-project] 7cc8fe: [LLVM][AArch64] Relax SVE/SME codegen predicates. ...

[Paul Walker via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7cc8fe2a2cd46800f3a0851f1d51853747ade228
      https://github.com/llvm/llvm-project/commit/7cc8fe2a2cd46800f3a0851f1d51853747ade228
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2025-07-02 (Wed, 02 Jul 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/fp8-sve-cvt-cvtlt.ll
    M llvm/test/CodeGen/AArch64/fp8-sve-cvtn.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-fexpa.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-binary-narrowing-add-sub.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-binary-narrowing-shr.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-complex-dot.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-contiguous-conflict-detection.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-faminmax.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-fp-converts.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-fp-int-binary-logarithm.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-fp-widening-mul-acc.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-int-mul-lane.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-luti.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-non-widening-pairwise-arith.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-polynomial-arithmetic.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-psel.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-revd.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-unary-narrowing.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-uniform-complex-arith.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-while-reversed.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-while.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-widening-complex-int-arith.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-widening-dsp.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-widening-pairwise-arith.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmlsl.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-cntp.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-dots.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-dupq.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-extq.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-fclamp.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-fp-reduce.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-int-reduce.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-loads.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-multivec-loads.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-multivec-stores.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-pmov-to-pred.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-pmov-to-vector.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-predicate-as-counter.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-qcvtn.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-qrshr.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-sclamp.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-stores.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-uclamp.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-while-pn.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-while-pp.ll

  Log Message:
  -----------
  [LLVM][AArch64] Relax SVE/SME codegen predicates. (#145322)

Code generation predicates like HasSVE2_or_SME implemented a strict
divide between streaming and non-streaming which meant some SME
instructions were not available unless a matching SVE feature was
enabled.



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