[all-commits] [llvm/llvm-project] 5035d2: AMDGPU: Implement ds_atomic_async_barrier_arrive_b...

[Changpeng Fang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5035d20dcbcea1edced779148ac69b84d3c97577
      https://github.com/llvm/llvm-project/commit/5035d20dcbcea1edced779148ac69b84d3c97577
  Author: Changpeng Fang <changpeng.fang at amd.com>
  Date:   2025-07-01 (Tue, 01 Jul 2025)

  Changed paths:
    M clang/include/clang/Basic/BuiltinsAMDGPU.def
    A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-async-load-store-lds.cl
    M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
    M llvm/lib/Target/AMDGPU/AMDGPU.td
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    M llvm/lib/Target/AMDGPU/DSInstructions.td
    M llvm/lib/Target/AMDGPU/GCNSubtarget.h
    M llvm/lib/Target/AMDGPU/SIDefines.h
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInstrFormats.td
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.atomic.async.barrier.arrive.b64.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.atomic.barrier.arrive.rtn.b64.ll
    A llvm/test/MC/AMDGPU/gfx1250_asm_ds.s
    A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_ds.txt

  Log Message:
  -----------
  AMDGPU: Implement ds_atomic_async_barrier_arrive_b64/ds_atomic_barrier_arrive_rtn_b64 (#146409)

These two instructions are supported by gfx1250. We define the
instructions and implement the corresponding intrinsic and builtin.

Co-authored-by: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>



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