[all-commits] [llvm/llvm-project] 4a2fa0: [VPlan] Support VPWidenIntOrFpInductionRecipes wit...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4a2fa0847fb07d181ef71798cb8d7f4c34599fbf
      https://github.com/llvm/llvm-project/commit/4a2fa0847fb07d181ef71798cb8d7f4c34599fbf
  Author: Luke Lau <luke at igalia.com>
  Date:   2025-07-01 (Tue, 01 Jul 2025)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
    M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
    M llvm/test/Transforms/LoopVectorize/RISCV/evl-compatible-loops.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-masked-access.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/only-compute-cost-for-vplan-vfs.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cond-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-gather-scatter.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-cast-intrinsics.ll

  Log Message:
  -----------
  [VPlan] Support VPWidenIntOrFpInductionRecipes with EVL tail folding (#144666)

Following on from #118638, this handles widened induction variables with
EVL tail folding by setting the VF operand to be EVL, calculated in the
vector body.

We need to do this for correctness since with EVL tail folding the
number of elements processed in the penultimate iteration may not be VF,
but the runtime EVL, and we need take this into account when updating
the backedge value.

- Because the VF may now not be a live-in we need to move the insertion
point to just after the VFs definition
- We also need to avoid truncating it when it's the same size as the
step type, previously this wasn't a problem for live-ins.
- Also because the VF may be smaller than the IV type, since the EVL is
always i32, we may need to zext it.

On -march=rva23u64 -O3 we get 87.1% more loops vectorized on TSVC, and
42.8% more loops vectorized on SPEC CPU 2017



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