[all-commits] [llvm/llvm-project] cf3d13: [AArch64] Do not generate ld1IndexPost when insert...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cf3d136c225361c9a3d1488cd285c784fd6a2a92
      https://github.com/llvm/llvm-project/commit/cf3d136c225361c9a3d1488cd285c784fd6a2a92
  Author: David Green <david.green at arm.com>
  Date:   2025-06-27 (Fri, 27 Jun 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll

  Log Message:
  -----------
  [AArch64] Do not generate ld1IndexPost when inserting into lane 0 of a zero vector (#145723)

If we are inserting into lane 0 of a zero vector, we can use the ldr
instructions to get the upper-lane zero for free. Do not attempt to make
post-inc operations in that case, which should be less micro-ops
overall.



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