[all-commits] [llvm/llvm-project] 950d28: [RISCV] Add ISel patterns for Qualcomm uC Xqcicm e...

[quic_hchandel via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 950d281eb2d42e53c05537965f714249a8e5084a
      https://github.com/llvm/llvm-project/commit/950d281eb2d42e53c05537965f714249a8e5084a
  Author: quic_hchandel <quic_hchandel at quicinc.com>
  Date:   2025-06-27 (Fri, 27 Jun 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    M llvm/test/CodeGen/RISCV/select-cond.ll
    A llvm/test/CodeGen/RISCV/xqcicm.ll

  Log Message:
  -----------
  [RISCV] Add ISel patterns for Qualcomm uC Xqcicm extension (#145643)

Add codegen patterns for the conditional move instructions in this
extension



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