[all-commits] [llvm/llvm-project] 0f013d: [SelectionDAG] Add DoNotPoisonEltMask to SimplifyD...

Björn Pettersson via All-commits all-commits at lists.llvm.org
Thu Jun 26 07:27:24 PDT 2025 

  Branch: refs/heads/users/bjope/demandedbits_bitcast_2
  Home:   https://github.com/llvm/llvm-project
  Commit: 0f013d398931f25b887d0b293459e994ff5b188e
      https://github.com/llvm/llvm-project/commit/0f013d398931f25b887d0b293459e994ff5b188e
  Author: Bjorn Pettersson <bjorn.a.pettersson at ericsson.com>
  Date:   2025-06-26 (Thu, 26 Jun 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
    M llvm/test/CodeGen/AMDGPU/shift-i128.ll
    M llvm/test/CodeGen/ARM/fpclamptosat_vec.ll
    M llvm/test/CodeGen/Thumb2/mve-fpclamptosat_vec.ll
    M llvm/test/CodeGen/Thumb2/mve-gather-ind8-unscaled.ll
    M llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
    M llvm/test/CodeGen/Thumb2/mve-pred-ext.ll
    M llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
    M llvm/test/CodeGen/Thumb2/mve-scatter-ind8-unscaled.ll
    M llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll
    M llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll
    M llvm/test/CodeGen/X86/avx512-intrinsics-upgrade.ll
    M llvm/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
    M llvm/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll
    M llvm/test/CodeGen/X86/buildvec-widen-dotproduct.ll
    M llvm/test/CodeGen/X86/combine-pmuldq.ll
    M llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
    M llvm/test/CodeGen/X86/gfni-funnel-shifts.ll
    M llvm/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
    M llvm/test/CodeGen/X86/known-never-zero.ll
    M llvm/test/CodeGen/X86/known-signbits-shl.ll
    M llvm/test/CodeGen/X86/known-signbits-vector.ll
    M llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
    M llvm/test/CodeGen/X86/pmulh.ll
    M llvm/test/CodeGen/X86/pr42727.ll
    M llvm/test/CodeGen/X86/rotate-extract-vector.ll
    M llvm/test/CodeGen/X86/shrink_vmul.ll
    M llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
    M llvm/test/CodeGen/X86/sshl_sat_vec.ll
    M llvm/test/CodeGen/X86/urem-seteq-illegal-types.ll
    M llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll
    M llvm/test/CodeGen/X86/ushl_sat_vec.ll
    M llvm/test/CodeGen/X86/vec_smulo.ll
    M llvm/test/CodeGen/X86/vec_umulo.ll
    M llvm/test/CodeGen/X86/vector-fshl-128.ll
    M llvm/test/CodeGen/X86/vector-fshl-256.ll
    M llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
    M llvm/test/CodeGen/X86/vector-fshl-rot-256.ll
    M llvm/test/CodeGen/X86/vector-fshr-128.ll
    M llvm/test/CodeGen/X86/vector-fshr-256.ll
    M llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
    M llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
    M llvm/test/CodeGen/X86/vector-mul.ll
    M llvm/test/CodeGen/X86/vector-rotate-128.ll
    M llvm/test/CodeGen/X86/vector-rotate-256.ll
    M llvm/test/CodeGen/X86/vector-shift-shl-128.ll
    M llvm/test/CodeGen/X86/vector-shift-shl-256.ll
    M llvm/test/CodeGen/X86/vector-shift-shl-sub128.ll
    M llvm/test/CodeGen/X86/vector_splat-const-shift-of-constmasked.ll

  Log Message:
  -----------
  [SelectionDAG] Add DoNotPoisonEltMask to SimplifyDemandedVectorElts

The fix for #138513 resulted in a number of regressions due to
the need to demand elements corresponding to bits used by bitcasts
even if those bits weren't used. Problem was that if we did not
demand those elements the calls to SimplifyDemandedVectorElts
could end up turning those unused elements in to poison, making
the bitcast result poison.

This patch is trying to avoid such regressions by adding a new
element mask ('DoNotPoisonEltMask') to SimplifyDemandedVectorElts
that identify elements that aren't really demanded, but they must
not be made more poisonous during simplifications.


  Commit: e14d538e1ca0d41942bff7a71c1a1abc1faf3151
      https://github.com/llvm/llvm-project/commit/e14d538e1ca0d41942bff7a71c1a1abc1faf3151
  Author: Bjorn Pettersson <bjorn.a.pettersson at ericsson.com>
  Date:   2025-06-26 (Thu, 26 Jun 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86ISelLowering.h
    M llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll
    M llvm/test/CodeGen/X86/bitcast-and-setcc-128.ll
    M llvm/test/CodeGen/X86/bitcast-setcc-128.ll
    M llvm/test/CodeGen/X86/bitcast-vector-bool.ll
    M llvm/test/CodeGen/X86/buildvec-widen-dotproduct.ll
    M llvm/test/CodeGen/X86/combine-pmuldq.ll
    M llvm/test/CodeGen/X86/combine-sdiv.ll
    M llvm/test/CodeGen/X86/combine-sra.ll
    M llvm/test/CodeGen/X86/combine-udiv.ll
    M llvm/test/CodeGen/X86/f16c-intrinsics-fast-isel.ll
    M llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
    M llvm/test/CodeGen/X86/known-pow2.ll
    M llvm/test/CodeGen/X86/masked_store.ll
    M llvm/test/CodeGen/X86/movmsk-cmp.ll
    M llvm/test/CodeGen/X86/mulvi32.ll
    M llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
    M llvm/test/CodeGen/X86/pmul.ll
    M llvm/test/CodeGen/X86/pr35918.ll
    M llvm/test/CodeGen/X86/pr41619.ll
    M llvm/test/CodeGen/X86/pr45563-2.ll
    M llvm/test/CodeGen/X86/pr45833.ll
    M llvm/test/CodeGen/X86/pr77459.ll
    M llvm/test/CodeGen/X86/psubus.ll
    M llvm/test/CodeGen/X86/sadd_sat_vec.ll
    M llvm/test/CodeGen/X86/sat-add.ll
    M llvm/test/CodeGen/X86/sdiv-exact.ll
    M llvm/test/CodeGen/X86/shrink_vmul.ll
    M llvm/test/CodeGen/X86/ssub_sat_vec.ll
    M llvm/test/CodeGen/X86/test-shrink-bug.ll
    M llvm/test/CodeGen/X86/udiv-exact.ll
    M llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll
    M llvm/test/CodeGen/X86/vec_minmax_sint.ll
    M llvm/test/CodeGen/X86/vec_minmax_uint.ll
    M llvm/test/CodeGen/X86/vector-compare-all_of.ll
    M llvm/test/CodeGen/X86/vector-compare-any_of.ll
    M llvm/test/CodeGen/X86/vector-fshl-128.ll
    M llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
    M llvm/test/CodeGen/X86/vector-fshr-128.ll
    M llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
    M llvm/test/CodeGen/X86/vector-mul.ll
    M llvm/test/CodeGen/X86/vector-pcmp.ll
    M llvm/test/CodeGen/X86/vector-reduce-fmaximum.ll
    M llvm/test/CodeGen/X86/vector-reduce-mul.ll
    M llvm/test/CodeGen/X86/vector-reduce-smax.ll
    M llvm/test/CodeGen/X86/vector-reduce-smin.ll
    M llvm/test/CodeGen/X86/vector-reduce-umax.ll
    M llvm/test/CodeGen/X86/vector-reduce-umin.ll
    M llvm/test/CodeGen/X86/vector-rotate-128.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining.ll
    M llvm/test/CodeGen/X86/vector-trunc-packus.ll
    M llvm/test/CodeGen/X86/vector-trunc-ssat.ll
    M llvm/test/CodeGen/X86/vector-trunc-usat.ll
    M llvm/test/CodeGen/X86/vselect.ll

  Log Message:
  -----------
  [SelectionDAG] Add DoNotPoisonEltMask to SimplifyDemandedVectorEltsForTargetNode

Add DoNotPoisonEltMask to SimplifyDemandedVectorEltsForTargetNode
and try to handle it for a number of X86 opcodes. In some situations
we just fallback and assume that the DoNotPoisonEltMask elements
are demanded.

Goal is to reduce amount of regressions after fix of #138513.


  Commit: ec5a8df32db08b278240daa274268f57bd6db6c9
      https://github.com/llvm/llvm-project/commit/ec5a8df32db08b278240daa274268f57bd6db6c9
  Author: Bjorn Pettersson <bjorn.a.pettersson at ericsson.com>
  Date:   2025-06-26 (Thu, 26 Jun 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v2bf16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v3bf16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v4bf16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v2f16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v3f16.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v4f16.ll
    M llvm/test/CodeGen/Thumb2/mve-vst3.ll
    M llvm/test/CodeGen/X86/avx512fp16-mov.ll
    M llvm/test/CodeGen/X86/combine-pmuldq.ll
    M llvm/test/CodeGen/X86/combine-sra.ll
    M llvm/test/CodeGen/X86/extractelement-load.ll
    M llvm/test/CodeGen/X86/half.ll
    M llvm/test/CodeGen/X86/movmsk-cmp.ll
    M llvm/test/CodeGen/X86/pmulh.ll
    M llvm/test/CodeGen/X86/pr107423.ll
    M llvm/test/CodeGen/X86/psubus.ll
    M llvm/test/CodeGen/X86/sadd_sat_vec.ll
    M llvm/test/CodeGen/X86/sat-add.ll
    M llvm/test/CodeGen/X86/ssub_sat_vec.ll
    M llvm/test/CodeGen/X86/vec_minmax_sint.ll
    M llvm/test/CodeGen/X86/vec_minmax_uint.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
    M llvm/test/CodeGen/X86/vector-reduce-smax.ll
    M llvm/test/CodeGen/X86/vector-reduce-smin.ll
    M llvm/test/CodeGen/X86/vector-reduce-umax.ll
    M llvm/test/CodeGen/X86/vector-reduce-umin.ll
    M llvm/test/CodeGen/X86/vector-trunc-packus.ll
    M llvm/test/CodeGen/X86/vector-trunc-ssat.ll
    M llvm/test/CodeGen/X86/vector-trunc-usat.ll

  Log Message:
  -----------
  [SelectionDAG] Add DoNotPoisonEltMask to SimplifyMultipleUseDemandedBits/VectorElts

Add DoNotPoisonEltMask to SimplifyMultipleUseDemandedBits and
SimplifyMultipleUseDemandedVectorElts.

Goal is to reduce amount of regressions after fix of #138513.


  Commit: 3ce0155e81cdc3ae00eac6e6eb0cda9f086d3995
      https://github.com/llvm/llvm-project/commit/3ce0155e81cdc3ae00eac6e6eb0cda9f086d3995
  Author: Bjorn Pettersson <bjorn.a.pettersson at ericsson.com>
  Date:   2025-06-26 (Thu, 26 Jun 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86ISelLowering.h

  Log Message:
  -----------
  [SelectionDAG] Add DoNotPoisonEltMask to SimplifyMultipleUseDemandedBitsForTargetNode


Compare: https://github.com/llvm/llvm-project/compare/0f013d398931%5E...3ce0155e81cd

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