[all-commits] [llvm/llvm-project] 09a240: [MLIR][ArmSVE] Add an ArmSVE dialect operation map...

[Momchil Velikov via All-commits]

  Branch: refs/heads/users/momchil-velikov/bfmmla-sve
  Home:   https://github.com/llvm/llvm-project
  Commit: 09a240bf67d90dba6d93095bfa6a8ac324d1401d
      https://github.com/llvm/llvm-project/commit/09a240bf67d90dba6d93095bfa6a8ac324d1401d
  Author: Momchil Velikov <momchil.velikov at arm.com>
  Date:   2025-06-26 (Thu, 26 Jun 2025)

  Changed paths:
    M mlir/include/mlir/Dialect/ArmSVE/IR/ArmSVE.td
    M mlir/lib/Dialect/ArmSVE/Transforms/LegalizeForLLVMExport.cpp
    M mlir/test/Dialect/ArmSVE/legalize-for-llvm.mlir
    M mlir/test/Dialect/ArmSVE/roundtrip.mlir
    M mlir/test/Target/LLVMIR/arm-sve.mlir

  Log Message:
  -----------
  [MLIR][ArmSVE] Add an ArmSVE dialect operation mapping to `bfmmla`


  Commit: 690b549719f86feac8ff9c04474cba1b234f27b2
      https://github.com/llvm/llvm-project/commit/690b549719f86feac8ff9c04474cba1b234f27b2
  Author: Momchil Velikov <momchil.velikov at arm.com>
  Date:   2025-06-26 (Thu, 26 Jun 2025)

  Changed paths:
    M mlir/include/mlir/Dialect/ArmSVE/IR/ArmSVE.td
    M mlir/lib/Dialect/ArmSVE/Transforms/LegalizeForLLVMExport.cpp
    M mlir/test/Dialect/ArmSVE/legalize-for-llvm.mlir
    M mlir/test/Dialect/ArmSVE/roundtrip.mlir

  Log Message:
  -----------
  [fixup] Skip the two-stage LLVM IR generation, map the op directly to the LLVM IR intrinsic


  Commit: 9bcd62eb2ae16405c32bd6d5af3e5e9d9d815cf7
      https://github.com/llvm/llvm-project/commit/9bcd62eb2ae16405c32bd6d5af3e5e9d9d815cf7
  Author: Momchil Velikov <momchil.velikov at arm.com>
  Date:   2025-06-26 (Thu, 26 Jun 2025)

  Changed paths:
    M mlir/test/Dialect/ArmSVE/invalid.mlir

  Log Message:
  -----------
  [fixup] Add some tests with invalid operands


Compare: https://github.com/llvm/llvm-project/compare/fcae83d1364a...9bcd62eb2ae1

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