[all-commits] [llvm/llvm-project] ce8f16: [RISCV] Use SelectAddrRegRegScale for Xqcisls inst...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ce8f1600d042726312b80ff7e80b26cd03e99c8f
      https://github.com/llvm/llvm-project/commit/ce8f1600d042726312b80ff7e80b26cd03e99c8f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-06-25 (Wed, 25 Jun 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    M llvm/test/CodeGen/RISCV/xqcisls.ll

  Log Message:
  -----------
  [RISCV] Use SelectAddrRegRegScale for Xqcisls instructions. (#145608)

This reuses code from XTHeadMemIdex. This saves ~500 bytes from the isel
table and provides more flexibility in what patterns can be matched.



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