[all-commits] [llvm/llvm-project] deb346: [RISCV] Add Tied operands in Xqcicm instructions a...
quic_hchandel via All-commits
all-commits at lists.llvm.org
Tue Jun 24 21:55:21 PDT 2025
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: deb3464192647501ee1ba8431ffad6aa4c68ef00
https://github.com/llvm/llvm-project/commit/deb3464192647501ee1ba8431ffad6aa4c68ef00
Author: quic_hchandel <quic_hchandel at quicinc.com>
Date: 2025-06-25 (Wed, 25 Jun 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/test/MC/RISCV/xqcicm-valid.s
M llvm/utils/TableGen/CompressInstEmitter.cpp
Log Message:
-----------
[RISCV] Add Tied operands in Xqcicm instructions and changes to handle a single tied operand in source DAG and instruction (#145538)
Tied Operands change is required for adding codegen patterns for
Qualcomm uC Xqcicm instructions
which will be done in a follow-up PR. This change leads to one of
instructions getting compressed even
when it shouldn't be. This case was not covered in #143660. Added
changes to correctly handle this case.
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