[all-commits] [llvm/llvm-project] e1cd45: [NVPTX] fold movs into loads and stores (#144581)

[Princeton Ferro via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e1cd450c8f7ca1815364b6b0a275be71eea39860
      https://github.com/llvm/llvm-project/commit/e1cd450c8f7ca1815364b6b0a275be71eea39860
  Author: Princeton Ferro <pferro at nvidia.com>
  Date:   2025-06-24 (Tue, 24 Jun 2025)

  Changed paths:
    M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
    M llvm/test/CodeGen/NVPTX/bf16-instructions.ll
    M llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll
    M llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
    M llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
    M llvm/test/CodeGen/NVPTX/fexp2.ll
    M llvm/test/CodeGen/NVPTX/flog2.ll
    M llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
    M llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll
    M llvm/test/CodeGen/NVPTX/fma-relu-instruction-flag.ll
    M llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
    M llvm/test/CodeGen/NVPTX/i8x2-instructions.ll
    M llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
    M llvm/test/CodeGen/NVPTX/ldg-invariant.ll
    M llvm/test/CodeGen/NVPTX/load-store-vectors.ll
    M llvm/test/CodeGen/NVPTX/load-with-non-coherent-cache.ll
    M llvm/test/CodeGen/NVPTX/math-intrins.ll
    M llvm/test/CodeGen/NVPTX/param-load-store.ll
    M llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
    M llvm/test/CodeGen/NVPTX/sext-setcc.ll
    M llvm/test/CodeGen/NVPTX/shift-opt.ll
    M llvm/test/CodeGen/NVPTX/unfold-masked-merge-vector-variablemask.ll
    M llvm/test/CodeGen/NVPTX/vector-loads.ll

  Log Message:
  -----------
  [NVPTX] fold movs into loads and stores (#144581)

Fold movs into loads and stores by increasing the number of return
values or operands. For example:

```
L: v2f16,ch = Load [p]
e0 = extractelt L, 0
e1 = extractelt L, 1
consume(e0, e1)
```

...becomes...

```
L: f16,f16,ch = LoadV2 [p]
consume(L:0, L:1)
```



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