[all-commits] [llvm/llvm-project] f6ab1f: [RISCV] Support LLVM IR intrinsics for XAndesVBFHC...

[Jim Lin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f6ab1f02ec0e6031412ecaab2fb232e4fb22b3d0
      https://github.com/llvm/llvm-project/commit/f6ab1f02ec0e6031412ecaab2fb232e4fb22b3d0
  Author: Jim Lin <jim at andestech.com>
  Date:   2025-06-24 (Tue, 24 Jun 2025)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCVXAndes.td
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
    A llvm/test/CodeGen/RISCV/rvv/xandesvbfhcvt-vfncvt-bf16-s.ll
    A llvm/test/CodeGen/RISCV/rvv/xandesvbfhcvt-vfwcvt-s-bf16.ll

  Log Message:
  -----------
  [RISCV] Support LLVM IR intrinsics for XAndesVBFHCvt (#145321)

This patch adds LLVM IR intrinsic support for XAndesVBFHCvt.

The document for the intrinsics can be found at:
https://github.com/andestech/andes-vector-intrinsic-doc/blob/ast-v5_4_0-release-v5/auto-generated/andes-v5/intrinsic_funcs.adoc#vector-widening-convert-intrinsicsxandesvbfhcvt
https://github.com/andestech/andes-vector-intrinsic-doc/blob/ast-v5_4_0-release-v5/auto-generated/andes-v5/intrinsic_funcs.adoc#vector-narrowing-convert-intrinsicsxandesvbfhcvt

Vector bf16 load/store intrisics is also enabled when +xandesvbfhcvt is
specified. The corresponding LLVM IR intrisic testcase would be added in
a follow-up patches.

The clang part will be added in a later patch.

Co-authored-by: Tony Chuan-Yue Yuan <yuan593 at andestech.com>



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