[all-commits] [llvm/llvm-project] 88b98d: [RISCV] Add ISel pattern for generating QC_BREV32 ...

[Sudharsan Veeravalli via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 88b98d3367f3b1e8741f18789b567b141c8ef87b
      https://github.com/llvm/llvm-project/commit/88b98d3367f3b1e8741f18789b567b141c8ef87b
  Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
  Date:   2025-06-24 (Tue, 24 Jun 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    A llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll
    R llvm/test/CodeGen/RISCV/xqcibm-cto-clo.ll

  Log Message:
  -----------
  [RISCV] Add ISel pattern for generating QC_BREV32 (#145288)

The `QC_BREV32` instruction reverses the bit order of `rs1` and writes
the result to `rd`



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