[all-commits] [llvm/llvm-project] 2f9c97: [RISCV] Add Andes AX45MPV processor definition (#1...

[Jim Lin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2f9c97c030c32c1838d7f102d55921ed4d3442e1
      https://github.com/llvm/llvm-project/commit/2f9c97c030c32c1838d7f102d55921ed4d3442e1
  Author: Jim Lin <jim at andestech.com>
  Date:   2025-06-24 (Tue, 24 Jun 2025)

  Changed paths:
    A clang/test/Driver/print-enabled-extensions/riscv-andes-ax45mpv.c
    M clang/test/Driver/riscv-cpus.c
    M clang/test/Misc/target-invalid-cpu-note/riscv.c
    M llvm/docs/ReleaseNotes.md
    M llvm/lib/Target/RISCV/RISCVProcessors.td

  Log Message:
  -----------
  [RISCV] Add Andes AX45MPV processor definition (#145267)

Andes AX45MPV is 64-bit in-order dual-issue 8-stage pipeline
linux-capable CPU implementing the RV64IMAFDCV ISA extension. That is
developed by Andes Technology https://www.andestech.com, a RISC-V IP
provider.

The overviews for AX45MPV:
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mpv/

Scheduling model for RVV extension will be implemented a follow-up PR.



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