[all-commits] [llvm/llvm-project] f40909: [RISCV] Add SiFive X390 scheduling model (#143938)

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f40909f605fdd7c049d50b6483db9e769fb933c0
      https://github.com/llvm/llvm-project/commit/f40909f605fdd7c049d50b6483db9e769fb933c0
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-06-23 (Mon, 23 Jun 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVProcessors.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    A llvm/test/tools/llvm-mca/RISCV/SiFiveX390/div-fdiv.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveX390/fractional-lmul-data.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveX390/reductions.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveX390/strided-load-store.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveX390/strided-load-x0.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveX390/vector-fp.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveX390/vector-integer-arithmetic.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveX390/vgather-vcompress.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveX390/vle-vse.s

  Log Message:
  -----------
  [RISCV] Add SiFive X390 scheduling model (#143938)

This patch adds the scheduling model for sifive-x390. X390 is a dual
issue in-order CPU. It has two scalar and two vector pipes, with
VLEN=1024 and DLEN=512.

Co-authored-by: Michael Maitland <michaeltmaitland at gmail.com>



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