[all-commits] [llvm/llvm-project] 7a3356: [RISCV] Factor out common SiFive7 scheduling model...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7a33569510535f0b917a2e50f644bf57490aee24
      https://github.com/llvm/llvm-project/commit/7a33569510535f0b917a2e50f644bf57490aee24
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-06-23 (Mon, 23 Jun 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/test/tools/llvm-mca/RISCV/SiFive7/div-fdiv.s
    M llvm/test/tools/llvm-mca/RISCV/SiFive7/gpr-bypass-c.s
    M llvm/test/tools/llvm-mca/RISCV/SiFive7/gpr-bypass.s
    M llvm/test/tools/llvm-mca/RISCV/SiFive7/instruction-tables-tests.s
    M llvm/test/tools/llvm-mca/RISCV/SiFive7/jump.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/different-lmul-instruments.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/different-sew-instruments.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/disable-im.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/fractional-lmul-data.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/lmul-instrument-at-start.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/lmul-instrument-in-middle.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/lmul-instrument-in-region.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/lmul-instrument-straddles-region.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/multiple-same-lmul-instruments.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/multiple-same-sew-instruments.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/needs-sew-but-only-lmul.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/no-vsetvli-to-start.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/reductions.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/sew-instrument-at-start.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/sew-instrument-in-middle.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/sew-instrument-in-region.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/sew-instrument-straddles-region.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/strided-load-store.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/strided-load-x0.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/vector-integer-arithmetic.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/vle-vse.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/vsetivli-lmul-instrument.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/vsetivli-lmul-sew-instrument.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/vsetvli-lmul-instrument.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/vsetvli-lmul-sew-instrument.s

  Log Message:
  -----------
  [RISCV] Factor out common SiFive7 scheduling model into an abstraction layer (#144442)

In preparation for sifive-x390's scheduling model, which shares quite a
lot with the existing SiFive7 scheduling model, this patch factors out
some of the components that will share between them. Notably:

- Processor resource definitions (i.e. pipes) are factored out into a
multiclass, `SiFive7ProcResources`. Similarly, WriteRes entries and
bypass entries (i.e. ReadAdvance) are also factored out into their own
multiclass: `SiFive7WriteResBase` and `SiFive7ReadAdvance`,
respectively.
- The aforementioned three components, `SiFive7ProcResources`,
`SiFive7WriteResBase`, and `SiFive7ReadAdvance` are encapsulated into a
bigger multiclass, `SiFive7SchedResources`, which configures these
components with parameters passed from the template arguments. An
example configure value would be the VLEN.
- SiFive7's SchedMachineModel carries not only standard fields like
issue width, but also the concrete config values corresponding to the
processor. For instance, the existing SiFive7 models has VLEN=512, while
X390 has VLEN=1024.
- In the final phase, we "bind" SchedMachineModel from each processor to
a SiFive7SchedResources that is instantiated from that
SchedMachineModel's config values.

Co-authored-by: Michael Maitland <michaeltmaitland at gmail.com>



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