[all-commits] [llvm/llvm-project] 6a0593: [AMDGPU] Extend wave reduce intrinsics for i32 typ...

[Aaditya via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6a0593b0a3831a14fd0e01ffca992f6ee6d86c64
      https://github.com/llvm/llvm-project/commit/6a0593b0a3831a14fd0e01ffca992f6ee6d86c64
  Author: Aaditya <115080342+easyonaadit at users.noreply.github.com>
  Date:   2025-06-23 (Mon, 23 Jun 2025)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
    R llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.reduce.umax.mir
    R llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.reduce.umin.mir

  Log Message:
  -----------
  [AMDGPU] Extend wave reduce intrinsics for i32 type (#126469)

Currently, wave reduction intrinsics are supported for `umin` and `umax`
operations for `i32` type only.
This patch extends support for the following operations: 
`add`, `sub`, `min`, `max`, `and`, `or`, `xor` for `i32` type.

---------

Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>



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