[all-commits] [llvm/llvm-project] b7d0c9: [SelectionDAG][RISCV] Treat zext nneg as sext in P...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b7d0c9b9d8e2b5c5d6677e368e3cdaf438df294e
      https://github.com/llvm/llvm-project/commit/b7d0c9b9d8e2b5c5d6677e368e3cdaf438df294e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-06-21 (Sat, 21 Jun 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/test/CodeGen/RISCV/shifts.ll

  Log Message:
  -----------
  [SelectionDAG][RISCV] Treat zext nneg as sext in PromoteIntOp_ZERO_EXTEND if the promoted input is sign extended. (#145120)

If the zext has the nneg flag and we can prove the promoted input
is sign extended, we can avoid generating an AND that we might not
be able to remove. RISC-V emits a lot of sext_inreg operations during
i32->i64 promotion that makes this likely.

I've restricted this to the case where the promoted type is the same
as the result type so we don't need to create an additional extend.

I've also restricted it to cases where the target has stated a
preference for sext like i32->i64 on RV64. This is largely to avoid
wasting time in computeNumSignBits until we have a test case that
benefits.



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