[all-commits] [llvm/llvm-project] 6c8c81: [libc] Fix feature check for riscv (#145169)

[Mikhail R. Gadelha via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6c8c816b175b3b14f47f35619cade4eced1586a2
      https://github.com/llvm/llvm-project/commit/6c8c816b175b3b14f47f35619cade4eced1586a2
  Author: Mikhail R. Gadelha <mikhail at igalia.com>
  Date:   2025-06-21 (Sat, 21 Jun 2025)

  Changed paths:
    M libc/src/__support/macros/properties/cpu_features.h

  Log Message:
  -----------
  [libc] Fix feature check for riscv (#145169)

This PR fixes the feature detection for RISC-V floating-point support in
LLVM's libc implementation.

The `__riscv_flen` macro represents the floating-point register width in
bits (32, 64, or 128). Since Extension D is specifically documented as
implying F, we can use simple >= comparisons to detect them.

For half-precision support, the implementation checks for the Zfhmin
extension as RVA22 and RVA23 profiles only require Zfhmin rather than
the full Zfh extension. Zfh also implies Zfhmin, so checking for Zfhmin
should cover all cases.



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