[all-commits] [llvm/llvm-project] 1fec09: [AArch64][GlobalISel] Allow selecting FPR index lo...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1fec092fd74abc6fa7399da5bcf165d6249883f5
      https://github.com/llvm/llvm-project/commit/1fec092fd74abc6fa7399da5bcf165d6249883f5
  Author: David Green <david.green at arm.com>
  Date:   2025-06-21 (Sat, 21 Jun 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    A llvm/test/CodeGen/AArch64/GlobalISel/select-fp-index-load.mir
    M llvm/test/CodeGen/AArch64/arm64-indexed-memory.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Allow selecting FPR index loads. (#143835)

We can, through legalization of certain operations, end up generating
G_INDEXED_LOAD into FPR registers that require entensions. SExt and ZExt
will always opt for GPR, but anyext/noext can curently be set to FPR
registers in regbankselect. As writing a subregister will set higher
bits in the same register to 0, we can successfully handle zext and
anyext on FPR registers, which is what this patch attempts to add.



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