[all-commits] [llvm/llvm-project] e14f32: [RISCV] Pre-test for #144461
Fangrui Song via All-commits
all-commits at lists.llvm.org
Fri Jun 20 20:13:30 PDT 2025
Branch: refs/heads/users/MaskRay/spr/move-relocation-specifier-constants-to-aarch64
Home: https://github.com/llvm/llvm-project
Commit: e14f327d8094e02134efa98625acaf6fd43fee08
https://github.com/llvm/llvm-project/commit/e14f327d8094e02134efa98625acaf6fd43fee08
Author: Liao Chunyu <chunyu at iscas.ac.cn>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
Log Message:
-----------
[RISCV] Pre-test for #144461
Commit: af49a650e172d56d684581b66afa9ab0368ec8f9
https://github.com/llvm/llvm-project/commit/af49a650e172d56d684581b66afa9ab0368ec8f9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/test/CodeGen/PowerPC/f128-arith.ll
Log Message:
-----------
PowerPC: Add baseline tests for more f128 libcall handling (#144381)
Some of these incorrectly call the l suffixed version of libm
functions and others assert.
Commit: 7b9d10d2e6410029fd0750b2e0566432dbf03dc7
https://github.com/llvm/llvm-project/commit/7b9d10d2e6410029fd0750b2e0566432dbf03dc7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/test/CodeGen/PowerPC/f128-arith.ll
Log Message:
-----------
PowerPC: Fix using long double libm functions for f128 intrinsics (#144382)
This wasn't setting the correct libcall names, which default to the
l suffixed libm names.
Commit: ad9e591fd53f2cf91a2744973b59669d873658af
https://github.com/llvm/llvm-project/commit/ad9e591fd53f2cf91a2744973b59669d873658af
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
Log Message:
-----------
[SelectionDAG][RISCV] Fold (add (vscale * C0), (vscale * C1)) to (vscale * (C0 + C1)) in getNode. (#144565)
We already have shl/mul vscale related folds in getNode.
This is an alternative to the DAGCombine proposed in #144507.
Commit: 74687180dde07312521db09c6f6454fe9d1e5662
https://github.com/llvm/llvm-project/commit/74687180dde07312521db09c6f6454fe9d1e5662
Author: Kirill Chibisov <contact at kchibisov.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/EmitC/IR/CMakeLists.txt
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.h
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
A mlir/include/mlir/Dialect/EmitC/IR/EmitCInterfaces.h
A mlir/include/mlir/Dialect/EmitC/IR/EmitCInterfaces.td
R mlir/include/mlir/Dialect/EmitC/IR/EmitCTraits.h
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
M mlir/lib/Dialect/EmitC/Transforms/FormExpressions.cpp
M mlir/lib/Dialect/EmitC/Transforms/Transforms.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
Log Message:
-----------
[mlir][emitc] Make CExpression trait into interface (#142771)
By defining `CExpressionInterface`, we move the side effect detection
logic from `emitc.expression` into the individual operations
implementing the interface allowing operations to gradually tune the
side effect.
It also allows checking for side effects each operation individually.
Commit: 10f29a607205c0c17ee9249a66feb63f0fdae182
https://github.com/llvm/llvm-project/commit/10f29a607205c0c17ee9249a66feb63f0fdae182
Author: Kunqiu Chen <camsyn at foxmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M compiler-rt/lib/msan/msan_interceptors.cpp
Log Message:
-----------
[MSan] Fix wrong unpoison size in SignalAction (#144071)
MSan should unpoison the parameters of extended signal handlers.
However, MSan unpoisoned the second parameter with the wrong size
`sizeof(__sanitizer_sigaction)`, inconsistent with its real type
`siginfo_t`.
This commit fixes this issue by correcting the size to
`sizeof(__sanitizer_siginfo)`.
Commit: 4d71f20b287e398f10bbff55d52bec9683ef89d2
https://github.com/llvm/llvm-project/commit/4d71f20b287e398f10bbff55d52bec9683ef89d2
Author: Robert Imschweiler <robert.imschweiler at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
Log Message:
-----------
[GlobalISel] prevent G_UNMERGE_VALUES for vectors with different elements (#133335)
This commit prevents building a G_UNMERGE_VALUES instruction with
different source and destination vector elements in
`LegalizationArtifactCombiner::ArtifactValueFinder::tryCombineMergeLike()`,
e.g.:
`%1:_(<2 x s8>), %2:_(<2 x s8>) = G_UNMERGE_VALUES %0:_(<2 x s16>)`
This LLVM defect was identified via the AMD Fuzzing project.
Commit: 896e187a6e923b8441428f9db63c412d989fc51d
https://github.com/llvm/llvm-project/commit/896e187a6e923b8441428f9db63c412d989fc51d
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineAndMaskToShift - pull out repeated SDLoc(). NFC.
Commit: dac94f28e696e8234ec69bbed549533ea6b00227
https://github.com/llvm/llvm-project/commit/dac94f28e696e8234ec69bbed549533ea6b00227
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineAndNotOrIntoAndNotAnd - pull out repeated SDLoc(). NFC.
Commit: 0875bee2b10185eca40aea3b3f49eb8462522eda
https://github.com/llvm/llvm-project/commit/0875bee2b10185eca40aea3b3f49eb8462522eda
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineAndNotIntoANDNP - pull out repeated SDLoc(). NFC.
Commit: 44b715293fcad79ef4a54474627ac574a759fa5a
https://github.com/llvm/llvm-project/commit/44b715293fcad79ef4a54474627ac574a759fa5a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
A llvm/test/Transforms/PhaseOrdering/X86/fmaddsub.ll
Log Message:
-----------
[PhaseOrdering][X86] Copy FMUL+ADDSUB/FMADDSUB build vector patterns from codegen tests
As detailed on #144489 - confirm the vectorisation of scalar FMUL+ADDSUB/FMADDSUB on various targets
Commit: 45ea46c44636094e9fcdbbeabfd11f9d0fad5e38
https://github.com/llvm/llvm-project/commit/45ea46c44636094e9fcdbbeabfd11f9d0fad5e38
Author: Garvit Gupta <quic_garvgupt at quicinc.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/docs/Toolchain.rst
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/lib/Driver/ToolChains/BareMetal.cpp
M clang/lib/Driver/ToolChains/BareMetal.h
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/include/c++/8.2.1/.keep
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/lib/.keep
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/lib/crt0.o
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/bin/aarch64-none-elf-ld
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/crtbegin.o
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/crtend.o
A clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crt0.o
A clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crtbegin.o
A clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crtend.o
A clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/bin/aarch64-none-elf-ld
A clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/include/c++/8.2.1/.keep
A clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/lib/.keep
A clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/lib/crt0.o
A clang/test/Driver/Inputs/basic_arm_gcc_tree/bin/armv6m-none-eabi-ld
A clang/test/Driver/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/crtbegin.o
A clang/test/Driver/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/crtend.o
A clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crt0.o
A clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crtbegin.o
A clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crtend.o
A clang/test/Driver/Inputs/basic_arm_nogcc_tree/bin/armv6m-none-eabi-ld
A clang/test/Driver/aarch64-gnutools.c
A clang/test/Driver/aarch64-toolchain-extra.c
A clang/test/Driver/aarch64-toolchain.c
A clang/test/Driver/arm-gnutools.c
A clang/test/Driver/arm-toolchain-extra.c
A clang/test/Driver/arm-toolchain.c
M clang/test/Driver/baremetal.cpp
A clang/test/Driver/check-no-multlib-warning.c
Log Message:
-----------
Reland [Driver] Add support for GCC installation detection in Baremetal toolchain (#144640)
This patch introduces enhancements to the Baremetal toolchain to support
GCC toolchain detection.
- If the --gcc-install-dir or --gcc-toolchain options are provided and
point to valid paths, the sysroot is derived from those locations.
- If not, the logic falls back to the existing sysroot inference
mechanism already present in the Baremetal toolchain.
- Support for adding include paths for the libstdc++ library has also
been added.
Additionally, the restriction to always use the integrated assembler has
been removed. With a valid GCC installation, the GNU assembler can now
be used as well.
This patch currently updates and adds tests for the ARM target only.
RISC-V-specific tests will be introduced in a later patch, once the
RISCVToolChain is fully merged into the Baremetal toolchain. At this
stage, there is no way to test the RISC-V target within this PR.
RFC:
https://discourse.llvm.org/t/merging-riscvtoolchain-and-baremetal-toolchains/75524
Commit: e07b1b26c38ba48af247b370a29eeb9879cefc97
https://github.com/llvm/llvm-project/commit/e07b1b26c38ba48af247b370a29eeb9879cefc97
Author: Rajveer Singh Bharadwaj <rajveer.developer at icloud.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
Log Message:
-----------
[DAG] Implement SDPatternMatch `m_Abs()` matcher (#144512)
Commit: a38932ac3c0a16226e3dde7f1532f117959c58df
https://github.com/llvm/llvm-project/commit/a38932ac3c0a16226e3dde7f1532f117959c58df
Author: Robert Imschweiler <robert.imschweiler at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
Log Message:
-----------
Revert "[GlobalISel] prevent G_UNMERGE_VALUES for vectors with different elements" (#144650)
Reverts llvm/llvm-project#133335
Commit: 49df87e71b73b230ecb21335dcb5f5390eebdab3
https://github.com/llvm/llvm-project/commit/49df87e71b73b230ecb21335dcb5f5390eebdab3
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M libc/src/__support/FPUtil/dyadic_float.h
Log Message:
-----------
[libc][printf] Fix out-of-range shift in float320 printf (#144542)
If you enable `LIBC_CONF_PRINTF_FLOAT_TO_STR_USE_FLOAT320` and use a
`%f` style printf format directive to print a nonzero number too small
to show up in the output digits, e.g. `printf("%.2f", 0.001)`, then the
output would be intermittently incorrect, because
`DyadicFloat::as_mantissa_type_rounded` would try to shift the 320-bit
mantissa right by more than 320 bits, invoking the 'undefined behavior'
clause commented in the `shift()` function in `big_int.h`.
There were already tests in the libc test suite exercising this case,
e.g. the subnormal tests in `LlvmLibcSPrintfTest.FloatDecimalConv` use
`%f` at the default precision of 6 decimal places on tiny numbers such
as 2^-1027. But because the behavior is undefined, they don't visibly
fail all the time, and in all previous test runs we'd tried with
USE_FLOAT320, they had got lucky.
The fix is simply to detect an out-of-range right shift before doing it,
and instead just set the output value to zero.
Commit: ba40a7bc2e65be86ac23c9cf6038ac085dda77eb
https://github.com/llvm/llvm-project/commit/ba40a7bc2e65be86ac23c9cf6038ac085dda77eb
Author: Mel Chen <mel.chen at sifive.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/first-order-recurrence-scalable-vf1.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-scalable-vf1.ll
Log Message:
-----------
[LoopVectorize] Vectorize fixed-order recurrence with vscale x 1. (#142772)
When the fixed-order recurrence phi is live-out from the loop, the
vectorizer uses VPInstruction::ExtractPenultimateElement to extract the
penultimate element from the recurrence vector. However, this is not
feasible when the VF is vscale x 1, since vscale could be 1, making the
vector contain only one element.
This patch changes the behavior for vscale x 1 by extracting the last
element from the vector produced by splicing the recurrence phi and the
previous value. This ensures we can still determine the correct live-out
value of the recurrence phi.
Commit: ca29c632f06fc0e02ebbbb9fbdc73e3abd6b096b
https://github.com/llvm/llvm-project/commit/ca29c632f06fc0e02ebbbb9fbdc73e3abd6b096b
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
A llvm/test/CodeGen/RISCV/icmp-non-byte-sized.ll
M llvm/test/CodeGen/RISCV/memcmp-optsize.ll
M llvm/test/CodeGen/RISCV/memcmp.ll
Log Message:
-----------
[RISCV] Support non-power-of-2 types when expanding memcmp
We can convert non-power-of-2 types into extended value types
and then they will be widen.
Reviewers: lukel97
Reviewed By: lukel97
Pull Request: https://github.com/llvm/llvm-project/pull/114971
Commit: 59d6fbb8ffe03ceecfcc07ebe22e256c97ef70dd
https://github.com/llvm/llvm-project/commit/59d6fbb8ffe03ceecfcc07ebe22e256c97ef70dd
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M flang/lib/Optimizer/Builder/FIRBuilder.cpp
A flang/test/HLFIR/fir-local-alloca-block.fir
Log Message:
-----------
[flang][fir] Provide allocation block for `fir.local` when required (#144521)
Extends `fir::FirOpBuilder::getAllocaBlock()` to support `fir.local`.
This allows us to retrieve an allocation block when needed for
`fir.local`.
Commit: 255b55c602f73964262893859a543a115b278e21
https://github.com/llvm/llvm-project/commit/255b55c602f73964262893859a543a115b278e21
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
Log Message:
-----------
[GlobalOpt] Use cast instead of dyn_cast. NFC (#144634)
The dyn_cast was not checked for null, and the cast is guaranteed to
succeed by an earlier check.
Commit: 7ea7ccd24d603ceec6eb5194d98911e6ab7c0717
https://github.com/llvm/llvm-project/commit/7ea7ccd24d603ceec6eb5194d98911e6ab7c0717
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
M llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
M llvm/test/CodeGen/PowerPC/aix-cc-byval-mir.ll
M llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-mir.ll
M llvm/test/CodeGen/PowerPC/aix-vec-arg-spills.ll
M llvm/test/CodeGen/PowerPC/aix-vector-vararg-caller.ll
M llvm/test/CodeGen/PowerPC/aix-vector-vararg-fixed-caller.ll
Log Message:
-----------
[PowerPC][AIX] Specify pointer info and alignment for stack store (#144526)
When lowering call arguments to stack, specify a stack MPI, as well as
the stack alignment, instead of using the defaults (which would be an
unknown location with ABI alignment).
I believe the asm diffs are just changes in scheduling.
Commit: c16dc63b44ae039f2ac123a8ffbc90031767d00b
https://github.com/llvm/llvm-project/commit/c16dc63b44ae039f2ac123a8ffbc90031767d00b
Author: Mikael Holmen <mikael.holmen at ericsson.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
Log Message:
-----------
[OMPIRBuilder] Fix gcc -Wparentheses warning [NFC]
Without this gcc warned like
/repo/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp:7559:68: warning: suggest parentheses around '&&' within '||' [-Wparentheses]
7559 | NumStaleCIArgs == (OffloadingArraysToPrivatize.size() + 2) &&
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~
7560 | "Wrong number of arguments for StaleCI when shareds are present");
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Commit: 669627d0c77ed8408358bc8c5973255fe28a36ea
https://github.com/llvm/llvm-project/commit/669627d0c77ed8408358bc8c5973255fe28a36ea
Author: Philipp Jung <philippjung2010 at live.de>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang-tools-extra/clang-tidy/cppcoreguidelines/CMakeLists.txt
M clang-tools-extra/clang-tidy/cppcoreguidelines/CppCoreGuidelinesTidyModule.cpp
A clang-tools-extra/clang-tidy/cppcoreguidelines/UseEnumClassCheck.cpp
A clang-tools-extra/clang-tidy/cppcoreguidelines/UseEnumClassCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines/use-enum-class.rst
M clang-tools-extra/docs/clang-tidy/checks/list.rst
A clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/use-enum-class.cpp
Log Message:
-----------
Add check 'cppcoreguidelines-use-enum-class' (#138282)
Warn on non-class enum definitions as suggested by the Core Guidelines:
https://isocpp.github.io/CppCoreGuidelines/CppCoreGuidelines#Renum-class
Commit: 43e1a5a411d972fe06a1afb86ffd5ba21fd2a376
https://github.com/llvm/llvm-project/commit/43e1a5a411d972fe06a1afb86ffd5ba21fd2a376
Author: Frank Schlimbach <frank.schlimbach at intel.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.h
M mlir/include/mlir/Dialect/Mesh/Transforms/Passes.h
M mlir/include/mlir/Dialect/Mesh/Transforms/Passes.td
M mlir/lib/Dialect/Mesh/IR/MeshOps.cpp
M mlir/lib/Dialect/Mesh/Transforms/ShardingPropagation.cpp
A mlir/test/Dialect/Mesh/backward-sharding-propagation.mlir
A mlir/test/Dialect/Mesh/forward-backward-sharding-propagation.mlir
A mlir/test/Dialect/Mesh/forward-sharding-propagation.mlir
Log Message:
-----------
[mlir][mesh] adding option for traversal order in sharding propagation (#144079)
The traversal order in sharding propagation was hard-coded. This PR
provides options to the pass to select a suitable order
- forward-only
- backward-only
- forward-backward
- backward-forward
Default is the previous behavior (backward-forward).
Commit: 355725a25e6be38d7a97cab9e206d2a16a1bd849
https://github.com/llvm/llvm-project/commit/355725a25e6be38d7a97cab9e206d2a16a1bd849
Author: Kunqiu Chen <camsyn at foxmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp
M llvm/test/Instrumentation/ThreadSanitizer/atomic-non-integer.ll
Log Message:
-----------
[TSan] Fix missing inst cleanup (#144067)
Commit 44e875ad5b2ce26826dd53f9e7d1a71436c86212 introduced a change that
replaces `ReplaceInstWithInst` with `Instruction::replaceAllUsesWith`,
without subsequent instruction cleanup.
This results in TSan leaving behind useless `load atomic` instructions
after 'replacing' them.
This commit adds cleanup back, consistent with the context.
Commit: 8e157fdbb7b4af9f67b139a9f05feaa9b338d3f5
https://github.com/llvm/llvm-project/commit/8e157fdbb7b4af9f67b139a9f05feaa9b338d3f5
Author: Sirui Mu <msrlancern at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
M clang/test/CIR/CodeGen/builtin_call.cpp
Log Message:
-----------
[CIR] Add support for __builtin_assume (#144376)
This patch adds support for the `__builtin_assume` builtin function.
Commit: fe42d34274cac79794637bf2f69f85537dde8b74
https://github.com/llvm/llvm-project/commit/fe42d34274cac79794637bf2f69f85537dde8b74
Author: Ying Yi <ying.yi at sony.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/lib/Headers/bmiintrin.h
M clang/lib/Headers/immintrin.h
M clang/lib/Headers/keylockerintrin.h
M clang/lib/Headers/x86gprintrin.h
M clang/lib/Headers/x86intrin.h
Log Message:
-----------
[clang][headers]Remove unnecessary guard of !defined(__SCE__). (#144522)
Sony PlayStation now supports C++20, and we wish to change the default
C++ mode to C++20 sometime in the future. As such, the !defined(__SCE__)
guards are redundant and we want to remove them. This in turn makes the
entire guard lines redundant (always true), so this patch removes them
entirely.
Commit: 58c4fa96cb111ea8d399296838f4cb6a294115ca
https://github.com/llvm/llvm-project/commit/58c4fa96cb111ea8d399296838f4cb6a294115ca
Author: Karlo Basioli <k.basioli at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Fix bazel build for #142771 (#144659)
Commit: 6fcdde2a4eb9eaf34511ac3a35075be329fe1fae
https://github.com/llvm/llvm-project/commit/6fcdde2a4eb9eaf34511ac3a35075be329fe1fae
Author: Lucas Duarte Prates <lucas.prates at arm.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M runtimes/CMakeLists.txt
Log Message:
-----------
[runtimes] Allow use of external llvm-lit on standalone builds (#144347)
When creating a standalone build of the runtimes sub-project, the
current CMake implementation looks for a lit executable that might
potentially exist in the build tree and unconditionally overrides the
value of `LLVM_EXTERNAL_LIT`. Due to this, any value passed via
`-DLLVM_EXTERNAL_LIT` when configuring the CMake project is ignored.
This change adds the `ALLOW_EXTERNAL` argument to the
`get_llvm_lit_path` call in the runtimes' CMakeLists.txt, allowing any
value previously set to be considered.
Commit: 757a0e6d3b6130a984960ee413a3c8a6f99c7cb5
https://github.com/llvm/llvm-project/commit/757a0e6d3b6130a984960ee413a3c8a6f99c7cb5
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
A llvm/test/CodeGen/SystemZ/fake-use-size.ll
Log Message:
-----------
[SystemZ] Treat FAKE_USE instructions as instructions without a size (#144390)
This patch fixes an error in which `FAKE_USE` instructions would trigger
an assertion in SystemZLongBranch due to them having a size of 0 without
being excepted in the assertion that each instruction, other than a set
of known 0-size instruction types, should have a non-0 size.
`FAKE_USE` instructions are no-op instructions that are emitted into
LLVM by the `-fextend-variable-liveness` clang flag to help preserve the
liveness of source variables in optimized code, and therefore they
should be understood as being valid size 0 instructions.
Commit: bb00fd087a3c3e02fb812e41218ad0a85d9f0fe1
https://github.com/llvm/llvm-project/commit/bb00fd087a3c3e02fb812e41218ad0a85d9f0fe1
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/cppcoreguidelines/BUILD.gn
Log Message:
-----------
[gn build] Port 669627d0c77e
Commit: cd8248f3e856a37cc1addcb74475b4d37dc8aa42
https://github.com/llvm/llvm-project/commit/cd8248f3e856a37cc1addcb74475b4d37dc8aa42
Author: Scott Constable <scott.d.constable at intel.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/X86/X86AsmPrinter.cpp
M llvm/test/CodeGen/X86/kcfi-arity.ll
Log Message:
-----------
Fixed a bug in `-fsanitize-kcfi-arity` (#142867)
Compiling with `fsanitize-kcfi-arity` can crash the compiler if a
function has more than 6 arguments, including floating-point arguments
passed in XMM registers. This patch fixes the feature by only counter
integer and stack arguments toward kCFI arity. For example, the compiler
crashed when it attempted to generate kCFI arity information for this
function:
https://github.com/torvalds/linux/blob/16b70698aa3ae7888826d0c84567c72241cf6713/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h#L680
As noted in a comment, floating-point registers are not relevant to
enforcing kCFI at this time.
Commit: dac0820b277835b7506a9c0d1dc5e077597f6742
https://github.com/llvm/llvm-project/commit/dac0820b277835b7506a9c0d1dc5e077597f6742
Author: Bjorn Pettersson <bjorn.a.pettersson at ericsson.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/test/CodeGen/Thumb2/mve-shuffle.ll
M llvm/test/CodeGen/Thumb2/mve-vld3.ll
M llvm/test/CodeGen/Thumb2/schedm7-hazard.ll
Log Message:
-----------
[Thumb2] Regenerate some test checks. NFC
Commit: 5a9cc93a2058e2c26d766f7be6aee63e928bf825
https://github.com/llvm/llvm-project/commit/5a9cc93a2058e2c26d766f7be6aee63e928bf825
Author: Karlo Basioli <k.basioli at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Fix for bazel build #142079 (#144665)
Commit: a13b7cc00c5f4b9d2636ed7a22c1390cf8033baf
https://github.com/llvm/llvm-project/commit/a13b7cc00c5f4b9d2636ed7a22c1390cf8033baf
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/test/Transforms/LICM/call-hoisting.ll
M llvm/test/Transforms/LICM/funclet.ll
Log Message:
-----------
[LICM] Support hoisting of non-argmemonly readonly calls (#144497)
The code checking whether a readonly call is safe to hoist is
currently limited to only argmemonly calls. However, the actual
implementation does not depend on this in any way. It either
does an MSSA clobber walk on the memory access (which will take
all locations accessed by the call into account), or it will
look at all MemoryDefs in an entirely location-independent manner.
The current restriction dates back to the time when LICM still
supported AST, in which case this code *did* reason about the
individual pointer arguments.
Commit: ee4c2bb68752a6c4b463f3873cde278b8d348628
https://github.com/llvm/llvm-project/commit/ee4c2bb68752a6c4b463f3873cde278b8d348628
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M lldb/test/Shell/SymbolFile/DWARF/x86/explicit-member-function-quals.cpp
Log Message:
-----------
[lldb][test] explicit-member-function-quals.cpp: add -glldb
This will get un-XFAILed but requires `-glldb` in an upcoming patch.
Commit: 561eca44e7639ee8805d0bf65a59b9898d782538
https://github.com/llvm/llvm-project/commit/561eca44e7639ee8805d0bf65a59b9898d782538
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
A llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg-mir.ll
M llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
A llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg-mir.ll
M llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll
Log Message:
-----------
[PowerPC] Split tests into asm and mir parts (NFC)
To allow both to be generated.
Commit: acde20b5605f3a3a8da2217e4526fc045e6603ed
https://github.com/llvm/llvm-project/commit/acde20b5605f3a3a8da2217e4526fc045e6603ed
Author: Steven Perron <stevenperron at google.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/AST/HLSL/vk.spec-constant.usage.hlsl
R clang/test/CodeGenHLSL/inline-spirv/SpirvType.alignment.hlsl
R clang/test/CodeGenHLSL/inline-spirv/SpirvType.hlsl
A clang/test/CodeGenHLSL/vk-features/SpirvType.alignment.hlsl
A clang/test/CodeGenHLSL/vk-features/SpirvType.hlsl
A clang/test/CodeGenHLSL/vk-features/vk.spec-constant.hlsl
A clang/test/SemaHLSL/vk.spec-constant.error.hlsl
Log Message:
-----------
[HLSL][SPIRV] Add vk::constant_id attribute. (#143544)
The vk::constant_id attribute is used to indicate that a global const
variable
represents a specialization constant in SPIR-V. This PR adds this
attribute to clang.
The documentation for the attribute is
[here](https://github.com/microsoft/DirectXShaderCompiler/blob/main/docs/SPIR-V.rst#specialization-constants).
The strategy is to to modify the initializer to get the value of a
specialize constant for a builtin defined in the SPIR-V backend.
Implements https://github.com/llvm/wg-hlsl/pull/287
Fixes https://github.com/llvm/llvm-project/issues/142448
---------
Co-authored-by: Nathan Gauër <github at keenuts.net>
Commit: d3441f7348203cc2a1d9c44fd24c1113954aa2b2
https://github.com/llvm/llvm-project/commit/d3441f7348203cc2a1d9c44fd24c1113954aa2b2
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV] Change getSmallBestKnownTC to return an ElementCount (NFC) (#141793)
This is prep work for enabling better UF calculations when using vscale
based VFs to vectorise loops with vscale based tripcounts.
NOTE: NFC because All uses remain fixed-length until a following PR
changes LoopVectorize's version of getSmallConstantTripCount().
Commit: b7ef5dbac91f9ccaf335ae4dd998e5783523f24e
https://github.com/llvm/llvm-project/commit/b7ef5dbac91f9ccaf335ae4dd998e5783523f24e
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
M llvm/test/CodeGen/AArch64/complex-deinterleaving-splat-scalable.ll
Log Message:
-----------
[LLVM][ComplexDeinterleaving] Update splat identification to include vector ConstantInt/FP. (#144516)
Commit: b5967264b0fbfd502b3a7edec27409e966fb68be
https://github.com/llvm/llvm-project/commit/b5967264b0fbfd502b3a7edec27409e966fb68be
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/Support/CodeGen.h
M llvm/include/llvm/Target/TargetOptions.h
Log Message:
-----------
CodeGen: Move ABI option enums to support (#142912)
Move these out of TargetOptions and into Support to avoid
the dependency on Target. There are similar ABI options
already in Support/CodeGen.h.
Commit: 4aca3dc48b0919b81bd86302b141f29869266c45
https://github.com/llvm/llvm-project/commit/4aca3dc48b0919b81bd86302b141f29869266c45
Author: Robert Imschweiler <robert.imschweiler at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
Log Message:
-----------
Reland: [GlobalISel] prevent G_UNMERGE_VALUES for vectors with different elements (#144661)
This commit prevents building a G_UNMERGE_VALUES instruction with
different source and destination vector elements in
`LegalizationArtifactCombiner::ArtifactValueFinder::tryCombineMergeLike()`,
e.g.:
`%1:_(<2 x s8>), %2:_(<2 x s8>) = G_UNMERGE_VALUES %0:_(<2 x s16>)`
This LLVM defect was identified via the AMD Fuzzing project.
Commit: c3efe7d64cebcd8679bec3ba7ff8154f8b0a1fa4
https://github.com/llvm/llvm-project/commit/c3efe7d64cebcd8679bec3ba7ff8154f8b0a1fa4
Author: Martin Storsjö <martin at martin.st>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M libcxx/test/libcxx/odr_signature.exceptions.sh.cpp
M libcxx/test/libcxx/odr_signature.hardening.sh.cpp
Log Message:
-----------
[libcxx] [test] Fix odr_signature tests with optimizations enabled (#144317)
If optimization is enabled, the inline `f()` function actually gets
inlined, meaning that the functions `tu1()` and `tu2()` trivially return
1 and 2, instead of actually referencing the potentially linker
deduplicated function `f()`, which is what the test tries to test.
Therefore, this test previously actually failed to test what it was
supposed to test, if optimization was enabled.
Mark the inline functions with `TEST_NOINLINE` to make sure that they
don't get inlined even with optimizations enabled.
Also update the TODO comments to explain why we have an XFAIL for msvc
mode here.
This avoids these tests unexpectedly passing if building in msvc mode,
with optimizations enabled
(`-DLIBCXX_TEST_PARAMS="optimization=speed"`).
Commit: 66d6964a55014e7fabb7c80fbba19d2145262b6b
https://github.com/llvm/llvm-project/commit/66d6964a55014e7fabb7c80fbba19d2145262b6b
Author: Garvit Gupta <quic_garvgupt at quicinc.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/test/Driver/aarch64-toolchain-extra.c
M clang/test/Driver/aarch64-toolchain.c
M clang/test/Driver/arm-toolchain-extra.c
M clang/test/Driver/arm-toolchain.c
Log Message:
-----------
Fix tests failing on fuchsia clang x86_64 builders (#144655)
Fuchsia sets CLANG_DEFAULT_UNWINDLIB to libunwind. As a result, when
rtlib is set to libgcc and unwindlib is not explicitly specified, tests
using Fuchsia as the default platform will fail. To address this, the
affected tests are now xfailed
This change fixes the following tests introduced in
https://github.com/llvm/llvm-project/commit/45ea46c44636094e9fcdbbeabfd11f9d0fad5e38:
clang/test/Driver/aarch64-toolchain-extra.c
clang/test/Driver/arm-toolchain-extra.c
clang/test/Driver/aarch64-toolchain.c
clang/test/Driver/arm-toolchain.c
Commit: 8a469da8b2342dd9104faf25deeddd8ad66ca6a6
https://github.com/llvm/llvm-project/commit/8a469da8b2342dd9104faf25deeddd8ad66ca6a6
Author: Oleksandr "Alex" Zinenko <git at ozinenko.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/lib/Dialect/MemRef/Transforms/ExpandOps.cpp
M mlir/test/Dialect/MemRef/expand-ops.mlir
Log Message:
-----------
[mlir] remove unnecessary atomic_rmw expansions (#144515)
The expansion of `memref.atomic_rmw` into a `memref.generic_atomic_rmw`
for floating-point min/max operations is no longer necessary as those
are now supported by the LLVM dialect and LLVM IR.
Furthermore, combining this expansion with direct lowering of
`generic_atomic_rmw` could leads to invalid LLVM dialect IR with
`cmpxchg` operating on floating-point values that it does not support.
Commit: d8e8ab79773f739c602c5869f80c6c5b5962c558
https://github.com/llvm/llvm-project/commit/d8e8ab79773f739c602c5869f80c6c5b5962c558
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/test/CodeGen/AArch64/stack-hazard.ll
Log Message:
-----------
[AArch64][SME] Fix restoring callee-saves from FP with hazard padding (#143371)
Currently, when hazard-padding is enabled a (fixed-size) hazard slot is
placed in the CS area, just after the frame record. The size of this
slot is part of the "CalleeSaveBaseToFrameRecordOffset". The SVE
epilogue emission code assumed this offset was always zero, and
incorrectly setting the stack pointer, resulting in all SVE registers
being reloaded from incorrect offsets.
```
| prev_lr |
| prev_fp |
| (a.k.a. "frame record") |
|-----------------------------------| <- fp(=x29)
| <hazard padding> |
|-----------------------------------| <- callee-saved base
| |
| callee-saved fp/simd/SVE regs |
| |
|-----------------------------------| <- SVE callee-save base
```
i.e. in the above diagram, the code assumed `fp == callee-saved base`.
Commit: 34a48941498d95ec2682f7adaeb6115b7b4d70ba
https://github.com/llvm/llvm-project/commit/34a48941498d95ec2682f7adaeb6115b7b4d70ba
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] detectZextAbsDiff - use SDPatternMatch::m_Abs() matcher. NFC.
Commit: 7c15edb306932e41c159f3d69c161ed0d89d47b7
https://github.com/llvm/llvm-project/commit/7c15edb306932e41c159f3d69c161ed0d89d47b7
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Descriptor.cpp
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/Floating.h
M clang/lib/AST/ByteCode/Integral.h
M clang/lib/AST/ByteCode/IntegralAP.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
M clang/lib/AST/ByteCode/InterpState.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ByteCode/PrimType.h
M clang/lib/AST/ByteCode/Program.h
M clang/test/AST/ByteCode/builtin-bit-cast-long-double.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
Log Message:
-----------
Reapply "[clang][bytecode] Allocate IntegralAP and Floating types usi… (#144676)
…ng an allocator (#144246)"
This reverts commit 57828fec760f086b334ce0cb1c465fc559dcaea4.
Commit: 6265ca686dfe18e6032e59637f144bad7ea6cf2b
https://github.com/llvm/llvm-project/commit/6265ca686dfe18e6032e59637f144bad7ea6cf2b
Author: Ties Stuij <ties.stuij at arm.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64.td
M llvm/lib/Target/AArch64/AArch64Processors.td
A llvm/lib/Target/AArch64/AArch64SchedA320.td
A llvm/test/tools/llvm-mca/AArch64/Cortex/A320-basic-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Cortex/A320-neon-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Cortex/A320-sve-instructions.s
Log Message:
-----------
[AArch64] Add Cortex-A320 scheduling model (#144385)
Instead of using the Cortex-A510 scheduling model, Cortex-A320 now uses
its own scheduling model, based off of the Cortex-A320 Software
Optimization Guide:
https://developer.arm.com/documentation/110285/r0p1
---------
Co-authored-by: Nashe Mncube <Nashe.Mncube at arm.com>
Commit: a1c2a712939897251729b6fc436a2db7db6f03fc
https://github.com/llvm/llvm-project/commit/a1c2a712939897251729b6fc436a2db7db6f03fc
Author: Andrei Golubev <andrey.golubev at intel.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparsificationAndBufferizationPass.cpp
Log Message:
-----------
[mlir][bufferization] Use Type instead of Value in unknown conversion (#144658)
Generally, bufferization should be able to create a memref from a tensor
without needing to know more than just a mlir::Type. Thus, change
BufferizationOptions::UnknownTypeConverterFn to accept just a type
(mlir::TensorType for now) instead of mlir::Value. Additionally, apply
the same rationale to getMemRefType() helper function.
Both changes are prerequisites to enable custom types support in
one-shot bufferization.
Commit: 66580f77b826e71a9727f1d6287bec6a6101f620
https://github.com/llvm/llvm-project/commit/66580f77b826e71a9727f1d6287bec6a6101f620
Author: Matthias Springer <me at m-sp.org>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/lib/Transforms/Utils/DialectConversion.cpp
Log Message:
-----------
[mlir][Transforms][NFC] Dialect Conversion: Keep `unresolvedMaterializations` up to date (#144254)
`unresolvedMaterializations` is a mapping from
`UnrealizedConversionCastOp` to `UnresolvedMaterializationRewrite`. This
mapping is needed to find the correct type converter for an unresolved
materialization.
With this commit, `unresolvedMaterializations` is updated immediately
when an op is being erased. This also cleans up the code base a bit:
`SingleEraseRewriter` is now used only during the "cleanup" phase and no
longer needed as a field of `ConversionRewriterImpl`.
This commit is in preparation of the One-Shot Dialect Conversion
refactoring: `allowPatternRollback = false` will in the future trigger
immediate materialization of all IR changes.
Commit: 4b2ab1494bc07493087252dff4e5e19808703048
https://github.com/llvm/llvm-project/commit/4b2ab1494bc07493087252dff4e5e19808703048
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Lower/OpenMP/Todo/declare-mapper-iterator.f90
Log Message:
-----------
[flang][OpenMP] Don't crash on iterator modifier in declare mapper (#144359)
Both the declare mapper directive argument, and the iterator modifier
can contain declaration-type-spec, so make sure that the processing of
one ends before processing of the other begins in semantic analysis.
Commit: a83d3362f686725bac76bfb9562663908de25f15
https://github.com/llvm/llvm-project/commit/a83d3362f686725bac76bfb9562663908de25f15
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M flang/lib/Semantics/resolve-directives.cpp
R flang/test/Lower/OpenMP/Todo/omp-doconcurrent.f90
A flang/test/Semantics/OpenMP/do-concurrent-collapse.f90
Log Message:
-----------
[flang][OpenMP] Don't allow DO CONCURRENT inside of a loop nest (#144506)
I don't think DO CONCURRENT fits the definition of a Canonical Loop Nest
(OpenMP 6.0 section 6.4.1).
It is however explicitly allowed for the LOOP construct (6.0 section
13.8).
There's some obscure language in OpenMP 6.0 for the LOOP construct:
> If the collapsed loop is a DO CONCURRENT loop, neither the
> data-sharing attribute clauses nor the collapse clause may be
specified.
>From the surrounding context, I think "collapsed loop" just means the
loop that the LOOP construct applies to. So I will interpret this to
mean that DO CONCURRENT can only be used with the LOOP construct if it
does not contain the COLLAPSE clause.
This also fixes a bug where the associated clause was never cleared
after it was set.
Fixes #144178
Commit: 8584abb05a84d3bf4e84cdfe4154d7ade8bdfd04
https://github.com/llvm/llvm-project/commit/8584abb05a84d3bf4e84cdfe4154d7ade8bdfd04
Author: Frank Schlimbach <frank.schlimbach at intel.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
A mlir/test/Target/SPIRV/lit.local.cfg
R mlir/test/lit.local.cfg
Log Message:
-----------
[mlir] mlir/test/lit.local.cfg -> mlir/test/Target/SPIRV/lit.local.cfg (#144685)
renamed: mlir/test/lit.local.cfg -> mlir/test/Target/SPIRV/lit.local.cfg
Commit: 68471d29eed2c49f9b439e505b3f24d387d54f97
https://github.com/llvm/llvm-project/commit/68471d29eed2c49f9b439e505b3f24d387d54f97
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Descriptor.cpp
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/Floating.h
M clang/lib/AST/ByteCode/Integral.h
M clang/lib/AST/ByteCode/IntegralAP.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
M clang/lib/AST/ByteCode/InterpState.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ByteCode/PrimType.h
M clang/lib/AST/ByteCode/Program.h
M clang/test/AST/ByteCode/builtin-bit-cast-long-double.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
Log Message:
-----------
Revert "Reapply "[clang][bytecode] Allocate IntegralAP and Floating types usi… (#144676)"
This reverts commit 7c15edb306932e41c159f3d69c161ed0d89d47b7.
This still breaks clang-armv8-quick:
https://lab.llvm.org/buildbot/#/builders/154/builds/17587
Commit: 6729da647afa2b0ee040ccd4f06153e45d6ca738
https://github.com/llvm/llvm-project/commit/6729da647afa2b0ee040ccd4f06153e45d6ca738
Author: Kunwar Grover <groverkss at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.h
M mlir/lib/Dialect/AMDGPU/Transforms/EmulateAtomics.cpp
M mlir/lib/Dialect/AMDGPU/Transforms/ResolveStridedMetadata.cpp
M mlir/lib/Dialect/AMDGPU/Transforms/TransferReadToLoad.cpp
Log Message:
-----------
[mlir][amdgpu][nfc] Add PatternBenefit to populate methods (#144663)
Commit: c4d99704e22097703c57ee67baea96fdabfd68ab
https://github.com/llvm/llvm-project/commit/c4d99704e22097703c57ee67baea96fdabfd68ab
Author: Garvit Gupta <quic_garvgupt at quicinc.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/docs/Toolchain.rst
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/lib/Driver/ToolChains/BareMetal.cpp
M clang/lib/Driver/ToolChains/BareMetal.h
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/include/c++/8.2.1/.keep
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/lib/.keep
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/lib/crt0.o
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/bin/aarch64-none-elf-ld
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/crtbegin.o
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/crtend.o
R clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crt0.o
R clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crtbegin.o
R clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crtend.o
R clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/bin/aarch64-none-elf-ld
R clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/include/c++/8.2.1/.keep
R clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/lib/.keep
R clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/lib/crt0.o
R clang/test/Driver/Inputs/basic_arm_gcc_tree/bin/armv6m-none-eabi-ld
R clang/test/Driver/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/crtbegin.o
R clang/test/Driver/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/crtend.o
R clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crt0.o
R clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crtbegin.o
R clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crtend.o
R clang/test/Driver/Inputs/basic_arm_nogcc_tree/bin/armv6m-none-eabi-ld
R clang/test/Driver/aarch64-gnutools.c
R clang/test/Driver/aarch64-toolchain-extra.c
R clang/test/Driver/aarch64-toolchain.c
R clang/test/Driver/arm-gnutools.c
R clang/test/Driver/arm-toolchain-extra.c
R clang/test/Driver/arm-toolchain.c
M clang/test/Driver/baremetal.cpp
R clang/test/Driver/check-no-multlib-warning.c
Log Message:
-----------
Revert "Reland [Driver] Add support for GCC installation detection in… (#144684)
… Baremetal toolchain (#144640)"
This reverts commit 45ea46c44636094e9fcdbbeabfd11f9d0fad5e38.
Commit: 1f34d68c4f086e7ea6ef9a529f9606476b38bbbb
https://github.com/llvm/llvm-project/commit/1f34d68c4f086e7ea6ef9a529f9606476b38bbbb
Author: Tobias Stadler <mail at stadler-tobias.de>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/docs/CommandGuide/llvm-opt-report.rst
M llvm/docs/Remarks.rst
M llvm/include/llvm/Remarks/RemarkFormat.h
M llvm/include/llvm/Remarks/RemarkParser.h
M llvm/include/llvm/Remarks/YAMLRemarkSerializer.h
M llvm/lib/Remarks/BitstreamRemarkParser.cpp
M llvm/lib/Remarks/BitstreamRemarkParser.h
M llvm/lib/Remarks/RemarkFormat.cpp
M llvm/lib/Remarks/RemarkLinker.cpp
M llvm/lib/Remarks/RemarkParser.cpp
M llvm/lib/Remarks/RemarkSerializer.cpp
M llvm/lib/Remarks/RemarkStreamer.cpp
M llvm/lib/Remarks/YAMLRemarkParser.cpp
M llvm/lib/Remarks/YAMLRemarkParser.h
M llvm/lib/Remarks/YAMLRemarkSerializer.cpp
M llvm/test/CodeGen/X86/remarks-section.ll
M llvm/unittests/Remarks/RemarksLinkingTest.cpp
M llvm/unittests/Remarks/YAMLRemarksParsingTest.cpp
M llvm/unittests/Remarks/YAMLRemarksSerializerTest.cpp
Log Message:
-----------
[Remarks] Remove yaml-strtab format (#144527)
Background: The yaml-strtab format looks just like the yaml format,
except that the values in the key/value pairs of the remarks are
deduplicated and replaced by indices into a string table (see removed
test cases for examples). The motivation behind this format was to
reduce size of the remarks files. However, it was quickly superseded by
the bitstream format.
Therefore, remove the yaml-strtab format, as it doesn't have a good
usecase anymore:
- It isn't particularly efficient
- It isn't human-readable
- It isn't straightforward to parse in external tools that can't use the
remarks library. We don't even support it in opt-viewer.
llvm-remarkutil is also missing options to parse/convert yaml-strtab, so
the chance that anyone is actually using this format is low.
Commit: 671caef379c603d2bcc428a00e3535b230162941
https://github.com/llvm/llvm-project/commit/671caef379c603d2bcc428a00e3535b230162941
Author: Jack Styles <jack.styles at arm.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M flang/lib/Semantics/resolve-directives.cpp
M flang/test/Semantics/OpenMP/allocate-align01.f90
M flang/test/Semantics/OpenMP/allocate01.f90
M flang/test/Semantics/OpenMP/allocate02.f90
M flang/test/Semantics/OpenMP/allocate03.f90
M flang/test/Semantics/OpenMP/allocate05.f90
M flang/test/Semantics/OpenMP/allocate06.f90
M flang/test/Semantics/OpenMP/allocate09.f90
M flang/test/Semantics/OpenMP/clause-validity01.f90
M flang/test/Semantics/OpenMP/deprecation.f90
M flang/test/Semantics/OpenMP/flush02.f90
M flang/test/Semantics/OpenMP/nested-barrier.f90
M flang/test/Semantics/OpenMP/nested-master.f90
M flang/test/Semantics/OpenMP/nested-teams.f90
M flang/test/Semantics/OpenMP/ordered-simd.f90
M flang/test/Semantics/OpenMP/parallel-master-goto.f90
Log Message:
-----------
[Flang][OpenMP] Update relevant warnings to emit when OMP >= v5.2 (#144492)
There has been a number of deprecation warnings that have been added to
Flang, however these features are only deprecated when the OpenMP
Version being used is 5.2 or later. Previously, flang did not consider
the version with the warnings so would always be emitted.
Flang now ensures warnings are emitted for the appropriate version of
OpenMP, and tests are updated to reflect this change.
Commit: fda6b751f1b1356e65816f85fbc5b98e78337940
https://github.com/llvm/llvm-project/commit/fda6b751f1b1356e65816f85fbc5b98e78337940
Author: Eric Fiselier <eric at efcs.ca>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M .github/workflows/libcxx-restart-preempted-jobs.yaml
Log Message:
-----------
Fix libc++ restarter job.
A while ago, the test workflow was updated with a new preemption regex,
however it was only applied to the test job, and not the job
that's actually restarting the failed libc++ test runs.
This fix should correct the issue and get the restarter working
again.
Commit: bdac9580f3bc341ccbeeb743ecca656756f5aaec
https://github.com/llvm/llvm-project/commit/bdac9580f3bc341ccbeeb743ecca656756f5aaec
Author: Mircea Trofin <mtrofin at google.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/Transforms/Scalar/JumpThreading.h
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
Log Message:
-----------
[nfc][jt] Drop `std::optional` pointers (#144548)
The `std::optional` didn't add any semantics that couldn't be modeled with the pointers being `nullptr`.
Commit: c5613dc8635000bc0e8396b8156d5639195776ab
https://github.com/llvm/llvm-project/commit/c5613dc8635000bc0e8396b8156d5639195776ab
Author: lorenzo chelini <l.chelini at icloud.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
M mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
M mlir/test/Integration/GPU/CUDA/dump-ptx.mlir
Log Message:
-----------
[MLIR] Mark LLVM::FMAOp as legal (#144671)
Mark LLVM::FMAOp as legal in configureGpuToNVVMConversionLegality, since
we can handle intrinsic lowering in the NVPTX backend and emit
fma.rn.f32.
Commit: 1d6f1029f7e8cf5468309078da3e85201844b625
https://github.com/llvm/llvm-project/commit/1d6f1029f7e8cf5468309078da3e85201844b625
Author: Sergei Lebedev <185856+superbobry at users.noreply.github.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
Log Message:
-----------
[mlir] [python] Fixed the return type of `MemRefType.get_strides_and_offset` (#144523)
Previously, the return type for `offset` was `list[int]`, which clearly
is not right.
Commit: 9db7502d229b48817521429c2a5d3fb84543fdf9
https://github.com/llvm/llvm-project/commit/9db7502d229b48817521429c2a5d3fb84543fdf9
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M libcxx/include/__iterator/iterator_traits.h
Log Message:
-----------
[libc++] Move __has_iterator_typedefs to the up-to-C++17 implementation of iterator_traits (#144265)
`__has_iterator_typedefs` is only used in the up-to-C++17 implementation
of `type_traits`. To make that clearer the struct is moved into that
code block.
Commit: 40d2f392106f43a60eea79f433b47a5ce44fc4a4
https://github.com/llvm/llvm-project/commit/40d2f392106f43a60eea79f433b47a5ce44fc4a4
Author: Akira Hatanaka <ahatanak at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Sema/SemaObjC.h
M clang/lib/Sema/SemaCast.cpp
M clang/lib/Sema/SemaExprObjC.cpp
M clang/test/SemaObjCXX/arc-type-conversion.mm
Log Message:
-----------
[Sema][ObjC] Loosen restrictions on reinterpret_cast involving indirect ARC-managed pointers (#144458)
Allow using reinterpret_cast for conversions between indirect ARC
pointers and other pointer types.
rdar://152905399
Commit: ee070d08163ac09842d9bf0c1315f311df39faf1
https://github.com/llvm/llvm-project/commit/ee070d08163ac09842d9bf0c1315f311df39faf1
Author: Andrei Golubev <andrey.golubev at intel.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationOps.td
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationTypeInterfaces.h
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationTypeInterfaces.td
M mlir/include/mlir/Dialect/Bufferization/IR/UnstructuredControlFlow.h
M mlir/lib/Dialect/Arith/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationDialect.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
A mlir/lib/Dialect/Bufferization/IR/BufferizationTypeInterfaces.cpp
M mlir/lib/Dialect/Bufferization/IR/CMakeLists.txt
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
M mlir/lib/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Linalg/Transforms/ConvertToDestinationStyle.cpp
M mlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Shape/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseGPUCodegen.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorCodegen.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenUtils.cpp
M mlir/lib/Dialect/Tensor/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/test/Dialect/Bufferization/Transforms/one-shot-bufferize.mlir
M mlir/test/lib/Dialect/Test/TestOpDefs.cpp
M mlir/test/lib/Dialect/Test/TestOps.h
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/test/lib/Dialect/Test/TestTypeDefs.td
M mlir/test/lib/Dialect/Test/TestTypes.cpp
Log Message:
-----------
[mlir][bufferization] Support custom types (1/N) (#142986)
Following the addition of TensorLike and BufferLike type interfaces (see
00eaff3e9c897c263a879416d0f151d7ca7eeaff), introduce minimal changes
required to bufferize a custom tensor operation into a custom buffer
operation.
To achieve this, new interface methods are added to TensorLike type
interface that abstract away the differences between existing (tensor ->
memref) and custom conversions.
The scope of the changes is intentionally limited (for example,
BufferizableOpInterface is untouched) in order to first understand the
basics and reach consensus design-wise.
---
Notable changes:
* mlir::bufferization::getBufferType() returns BufferLikeType (instead
of BaseMemRefType)
* ToTensorOp / ToBufferOp operate on TensorLikeType / BufferLikeType.
Operation argument "memref" renamed to "buffer"
* ToTensorOp's tensor type inferring builder is dropped (users now need
to provide the tensor type explicitly)
Commit: 6f4add34801e6ce02a5ebc96df4d1ca479125649
https://github.com/llvm/llvm-project/commit/6f4add34801e6ce02a5ebc96df4d1ca479125649
Author: Omair Javaid <omair.javaid at linaro.org>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M compiler-rt/lib/fuzzer/tests/CMakeLists.txt
Log Message:
-----------
[compiler-rt] [Fuzzer] Fix ARMv7 test link failure by linking unwinder (#144495)
compiler-rt/lib/fuzzer/tests build was failing on armv7, with undefined
references to unwinder symbols, such as __aeabi_unwind_cpp_pr0.
This occurs because the test is built with `-nostdlib++` but `libunwind`
is not explicitly linked to the final test executable.
This patch resolves the issue by adding CMake logic to explicitly link
the required unwinder to the fuzzer tests, inspired by the same solution
used to fix Scudo build failures by https://reviews.llvm.org/D142888.
Commit: 36038a1048b2aab87ed18f982e960c044ad97670
https://github.com/llvm/llvm-project/commit/36038a1048b2aab87ed18f982e960c044ad97670
Author: Orlando Cazalet-Hyams <orlando.hyams at sony.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/CodeGen/FunctionLoweringInfo.h
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Log Message:
-----------
[RemoveDIs][NFC] Remove dbg intrinsic handling code from SelectionDAG ISel (#144702)
Commit: 8fc20bffabe7fe6cdc4a9ec1bc79202eba5f1f23
https://github.com/llvm/llvm-project/commit/8fc20bffabe7fe6cdc4a9ec1bc79202eba5f1f23
Author: Karlo Basioli <k.basioli at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
Fix bazel build issue caused by 142986 (#144721)
Commit: e4c3b037bc7f5d9a8089de4c509d3e6034735891
https://github.com/llvm/llvm-project/commit/e4c3b037bc7f5d9a8089de4c509d3e6034735891
Author: amordo <iammorjj at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
A llvm/test/Transforms/InstCombine/fmul-tan-cos.ll
Log Message:
-----------
[InstCombine] Fold `tan(x) * cos(x) => sin(x)` (#136319)
This patch enables folding `tan(x) * cos(x) -> sin(x)` under the `contract` flag.
Fixes https://github.com/llvm/llvm-project/issues/34950.
Commit: b53c1e4ee810ac21dab5d27413af1f31a6a4cbfa
https://github.com/llvm/llvm-project/commit/b53c1e4ee810ac21dab5d27413af1f31a6a4cbfa
Author: John Brawn <john.brawn at arm.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
A llvm/test/CodeGen/AArch64/vector-ldst-offset.ll
M llvm/test/CodeGen/AArch64/zext-to-tbl.ll
Log Message:
-----------
[AArch64] Add ISel for postindex ld1/st1 in big-endian (#144387)
When big-endian we need to use ld1/st1 for vector loads and stores so
that we get the elements in the correct order, but this prevents
postindex addressing from being used. Fix this by adding the appropriate
ISel patterns, plus the relevant changes in ISelLowering and
ISelDAGToDAG to cause postindex addressing to be used.
Commit: 3af4d4e8100fda2a7e1bd0dbbe0914b584ad08d6
https://github.com/llvm/llvm-project/commit/3af4d4e8100fda2a7e1bd0dbbe0914b584ad08d6
Author: Nathan Gauër <brioche at google.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/test/CodeGenHLSL/semantics/SV_Position.ps.hlsl
A llvm/test/CodeGen/SPIRV/linkage/link-attribute-vk.ll
Log Message:
-----------
[HLSL][SPIR-V] Fix LinkageAttribute emission for BuiltIn (#144701)
BuiltIn variables were missing the visibility attribute, which caused
the Linkage capability to be emitted by the backend.
Commit: 8b8a3699dbdbb5d7865b0fe330d972c3fa380f1e
https://github.com/llvm/llvm-project/commit/8b8a3699dbdbb5d7865b0fe330d972c3fa380f1e
Author: Graham Hunter <graham.hunter at arm.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/sve2p1-vector-shuffles.ll
Log Message:
-----------
[AArch64] Use dupq (SVE2.1) for segmented lane splats (#144482)
Use the dupq instructions (when available) to represent a splat of the
same lane within each 128b segment of a wider fixed vector.
Commit: 9da9d32670ddbf610f0788236e78b2382037f00b
https://github.com/llvm/llvm-project/commit/9da9d32670ddbf610f0788236e78b2382037f00b
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
A llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
Log Message:
-----------
[AMDGPU][True16][CodeGen] sext i16 inreg in true16 mode (#144024)
update sext pattern in true16, setting up proper vgpr16 reg use
Commit: 5d502aeddf2a5d93c3fd93103054261acf4d92f3
https://github.com/llvm/llvm-project/commit/5d502aeddf2a5d93c3fd93103054261acf4d92f3
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
M flang/test/Semantics/OpenMP/atomic-update-only.f90
M flang/test/Semantics/OpenMP/atomic03.f90
M flang/test/Semantics/OpenMP/atomic04.f90
Log Message:
-----------
[flang][OpenMP] Clarify confusing error message (#144707)
The message "The atomic variable x should occur exactly once among the
arguments of the top-level [...] operator" was intended to convey that
(1) an atomic variable should be an argument, and (2) it should be
exactly one of the arguments. However, the wording turned out to be
sowing confusion instead.
Rework the corresponding check, and emit an individual error message for
each problematic situation:
- "atomic variable cannot be a proper subexpression of an argument",
- "atomic variable should appear as an argument",
- "atomic variable should be exactly one of the arguments".
Fixes https://github.com/llvm/llvm-project/issues/144599
Commit: b5aaf9d988ff2dc652c86271b181bf0497eb97cb
https://github.com/llvm/llvm-project/commit/b5aaf9d988ff2dc652c86271b181bf0497eb97cb
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/test/Transforms/InstCombine/vp-reverse.ll
Log Message:
-----------
[InstCombine] Implement vp.reverse reordering/elimination through binop/unop (#143963)
This simply copies the structure of the vector.reverse patterns from
just above, and reimplements them for the vp.reverse intrinsics when the
mask is all ones and the EVLs exactly match.
Its unfortunate that we have three different ways to represent a reverse
(shuffle, vector.reverse, and vp.reverse) but I don't see an obvious way
to remove any them because the semantics are slightly different.
This significantly improves vectorization in TSVC_2's s112 and s1112
loops when using EVL tail folding.
Commit: 0fa373c77ded203eddb973c79244c75ee5957eaf
https://github.com/llvm/llvm-project/commit/0fa373c77ded203eddb973c79244c75ee5957eaf
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
A llvm/test/Transforms/LowerMatrixIntrinsics/phi.ll
M llvm/test/Transforms/LowerMatrixIntrinsics/propagate-backwards-unsupported.ll
Log Message:
-----------
[Matrix] Propagate shape information through PHI insts (#141681)
... and split them as we lower them, avoiding several shuffles in the
process.
Commit: a2cee05449636c8e0d630b2ccdc71f2d422227a9
https://github.com/llvm/llvm-project/commit/a2cee05449636c8e0d630b2ccdc71f2d422227a9
Author: Christopher Ferris <cferris1000 at users.noreply.github.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M compiler-rt/lib/scudo/standalone/chunk.h
M compiler-rt/lib/scudo/standalone/combined.h
M compiler-rt/lib/scudo/standalone/report.cpp
M compiler-rt/lib/scudo/standalone/report.h
Log Message:
-----------
[scudo] Make report pointers const. (#144624)
Mark as many of the reportXX functions that take pointers const. This
avoid the need to use const_cast when calling these functions on an
already const pointer.
Fix reportHeaderCorruption calls where an argument was passed into an
append call that didn't use them.
Commit: 13510c07364dc3ac30f34e73c98ac8dc75e7efc7
https://github.com/llvm/llvm-project/commit/13510c07364dc3ac30f34e73c98ac8dc75e7efc7
Author: Peng Liu <winner245 at hotmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M libcxx/docs/FeatureTestMacroTable.rst
M libcxx/include/list
M libcxx/include/version
M libcxx/test/std/containers/sequences/list/compare.pass.cpp
M libcxx/test/std/containers/sequences/list/compare.three_way.pass.cpp
M libcxx/test/std/containers/sequences/list/get_allocator.pass.cpp
M libcxx/test/std/containers/sequences/list/incomplete_type.pass.cpp
M libcxx/test/std/containers/sequences/list/iterators.pass.cpp
M libcxx/test/std/containers/sequences/list/list.capacity/empty.pass.cpp
M libcxx/test/std/containers/sequences/list/list.capacity/max_size.pass.cpp
M libcxx/test/std/containers/sequences/list/list.capacity/resize_size.pass.cpp
M libcxx/test/std/containers/sequences/list/list.capacity/resize_size_value.pass.cpp
M libcxx/test/std/containers/sequences/list/list.capacity/size.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/assign_copy.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/assign_initializer_list.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/assign_move.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/copy.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/copy_alloc.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/default.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/default_stack_alloc.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/from_range.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/initializer_list.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/initializer_list_alloc.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/input_iterator.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/move.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/move_alloc.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/op_equal_initializer_list.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/size_type.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/size_value_alloc.pass.cpp
M libcxx/test/std/containers/sequences/list/list.erasure/erase.pass.cpp
M libcxx/test/std/containers/sequences/list/list.erasure/erase_if.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/append_range.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/assign_range.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/clear.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/emplace.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/emplace_back.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/emplace_front.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/erase_iter.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/erase_iter_iter.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/insert_iter_initializer_list.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/insert_iter_iter_iter.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/insert_iter_rvalue.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/insert_iter_size_value.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/insert_iter_value.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/insert_range.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/pop_back.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/pop_front.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/prepend_range.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/push_back.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/push_back_rvalue.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/push_front.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/push_front_rvalue.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/merge.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/merge_comp.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/remove.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/remove_if.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/reverse.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/sort.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/sort_comp.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/splice_pos_list.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/splice_pos_list_iter.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/splice_pos_list_iter_iter.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/unique.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/unique_pred.pass.cpp
M libcxx/test/std/containers/sequences/list/list.special/swap.pass.cpp
M libcxx/test/std/containers/sequences/list/list.special/swap_noexcept.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/list.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
M libcxx/test/support/min_allocator.h
M libcxx/utils/generate_feature_test_macro_components.py
Log Message:
-----------
[libc++] Make list constexpr as part of P3372R3 (#129799)
This patch makes `std::list` constexpr as part of P3372R3.
Fixes #128659.
Commit: 6d785ca4218b18e77e39320bea7f8973c3ea2764
https://github.com/llvm/llvm-project/commit/6d785ca4218b18e77e39320bea7f8973c3ea2764
Author: Ying Yi <ying.yi at sony.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/test/PCH/ignored-pch.c
Log Message:
-----------
[Clang] Fix the clang/test/PCH/ignored-pch.c test. (#144737)
Change the test to check the exit status of the 'ls' command line
(instead of error message) since the error message is different when
running 'ls' command on the different Host machine.
Commit: 2a41350aabd8b7d3e406141a55ce0bb6f5e70a76
https://github.com/llvm/llvm-project/commit/2a41350aabd8b7d3e406141a55ce0bb6f5e70a76
Author: Karlo Basioli <k.basioli at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
Fix bazel build issue caused by #142986 second attempt (#144721 didnt… (#144743)
… cover everything)
Commit: dd40c460c42d075c47f0d1a6d83f129655eafe10
https://github.com/llvm/llvm-project/commit/dd40c460c42d075c47f0d1a6d83f129655eafe10
Author: Peng Liu <winner245 at hotmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M libcxx/include/forward_list
Log Message:
-----------
[libc++] Clean up casts in std::forward_list (#130310)
The patch removes unnecessary casts to `void*` pointers, inline some
casts, and eliminates an identity cast.
Commit: 9827440f1e723423baf4c235e844eb8ac48a8f97
https://github.com/llvm/llvm-project/commit/9827440f1e723423baf4c235e844eb8ac48a8f97
Author: Peng Liu <winner245 at hotmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M libcxx/docs/ReleaseNotes/21.rst
M libcxx/include/__algorithm/for_each.h
M libcxx/include/__algorithm/for_each_n.h
M libcxx/include/__algorithm/ranges_for_each.h
M libcxx/include/__algorithm/ranges_for_each_n.h
M libcxx/include/experimental/iterator
M libcxx/include/mutex
M libcxx/include/shared_mutex
M libcxx/test/benchmarks/algorithms/nonmodifying/for_each.bench.cpp
M libcxx/test/benchmarks/algorithms/nonmodifying/for_each_n.bench.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.foreach/ranges.for_each.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.foreach/ranges.for_each_n.pass.cpp
Log Message:
-----------
[libc++] Optimize ranges::{for_each, for_each_n} for segmented iterators (#132896)
Previously, the segmented iterator optimization was limited to `std::{for_each, for_each_n}`. This patch
extends the optimization to `std::ranges::for_each` and `std::ranges::for_each_n`, ensuring consistent
optimizations across these algorithms. This patch first generalizes the `std` algorithms by introducing
a `Projection` parameter, which is set to `__identity` for the `std` algorithms. Then we let the `ranges`
algorithms to directly call their `std` counterparts with a general `__proj` argument. Benchmarks
demonstrate performance improvements of up to 21.4x for ``std::deque::iterator`` and 22.3x for
``join_view`` of ``vector<vector<char>>``.
Addresses a subtask of #102817.
Commit: 00189211486d052b25429f11790ef5486cf9d3ce
https://github.com/llvm/llvm-project/commit/00189211486d052b25429f11790ef5486cf9d3ce
Author: woruyu <99597449+woruyu at users.noreply.github.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
A llvm/test/CodeGen/X86/fold-masked-merge-demorgan.ll
Log Message:
-----------
[DAG] add (~a | x) & (a | y) -> (a & (x ^ y)) ^y for foldMaskedMerge (#144342)
### Summary
This PR resolves https://github.com/llvm/llvm-project/issues/143864
Add (~a | x) & (a | y) -> (a & (x ^ y)) ^y for foldMaskedMerge func
using SDPatternMatch
aftering adding this pattern, run ```ninja check-llvm-codegen```, all
other cases remain unchanged, so I add a
testcase(fold-masked-merge-demorgan.ll) for it
---------
Co-authored-by: Simon Pilgrim <llvm-dev at redking.me.uk>
Commit: fe3933da15b5bc635bce156f1f8d11a784316a07
https://github.com/llvm/llvm-project/commit/fe3933da15b5bc635bce156f1f8d11a784316a07
Author: Yang Bai <baiyang0132 at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Affine/constant-fold.mlir
M mlir/test/Dialect/Linalg/mesh-spmdization.mlir
M mlir/test/Dialect/Mesh/spmdization.mlir
M mlir/test/Dialect/Tensor/mesh-spmdization.mlir
M mlir/test/Dialect/Tosa/constant_folding.mlir
M mlir/test/Dialect/Vector/constant-fold.mlir
A mlir/test/Dialect/Vector/single-fold.mlir
M mlir/test/Transforms/constant-fold-debuginfo.mlir
M mlir/test/Transforms/constant-fold.mlir
M mlir/test/lib/Transforms/CMakeLists.txt
R mlir/test/lib/Transforms/TestConstantFold.cpp
A mlir/test/lib/Transforms/TestSingleFold.cpp
M mlir/tools/mlir-opt/mlir-opt.cpp
Log Message:
-----------
[mlir][vector] Support complete folding in single pass for vector.insert/vector.extract (#142124)
### Description
This patch improves the folding efficiency of `vector.insert` and
`vector.extract` operations by not returning early after successfully
converting dynamic indices to static indices.
This PR also renames the test pass `TestConstantFold` to
`TestSingleFold` and adds comprehensive documentation explaining the
single-pass folding behavior.
### Motivation
Since the `OpBuilder::createOrFold` function only calls `fold` **once**,
the current `fold` methods of `vector.insert` and `vector.extract` may
leave the op in a state that can be folded further. For example,
consider the following un-folded IR:
```
%v1 = vector.insert %e1, %v0 [0] : f32 into vector<128xf32>
%c0 = arith.constant 0 : index
%e2 = vector.extract %v1[%c0] : f32 from vector<128xf32>
```
If we use `createOrFold` to create the `vector.extract` op, then the
result will be:
```
%v1 = vector.insert %e1, %v0 [127] : f32 into vector<128xf32>
%e2 = vector.extract %v1[0] : f32 from vector<128xf32>
```
But this is not the optimal result. `createOrFold` should have returned
`%e1`.
The reason is that the execution of fold returns immediately after
`extractInsertFoldConstantOp`, causing subsequent folding logics to be
skipped.
---------
Co-authored-by: Yang Bai <yangb at nvidia.com>
Commit: 4084ffcf1e69b962e864aa138bb54dabbcec912f
https://github.com/llvm/llvm-project/commit/4084ffcf1e69b962e864aa138bb54dabbcec912f
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M flang/include/flang/Semantics/dump-expr.h
M flang/lib/Semantics/dump-expr.cpp
Log Message:
-----------
[flang] Show types in DumpEvExpr (#143743)
When dumping evaluate::Expr, show type names which contain a lot of
useful information.
For example show
```
expr <Fortran::evaluate::SomeType> {
expr <Fortran::evaluate::SomeKind<Fortran::common::TypeCategory::Integer>> {
expr <Fortran::evaluate::Type<Fortran::common::TypeCategory::Integer, 4>> {
...
```
instead of
```
expr T {
expr T {
expr T {
...
```
Commit: 2a8c65e983b3f4e1c83d8028d354f7bacc149015
https://github.com/llvm/llvm-project/commit/2a8c65e983b3f4e1c83d8028d354f7bacc149015
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/CodeGen/MachineFunction.cpp
Log Message:
-----------
[CodeGen][NFC] Fix quadratic c-t for large jump tables
Deleting a basic block removes all references from jump tables, which
is O(n). When freeing a MachineFunction, all basic blocks are deleted
before the jump tables, causing O(n^2) runtime. Fix this by deallocating
the jump table first.
Test case generator:
import sys
n = int(sys.argv[1])
print("define void @f(i64 %c, ptr %p) {")
print(" switch i64 %c, label %d [")
for i in range(n):
print(f" i64 {i}, label %h{i}")
print(f" ]")
for i in range(n):
print(f'h{i}:')
print(f' store i64 {i*i}, ptr %p')
print(f' ret void')
print('d:')
print(' ret void')
print('}')
Improvement at 5000 entries:
Benchmark 1: ./llc.pre -filetype=obj -O0 <switch5k.bc
Time (mean ± σ): 49.7 ms ± 1.0 ms
Range (min … max): 48.0 ms … 52.1 ms 57 runs
Benchmark 2: ./llc.post -filetype=obj -O0 <switch5k.bc
Time (mean ± σ): 39.4 ms ± 0.8 ms
Range (min … max): 37.1 ms … 41.1 ms 72 runs
Summary
./llc.post -filetype=obj -O0 <switch5k.bc ran
1.26 ± 0.04 times faster than ./llc.pre -filetype=obj -O0 <switch5k.bc
Improvement at 20000 entries:
Benchmark 1: ./llc.pre -filetype=obj -O0 <switch20k.bc
Time (mean ± σ): 281.7 ms ± 1.0 ms
Range (min … max): 280.2 ms … 283.0 ms 10 runs
Benchmark 2: ./llc.post -filetype=obj -O0 <switch20k.bc
Time (mean ± σ): 123.9 ms ± 1.5 ms
Range (min … max): 121.4 ms … 129.2 ms 23 runs
Summary
./llc.post -filetype=obj -O0 <switch20k.bc ran
2.27 ± 0.03 times faster than ./llc.pre -filetype=obj -O0 <switch20k.bc
Pull Request: https://github.com/llvm/llvm-project/pull/144108
Commit: 77bc25485135b8a8cb2427910a8850fbc4e4be09
https://github.com/llvm/llvm-project/commit/77bc25485135b8a8cb2427910a8850fbc4e4be09
Author: John Brawn <john.brawn at arm.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
[AArch64] Fix build failure with -Werror (#144749)
PR#144387 caused buildbot failures with -Werror due to a comparison
between signed and unsigned types. Fix this with an explicit cast.
Commit: 298f1c276f4f9c18b25a79ffe6e619e89c5fbf7e
https://github.com/llvm/llvm-project/commit/298f1c276f4f9c18b25a79ffe6e619e89c5fbf7e
Author: Artem Belevich <tra at google.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/lib/Headers/__clang_cuda_intrinsics.h
Log Message:
-----------
Revert "Add missing intrinsics to cuda headers" (#144755)
Reverts llvm/llvm-project#143664
as it breaks CUDA compilation.
Commit: d9f7979a63ceac88727632ecfd522c073288b6c1
https://github.com/llvm/llvm-project/commit/d9f7979a63ceac88727632ecfd522c073288b6c1
Author: Justin King <jcking at google.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
A compiler-rt/test/sanitizer_common/TestCases/Linux/free_aligned_sized.c
A compiler-rt/test/sanitizer_common/TestCases/Linux/free_sized.c
Log Message:
-----------
sanitizer_common: add unsupported test for free_sized and free_aligned_sized from C23 (#144727)
Signed-off-by: Justin King <jcking at google.com>
Commit: 82acd8c377e9ed267195afdbde16eedebabc648c
https://github.com/llvm/llvm-project/commit/82acd8c377e9ed267195afdbde16eedebabc648c
Author: Lei Huang <lei at ca.ibm.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.h
M llvm/lib/Target/PowerPC/PPCInstrMMA.td
M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
M llvm/test/CodeGen/PowerPC/dmr-spill.ll
A llvm/test/CodeGen/PowerPC/dmrp-spill.ll
Log Message:
-----------
[PowerPC] Add code to spill and restore DMRp registers (#142443)
Commit: 835d3034fe96931cf907537b51b9cdd87b59d3ad
https://github.com/llvm/llvm-project/commit/835d3034fe96931cf907537b51b9cdd87b59d3ad
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
A llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmov-gpr32.ll
R llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmov.ll
Log Message:
-----------
[AArch64] improve zero-cycle regmov test (#143680)
- Add a `gpr32` suffix to test name to denote the specific register
class being checked
- Expand `-mtriple=arm64-apple-ios` to `-march=arm64` to broaden the
test context to the generic architecture, as the specific triple is not
required
- Port `bl` match to Linux too via the regex: `{{_?foo}}`
- Advance `-mcpu=cyclone` to the newer M series major `-mcpu=apple-m1`
- Use `-mcpu` so that `-mattr=-zcm` has a real effect
- Add a test that generic arm64 doesn't optimize for ZCM
- Distinguish 4 different assembly layouts: NOTCPU, CPU, NOTATTR, ATTR
- Fix broken test logic, for example: `; NOT: mov [[REG2:w[0-9]+]], w3`
matched `mov w1, w3` then `REG2` captured `w1` but then `; NOT: mov w1,
[[REG2]]` matched by prefix `mov, w1, w19` even though it should have
matched `mov w1, w1`. This change adds explicit matches for all of the
generated copies.
Commit: 6f4e4ea17745d1414519651eb4067ce14031ea93
https://github.com/llvm/llvm-project/commit/6f4e4ea17745d1414519651eb4067ce14031ea93
Author: sribee8 <sriya.pratipati at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M libc/src/__support/HashTable/CMakeLists.txt
M libc/src/__support/HashTable/randomness.h
M libc/src/__support/OSUtil/linux/CMakeLists.txt
A libc/src/__support/OSUtil/linux/getrandom.h
M libc/src/sys/random/linux/getrandom.cpp
Log Message:
-----------
[libc] Internal getrandom implementation (#144427)
Implemented an internal getrandom to avoid calls to the public one in
table.h
---------
Co-authored-by: Sriya Pratipati <sriyap at google.com>
Commit: dfe4d44d8de645d151d3483272c1c1f80c27ab31
https://github.com/llvm/llvm-project/commit/dfe4d44d8de645d151d3483272c1c1f80c27ab31
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
Log Message:
-----------
Revert "[VPlan] Remove unnecessary DomTreeUpdater flush (NFC)." (#144758)
This reverts commit 2e337349f436d75af112c081df5ec683871cbcc8.
Causes breakages internally, will post reproducer later.
Commit: 071a6feabd7aeec2c1239719f50f6912cf94d00a
https://github.com/llvm/llvm-project/commit/071a6feabd7aeec2c1239719f50f6912cf94d00a
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[TTI] Remove PPC hasActiveVectorLength impl, simplify interface (NFC). (#142310)
PPCTTIImpl defines hasActiveVectorLength and also getVPMemoryOpCost, but
they appear unused (i.e. no changes to tests).
Remove them, as they complicate the interface for hasActiveVectorLength.
This simplifies the only use in LV as now no placeholder values need to
be passed.
PR: https://github.com/llvm/llvm-project/pull/142310
Commit: 3f3526f36d23eac8d099e8e887a924c94000bbfa
https://github.com/llvm/llvm-project/commit/3f3526f36d23eac8d099e8e887a924c94000bbfa
Author: zhijian lin <zhijian at ca.ibm.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll
M llvm/test/CodeGen/PowerPC/all-atomics.ll
M llvm/test/CodeGen/PowerPC/loop-comment.ll
Log Message:
-----------
[NFC][PowerPC] pre-commit running the update_llc_test_checks.py for all-atomics.ll,loop-comment.ll etc (#144411)
Run the update_llc_test_checks.py for all-atomics.ll,loop-comment.ll
,PR35812-neg-cmpxchg.ll (Pre-commit patch for the
https://github.com/llvm/llvm-project/pull/144089)
Commit: 17f5b8b52a3552de1143efb42af6a94d47d8c7fd
https://github.com/llvm/llvm-project/commit/17f5b8b52a3552de1143efb42af6a94d47d8c7fd
Author: Andre Kuhlenschmidt <andre.kuhlenschmidt at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M flang/include/flang/Support/Fortran-features.h
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Support/Fortran-features.cpp
Log Message:
-----------
[flang][driver] add ability to look up feature flags without setting them (#144559)
This just adds some convenience methods to feature control and rewrites
old code in terms of those methods. Also cleans up some names that I
just realize were overloads of another method.
Commit: 8c3fbaf0ee7322e948403d2234a7230bd6137c98
https://github.com/llvm/llvm-project/commit/8c3fbaf0ee7322e948403d2234a7230bd6137c98
Author: Walter J.T.V <81811777+eZWALT at users.noreply.github.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/include/clang/AST/StmtOpenMP.h
M clang/lib/AST/StmtOpenMP.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
Log Message:
-----------
[Clang][OpenMP][LoopTransformations] Fix incorrect number of generated loops for Tile and Reverse directives (#140532)
This patch is closely related to #139293 and addresses an existing issue
in the loop transformation codebase. Specifically, it corrects the
handling of the `NumGeneratedLoops` variable in
`OMPLoopTransformationDirective` AST nodes and its inheritors (such as
OMPUnrollDirective, OMPTileDirective, etc.).
Previously, this variable was inaccurately set for certain
transformations like reverse or tile. While this did not lead to
functional bugs, since the value was only checked to determine whether
it was greater than zero or equal to zero, the inconsistency could
introduce problems when supporting more complex directives in the
future.
Commit: ab6beeca9ccc1968661eea27c1a55e8734f7437b
https://github.com/llvm/llvm-project/commit/ab6beeca9ccc1968661eea27c1a55e8734f7437b
Author: uthmanna <114300283+uthmanna at users.noreply.github.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
M llvm/tools/llvm-cov/CoverageExporterJson.cpp
Log Message:
-----------
[llvm-cov] Export decision coverage to output json (#144335)
This commit adds decision coverage counts derived from MC/DC test vector execution to the JSON output of llvm-cov, as
discussed here: [Missing Decision Coverage (DC) in output
json](https://discourse.llvm.org/t/missing-decision-coverage-dc-in-output-json/86783)
with @evodius96
---------
Co-authored-by: uthmanna <andre.uthmann at vector.com>
Commit: ca9a09dbe679dbdd4d47cb7894977e04c3bb914e
https://github.com/llvm/llvm-project/commit/ca9a09dbe679dbdd4d47cb7894977e04c3bb914e
Author: Kazu Hirata <kazu at google.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M libcxx/docs/ABIGuarantees.rst
Log Message:
-----------
[libc++] Fix a typo in documentation (#144763)
Commit: a94eb27a29ef3aee5ccafc1d7bebee1c8efbaf38
https://github.com/llvm/llvm-project/commit/a94eb27a29ef3aee5ccafc1d7bebee1c8efbaf38
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Analysis/HashRecognize.cpp
M llvm/test/Analysis/HashRecognize/cyclic-redundancy-check.ll
Log Message:
-----------
[HashRecognize] Fix big-endian CRC tables (#144754)
Big-endian CRC tables are incorrect due to the initial value of CRC in
genSarwateTable being hard-coded for CRC-8. 128 is the signed-min value
for CRC-8, but it should be generalized to APInt::getSignedMinValue. The
issue was found when writing CRC verification tests for llvm-test-suite.
Commit: f13b9e3643661ea2cda252c7e2c59ace036407c7
https://github.com/llvm/llvm-project/commit/f13b9e3643661ea2cda252c7e2c59ace036407c7
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/Analysis/HashRecognize.h
M llvm/lib/Analysis/HashRecognize.cpp
Log Message:
-----------
[HashRecognize] Don't const-qualify Values in result (#144752)
Const-qualifying Values in the analysis result makes them unusable with
IRBuilder. The issue was discovered when attempting to use the result of
the analysis for a transform.
Commit: 156a64c585faf0870936b62ec85fae19ceb9ad3f
https://github.com/llvm/llvm-project/commit/156a64c585faf0870936b62ec85fae19ceb9ad3f
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Analysis/HashRecognize.cpp
M llvm/test/Analysis/HashRecognize/cyclic-redundancy-check.ll
Log Message:
-----------
[HashRecognize] Tighten pre-conditions for analysis (#144757)
Exit early if the TC is not a byte-multiple, as optimization works by
dividing TC by 8. Also delay the SCEV TC query.
Commit: 88d250729eb00842a41c946632bcacf1af106f64
https://github.com/llvm/llvm-project/commit/88d250729eb00842a41c946632bcacf1af106f64
Author: Alan Phipps <a-phipps at ti.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
M llvm/tools/llvm-cov/CoverageExporterJson.cpp
Log Message:
-----------
Revert "[llvm-cov] Export decision coverage to output json" (#144783)
Reverts llvm/llvm-project#144335
Need to resolve test failures
Commit: fb0651959b1b6ae64f84cf5840adc95923af991f
https://github.com/llvm/llvm-project/commit/fb0651959b1b6ae64f84cf5840adc95923af991f
Author: Jameson Nash <vtjnash at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/trampoline.ll
Log Message:
-----------
[AArch64] fix trampoline implementation: actually use X15 (#143892)
A incorrect switch statement caused it to try to use X4 instead of X15
in #126743, which would have not worked.
Commit: c04fc5596ec8c197c75b92a086c31438bfb08faf
https://github.com/llvm/llvm-project/commit/c04fc5596ec8c197c75b92a086c31438bfb08faf
Author: Jameson Nash <vtjnash at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
M llvm/test/Transforms/MemCpyOpt/memcpy-memcpy-offset.ll
M llvm/test/Transforms/MemCpyOpt/variable-sized-memcpy-memcpy.ll
Log Message:
-----------
[MemCpyOpt] allow some undef contents overread in processMemCpyMemCpyDependence (#143745)
Allows memcpy to memcpy forwarding in cases where the second memcpy is
larger, but the overread is known to be undef, by shrinking the memcpy
size.
Refs https://github.com/llvm/llvm-project/pull/140954 which laid some of
the groundwork for this.
Commit: 67c52aacae2aa698eb1d31d81d2376bd77723d3a
https://github.com/llvm/llvm-project/commit/67c52aacae2aa698eb1d31d81d2376bd77723d3a
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/test/CIR/CodeGen/struct.c
Log Message:
-----------
[CIR] Upstream support for IncompleteArrayType (#144138)
This change adds the basic support for IncompleteArray
Issue https://github.com/llvm/llvm-project/issues/130197
Commit: d4b7c0d8b437f50ea254d814a1aeecf87a17be91
https://github.com/llvm/llvm-project/commit/d4b7c0d8b437f50ea254d814a1aeecf87a17be91
Author: Tobias Stadler <mail at stadler-tobias.de>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/Remarks/RemarkFormat.h
M llvm/include/llvm/Remarks/RemarkLinker.h
M llvm/lib/Remarks/RemarkFormat.cpp
M llvm/lib/Remarks/RemarkLinker.cpp
M llvm/lib/Remarks/RemarkParser.cpp
M llvm/lib/Remarks/RemarkSerializer.cpp
A llvm/test/tools/llvm-remarkutil/Inputs/broken-remark-magic.bitstream
M llvm/test/tools/llvm-remarkutil/annotation-count.test
A llvm/test/tools/llvm-remarkutil/broken-bitstream-remark-magic.test
M llvm/test/tools/llvm-remarkutil/empty-file.test
M llvm/test/tools/llvm-remarkutil/instruction-count.test
M llvm/test/tools/llvm-remarkutil/instruction-mix.test
M llvm/test/tools/llvm-remarkutil/size-diff/no-difference.test
M llvm/tools/llvm-remarkutil/RemarkUtilHelpers.h
M llvm/unittests/Remarks/RemarksLinkingTest.cpp
Log Message:
-----------
[Remarks] Auto-detect remark parser format (#144554)
Add remark format 'Auto', which performs automatic detection of the
remark format using the magic numbers at the beginning of the remarks
files.
The RemarkLinker already did something similar, so we streamlined this
and exposed this to llvm-remarkutil.
Commit: 22a69a266d8206b1585dd82d466cd96d01725a65
https://github.com/llvm/llvm-project/commit/22a69a266d8206b1585dd82d466cd96d01725a65
Author: Justin King <jcking at google.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M compiler-rt/lib/lsan/lsan_allocator.cpp
M compiler-rt/lib/lsan/lsan_allocator.h
M compiler-rt/lib/lsan/lsan_interceptors.cpp
M compiler-rt/lib/lsan/lsan_malloc_mac.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_malloc_mac.inc
M compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
M compiler-rt/test/sanitizer_common/TestCases/Linux/free_aligned_sized.c
M compiler-rt/test/sanitizer_common/TestCases/Linux/free_sized.c
Log Message:
-----------
lsan: Support free_sized and free_aligned_sized from C23 (#144604)
Adds support to LSan for `free_sized` and `free_aligned_sized` from C23.
Other sanitizers will be handled with their own separate PRs.
For https://github.com/llvm/llvm-project/issues/144435
This is attempt number 2.
Signed-off-by: Justin King <jcking at google.com>
Commit: 23b8f11b27f1345cfdd9d03c9ebaccaf81897764
https://github.com/llvm/llvm-project/commit/23b8f11b27f1345cfdd9d03c9ebaccaf81897764
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Remove redundant VPWidenRecipe constructors (NFC)
Since the removal of VPWidenEVLRecipe, the constructors taking a
VPDefOpcode are not needed any more. Remove them.
Commit: a630ca6f6c4727d852d60076d1179c3e9830ca2f
https://github.com/llvm/llvm-project/commit/a630ca6f6c4727d852d60076d1179c3e9830ca2f
Author: Chelsea Cassanova <chelsea_cassanova at apple.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M lldb/include/lldb/Core/Debugger.h
M lldb/source/Breakpoint/Breakpoint.cpp
M lldb/source/Core/CoreProperties.td
M lldb/source/Core/Debugger.cpp
A lldb/test/API/terminal/TestDisabledBreakpoints.py
Log Message:
-----------
[lldb][breakpoint] Grey out disabled breakpoints (#91404)
This commit adds colour settings to the list of breakpoints in order to
grey out breakpoints that have been disabled.
Commit: a88e655809655eec8fa85366318fb3c4a0baa113
https://github.com/llvm/llvm-project/commit/a88e655809655eec8fa85366318fb3c4a0baa113
Author: Andrew Rogers <andrurogerz at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Support/BLAKE3/CMakeLists.txt
Log Message:
-----------
[llvm] build Blake3 source with LLVM_EXPORTS defined (#144753)
## Purpose
This patch ensures that the BLAKE3 implementation in the LLVM Support
library exports its public interface with `__declspec(dllexport)` when
building LLVM as a Windows DLL.
## Background
The effort to support building LLVM as a Windows DLL is tracked in
#109483. Additional context is provided in [this
discourse](https://discourse.llvm.org/t/psa-annotating-llvm-public-interface/85307).
## Overview
Replicate [this
logic](https://github.com/llvm/llvm-project/blob/main/llvm/cmake/modules/AddLLVM.cmake#L662-L664)
from `llvm_add_library()` for the `LLVMSupportBlake3` target. Without
this change, the `llvm_blake_` functions will only be annotated with
`__declspec(dllimport)` when building LLVM as a Windows DLL which leads
to inconsistent DLL linkage warnings from MSVC and `clang-cl`.
Commit: 96bbe472ef01e5f34bfeabedceea397889ff1119
https://github.com/llvm/llvm-project/commit/96bbe472ef01e5f34bfeabedceea397889ff1119
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
M mlir/test/CMakeLists.txt
M mlir/test/Target/SPIRV/constant.mlir
R mlir/test/Target/SPIRV/lit.local.cfg
M mlir/test/lit.cfg.py
M mlir/test/lit.site.cfg.py.in
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
Revert "[mlir][spirv] Fix int type declaration duplication when serializing" and follow up commits (#144773)
This reverts the following PRs:
* https://github.com/llvm/llvm-project/pull/143108
* https://github.com/llvm/llvm-project/pull/144538
* https://github.com/llvm/llvm-project/pull/144685
Reverting because this disabled tests when building without the llvm
spirv backend enabled.
Commit: b85e92990fdec32ec7512dec7bd36d945f8e0144
https://github.com/llvm/llvm-project/commit/b85e92990fdec32ec7512dec7bd36d945f8e0144
Author: Alexey Karyakin <akaryaki at quicinc.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/BinaryFormat/ELF.h
Log Message:
-----------
Hexagon v87 v89 elf flags (#144584)
Commit: 7aecd7ecacb4b305b94149f3cfcef306a9da6beb
https://github.com/llvm/llvm-project/commit/7aecd7ecacb4b305b94149f3cfcef306a9da6beb
Author: Diego Caballero <dieg0ca6aller0 at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/IR/OpBase.td
M mlir/lib/TableGen/Operator.cpp
M mlir/test/Dialect/Vector/invalid.mlir
M mlir/test/Dialect/Vector/ops.mlir
M mlir/tools/mlir-tblgen/OpFormatGen.cpp
Log Message:
-----------
[mlir][Vector] Add `vector.to_elements` op (#141457)
This PR introduces the `vector.to_elements` op, which decomposes a
vector into its scalar elements. This operation is symmetrical to the
existing `vector.from_elements`.
Examples:
```
// Decompose a 0-D vector.
%0 = vector.to_elements %v0 : vector<f32>
// %0 = %v0[0]
// Decompose a 1-D vector.
%0:2 = vector.to_elements %v1 : vector<2xf32>
// %0#0 = %v1[0]
// %0#1 = %v1[1]
// Decompose a 2-D.
%0:6 = vector.to_elements %v2 : vector<2x3xf32>
// %0#0 = %v2[0, 0]
// %0#1 = %v2[0, 1]
// %0#2 = %v2[0, 2]
// %0#3 = %v2[1, 0]
// %0#4 = %v2[1, 1]
// %0#5 = %v2[1, 2]
```
This op is aimed at reducing code size when modeling "structured" vector
extractions and simplifying canonicalizations of large sequences of
`vector.extract` and `vector.insert` ops into `vector.shuffle` and other
sophisticated ops that can re-arrange vector elements.
Commit: 86d1d6b2c0c1f03e82cb8e360f2672c6f0ea39d5
https://github.com/llvm/llvm-project/commit/86d1d6b2c0c1f03e82cb8e360f2672c6f0ea39d5
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/TargetInfo.cpp
M clang/lib/CodeGen/TargetInfo.h
M clang/lib/CodeGen/Targets/AMDGPU.cpp
M clang/lib/CodeGen/Targets/NVPTX.cpp
M clang/lib/CodeGen/Targets/SPIR.cpp
Log Message:
-----------
[clang] Use TargetInfo to determine device kernel calling convention (#144728)
We should abstract this logic away to `TargetInfo`. See
https://github.com/llvm/llvm-project/pull/137882 for more information.
---------
Signed-off-by: Sarnie, Nick <nick.sarnie at intel.com>
Commit: 03bdc0a1f68adcddef80a4e7931dbfae914e5652
https://github.com/llvm/llvm-project/commit/03bdc0a1f68adcddef80a4e7931dbfae914e5652
Author: Chelsea Cassanova <chelsea_cassanova at apple.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M lldb/source/Target/Target.cpp
M lldb/test/API/functionalities/progress_reporting/TestProgressReporting.py
Log Message:
-----------
[lldb][target] Add progress report for wait-attaching to process (#144768)
This commit adds a progress report when wait-attaching to a process as
well as a test for this.
Commit: 4dca4459a328b8d589d81cd1f203b798c36ebf35
https://github.com/llvm/llvm-project/commit/4dca4459a328b8d589d81cd1f203b798c36ebf35
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp
M clang/lib/CIR/CodeGen/CIRGenValue.h
M clang/test/CIR/CodeGen/complex.cpp
Log Message:
-----------
[CIR] Upstream ComplexType builtin_complex (#144225)
This change adds support for builtin_complex
https://github.com/llvm/llvm-project/issues/141365
Commit: ac37a0df949afc31d12de75f85306db32dd50713
https://github.com/llvm/llvm-project/commit/ac37a0df949afc31d12de75f85306db32dd50713
Author: Diego Caballero <dieg0ca6aller0 at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/include/mlir/IR/OpBase.td
Log Message:
-----------
[mlir] Fix integer comparison warning (#144794)
Introduced by https://github.com/llvm/llvm-project/pull/141457
Commit: d10079e305acae58b44dc773cb94f7127de197ef
https://github.com/llvm/llvm-project/commit/d10079e305acae58b44dc773cb94f7127de197ef
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
Log Message:
-----------
[RISCV] Reduce the VL of both operands in VMERGE_VVM (#144759)
The `tryToReduceVL` function in RISCVVectorPeephole currently only
reduces the VL of the instruction that defines the true operand in
VMERGE_VVM. We should be able to reduce VL of both operands. This patch
generalizes this function to support multiple operands from a single
instruction.
Commit: c4d7ea8049688a1d6d6d93129893fd1700a9f7e5
https://github.com/llvm/llvm-project/commit/c4d7ea8049688a1d6d6d93129893fd1700a9f7e5
Author: Javier Lopez-Gomez <javier.lopez.gomez at proton.me>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/DebugInfo/LogicalView/Core/LVElement.h
M llvm/include/llvm/DebugInfo/LogicalView/Core/LVScope.h
M llvm/include/llvm/DebugInfo/LogicalView/Core/LVSupport.h
Log Message:
-----------
[llvm-debuginfo-analyzer] Apply various memory savings in Core/LVxxx base classes (#144399)
This small changelist reduces memory footprint of instances of the Core
classes. Specifically,
- For `LVProperties`, use underlying type of `uint32_t` if there are at
most 32 properties to keep track of. Otherwise, fallback to the generic
`std::bitset<N>`.
The use of `llvm::SmallBitVector` is disregarded in this case, as the
upper bound on the size of the bitset can be determined statically (no
heap alloc ever needed).
- Reorder members in `LVElement` s.t. padding between members is
reduced.
- `LVScopeCompileUnit`: fix a couple of members which should be `static
constexpr` instead.
Commit: 51aa6a4993ea18c968a087352d1cf569c840c41f
https://github.com/llvm/llvm-project/commit/51aa6a4993ea18c968a087352d1cf569c840c41f
Author: Ebuka Ezike <yerimyah1 at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M lldb/test/API/tools/lldb-dap/memory/TestDAP_memory.py
M lldb/tools/lldb-dap/Handler/ReadMemoryRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
M lldb/unittests/DAP/ProtocolTypesTest.cpp
Log Message:
-----------
[lldb-dap] Use protocol types for ReadMemory request (#144552)
Read memory from process instead of target.
Commit: 118bfcda46c17349575217bc901e8e5942521955
https://github.com/llvm/llvm-project/commit/118bfcda46c17349575217bc901e8e5942521955
Author: Jianhui Li <jian.hui.li at intel.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
M mlir/test/Dialect/XeGPU/xegpu-blocking.mlir
M mlir/test/lib/Dialect/XeGPU/TestXeGPUTransforms.cpp
Log Message:
-----------
[MLIR][XEGPU] Add blocking support for scatter ops (#144766)
Add blocking support for scatter ops: Create_tdesc, update, prefetch,
load and store. It also enables the load/store with chunk size.
Commit: 7b6963ea672f8fedbbaefd15eaca943495709d37
https://github.com/llvm/llvm-project/commit/7b6963ea672f8fedbbaefd15eaca943495709d37
Author: Muhammad Omair Javaid <omair.javaid at linaro.org>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M compiler-rt/lib/fuzzer/tests/CMakeLists.txt
Log Message:
-----------
[compiler-rt] [Fuzzer] Fix tests linking buildbot failure (#144495)
Fix for #144495 by 6f4add3 broke sanitizer-aarch64-linux buildbot.
compiler-rt/lib/fuzzer/tests build failed because the linker was
looking gcc_s without '-l' appended.
The CMake script was adding the library name without the required
'-l' prefix. This patch adds the -l prefix changing gcc_s to -lgcc_s
and gcc to -lgcc.
https://lab.llvm.org/buildbot/#/builders/51/builds/18170
Commit: 00ae89a1cbece94412cf832e47fdf449a611ad24
https://github.com/llvm/llvm-project/commit/00ae89a1cbece94412cf832e47fdf449a611ad24
Author: zGoldthorpe <Zach.Goldthorpe at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/Transforms/IPO/Attributor.h
M llvm/lib/Transforms/IPO/Attributor.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
R llvm/test/Transforms/Attributor/AMDGPU/tag-invariant-loads.ll
M llvm/test/Transforms/Attributor/dereferenceable-1.ll
M llvm/test/Transforms/Attributor/value-simplify-local-remote.ll
Log Message:
-----------
Revert "[IPO] Added attributor for identifying invariant loads" (#144808)
Reverts llvm/llvm-project#141800
The implementation critically misunderstands the `AAMemoryBehavior`
attributor, which it relies on heavily.
@shiltian, since I do not have commit permissions.
Commit: e0933ab5ae4856c4aa188a5ea16716b3a8d0840b
https://github.com/llvm/llvm-project/commit/e0933ab5ae4856c4aa188a5ea16716b3a8d0840b
Author: Chelsea Cassanova <chelsea_cassanova at apple.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M lldb/source/Target/Target.cpp
M lldb/test/API/functionalities/progress_reporting/TestProgressReporting.py
Log Message:
-----------
Revert "[lldb][target] Add progress report for wait-attaching to process" (#144810)
This is breaking TestCreateAfterAttach.py on Ubuntu:
```
======================================================================
FAIL: test_create_after_attach_dwo (TestCreateAfterAttach.CreateAfterAttachTestCase.test_create_after_attach_dwo)
Test thread creation after process attach.
----------------------------------------------------------------------
Traceback (most recent call last):
File "/home/buildbot/worker/as-builder-9/lldb-remote-linux-ubuntu/llvm-project/lldb/packages/Python/lldbsuite/test/lldbtest.py", line 1804, in test_method
return attrvalue(self)
^^^^^^^^^^^^^^^
File "/home/buildbot/worker/as-builder-9/lldb-remote-linux-ubuntu/llvm-project/lldb/packages/Python/lldbsuite/test/decorators.py", line 149, in wrapper
return func(*args, **kwargs)
^^^^^^^^^^^^^^^^^^^^^
File "/home/buildbot/worker/as-builder-9/lldb-remote-linux-ubuntu/llvm-project/lldb/test/API/functionalities/thread/create_after_attach/TestCreateAfterAttach.py", line 36, in test_create_after_attach
self.runCmd("process attach -p " + str(pid))
File "/home/buildbot/worker/as-builder-9/lldb-remote-linux-ubuntu/llvm-project/lldb/packages/Python/lldbsuite/test/lldbtest.py", line 1005, in runCmd
self.assertTrue(self.res.Succeeded(), msg + output)
AssertionError: False is not true : Command 'process attach -p 1474309' did not return successfully
Error output:
error: attach failed: lost connection
```
on the buildbots for lldb-remote-linux-ubuntu, lldb-arm-ubuntu,
lldb-aarch64-ubuntu, lldb-arm-ubuntu.
Commit: 780c0ef7fb97027aa21c2ee6b02282693f908a20
https://github.com/llvm/llvm-project/commit/780c0ef7fb97027aa21c2ee6b02282693f908a20
Author: Andrew Rogers <andrurogerz at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/tools/llvm-jitlink/llvm-jitlink-executor/CMakeLists.txt
Log Message:
-----------
[llvm] explicitly link llvm-jitlink-executor with ExecutionEngine (#144778)
## Overview
Explicitly link `llvm-jitlink-executor` with `ExecutionEngine` to avoid
link failures when building LLVM as a Windows DLL. This link dependency
should probably have always been declared here, but didn't matter when
building against an LLVM static library because it was (presumably)
picked up as a transitive dependency.
This change is required to enable the Windows DLL build because
`llvm-jitlink-executor` is declared using `add_llvm_utility` which
invokes `add_llvm_executable` with
[`DISABLE_LLVM_LINK_LLVM_DYLIB`](https://github.com/llvm/llvm-project/blob/main/llvm/cmake/modules/AddLLVM.cmake#L500-L502)
so it links statically against its dependencies instead of against the
main LLVM library.
## Background
The effort to support building LLVM as a Windows DLL is tracked in
#109483. Additional context is provided in [this
discourse](https://discourse.llvm.org/t/psa-annotating-llvm-public-interface/85307).
Commit: bb1f5c3189c4d8d30e3b1273e0b774a7ccdbd86a
https://github.com/llvm/llvm-project/commit/bb1f5c3189c4d8d30e3b1273e0b774a7ccdbd86a
Author: Guy David <49722543+guy-david at users.noreply.github.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/test/CodeGen/AArch64/min-jump-table.ll
Log Message:
-----------
[AArch64] Lower jump table cases threshold to 10 (#143632)
Previous stabs at this setting
(https://github.com/llvm/llvm-project/pull/71166) hypertuned it for
SPEC2017, but Clang's own compilation can benefit from a slightly lower
threshold, yielding a 0.3% improvement in compile time, while still not
regressing SPEC.
Most notable beneficiaries of this change are:
- `llvm::Instruction::getNumSuccessors` (11 cases)
- `llvm::Instruction::getSuccessor` (11 cases)
Test Suite with a bootstrapped build:
```
Tests: 4316
Metric: compile_time
Program compile_time
lhs rhs diff
SingleSour...ce/UnitTests/SignlessTypes/div 0.02 0.02 3.0%
SingleSour.../UnitTests/SignlessTypes/cast2 0.02 0.02 2.8%
SingleSource/Benchmarks/Misc/flops-4 0.02 0.02 1.9%
SingleSour...ebra/solvers/cholesky/cholesky 0.05 0.05 1.8%
SingleSour...tTests/2020-01-06-coverage-006 0.02 0.02 1.7%
SingleSour...ce/Benchmarks/Stanford/FloatMM 0.03 0.03 1.7%
SingleSour...9-04-16-BitfieldInitialization 0.02 0.02 1.7%
SingleSour...nitTests/2003-07-08-BitOpsTest 0.02 0.02 1.7%
MultiSourc...marks/Prolangs-C++/vcirc/vcirc 0.02 0.02 1.6%
MultiSourc...Prolangs-C/fixoutput/fixoutput 0.05 0.05 1.5%
SingleSour...h/stencils/jacobi-1d/jacobi-1d 0.04 0.04 1.4%
MultiSourc...rks/Prolangs-C++/office/office 0.28 0.28 1.4%
SingleSour...arks/Adobe-C++/functionobjects 0.39 0.40 1.3%
SingleSour...Tests/2003-10-29-ScalarReplBug 0.02 0.02 1.2%
SingleSour...arks/Adobe-C++/stepanov_vector 0.41 0.42 1.2%
Geomean difference -0.3%
compile_time
l/r lhs rhs diff
count 4316.000000 4316.000000 469.000000
mean 0.057747 0.057595 -0.003034
std 0.544528 0.543139 0.007625
min 0.000000 0.000000 -0.035294
25% 0.000000 0.000000 -0.007006
50% 0.000000 0.000000 -0.003257
75% 0.000000 0.000000 0.000000
max 18.295300 18.252500 0.030151
```
Commit: 5f69d680e2cc94dcb30a7f29e8144725530a6da4
https://github.com/llvm/llvm-project/commit/5f69d680e2cc94dcb30a7f29e8144725530a6da4
Author: Steven Perron <stevenperron at google.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaHLSL.cpp
R clang/test/AST/HLSL/vk.spec-constant.usage.hlsl
A clang/test/CodeGenHLSL/inline-spirv/SpirvType.alignment.hlsl
A clang/test/CodeGenHLSL/inline-spirv/SpirvType.hlsl
R clang/test/CodeGenHLSL/vk-features/SpirvType.alignment.hlsl
R clang/test/CodeGenHLSL/vk-features/SpirvType.hlsl
R clang/test/CodeGenHLSL/vk-features/vk.spec-constant.hlsl
R clang/test/SemaHLSL/vk.spec-constant.error.hlsl
Log Message:
-----------
Revert "[HLSL][SPIRV] Add vk::constant_id attribute." (#144812)
Reverts llvm/llvm-project#143544
Commit: d265105b8f50718a684d792d3ca957231d668533
https://github.com/llvm/llvm-project/commit/d265105b8f50718a684d792d3ca957231d668533
Author: David Justo <david.justo.1996 at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M compiler-rt/test/fuzzer/uncaught-exception.test
Log Message:
-----------
Augment `uncaught-exception.test` fuzzer test to be msvc-compatible (#125924)
Today, the `uncaught-exception.test` fuzzer test checks for the string
"libFuzzer: deadly signal" in the program output as the result of an
uncaught exception.
Although this is correct for `clang`, `msvc` reports a different error
message: "libFuzzer: uncaught C++ exception". Since `msvc` reuses the
`libFuzzer` infrastructure for ASan regression testing, it would help us
greatly if the test handled the `msvc` divergence more gracefully.
**This PR:** augments this test so check for a different string (namely
"libFuzzer: uncaught C++ exception") if the compiler target matches the
`msvc` naming scheme.
I understand if this is outside the scope of support for LLVM as well,
and I'm also open for different approaches here. Thanks!
Commit: bc8908a4e93b0641e1c17f408885c8aebb308bbe
https://github.com/llvm/llvm-project/commit/bc8908a4e93b0641e1c17f408885c8aebb308bbe
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Target/ARM/ARMISelLowering.h
Log Message:
-----------
ARM: Move declaration of supportSplitCSR to be public (#144679)
This is an implementation of a public method from the base
class, so it should also be public. Avoids unrelated diff
in a future patch.
Commit: 874a02f05b6ebb4b5dbe0ab09beb9c3d5b36e237
https://github.com/llvm/llvm-project/commit/874a02f05b6ebb4b5dbe0ab09beb9c3d5b36e237
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMAsmPrinter.h
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
Log Message:
-----------
ARM: Move ABI helpers from Subtarget to TargetMachine (#144680)
These are module level concepts, and attaching them to the
function level subtarget is confusing. Similarly these other
helpers that only operate on the triple should also be removed
from the subtarget.
Commit: 6e5ee4aa98f1dc16e6a75a7fd298a59f1edd1c6e
https://github.com/llvm/llvm-project/commit/6e5ee4aa98f1dc16e6a75a7fd298a59f1edd1c6e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVCallingConv.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/test/CodeGen/RISCV/interrupt-attr.ll
A llvm/test/CodeGen/RISCV/rvv/interrupt-attr-nocall.ll
Log Message:
-----------
[RISCV] Save vector registers in interrupt handler. (#143808)
Corresponding gcc bug report
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110665
The generated code is pretty awful.
Commit: 2bcdfa198aa511479c46144c5cf95c7c685384ef
https://github.com/llvm/llvm-project/commit/2bcdfa198aa511479c46144c5cf95c7c685384ef
Author: Sirui Mu <msrlancern at gmail.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/Interfaces/CIROpInterfaces.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenCall.h
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
M clang/test/CIR/CodeGen/call.c
M clang/test/CIR/IR/call.cir
Log Message:
-----------
[CIR] Add side effect attribute to call operations (#144201)
This patch adds `side_effect` attribute to `cir.call` operation.
Other function call attributes will be added in later patches.
Commit: faf9295f4e3a23a972d29e2be85052beef409d08
https://github.com/llvm/llvm-project/commit/faf9295f4e3a23a972d29e2be85052beef409d08
Author: MingYan <99472920+NexMing at users.noreply.github.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
Log Message:
-----------
[RISCV] Fix a bug where AVL is the last MI in MBB. (#144668)
When `AVL` is the last MI, `std::next(II)` equals `MBB.end()`, and
calling `II->getParent()` at that point will cause an error.
---------
Co-authored-by: yanming <ming.yan at terapines.com>
Commit: bfee625821c07d9a05b48e4a8b0f3d73c1233107
https://github.com/llvm/llvm-project/commit/bfee625821c07d9a05b48e4a8b0f3d73c1233107
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/IR/Verifier.cpp
A llvm/test/Verifier/NVPTX/fence-proxy.tensormap.ll
M llvm/test/Verifier/NVPTX/setmaxnreg.ll
Log Message:
-----------
[NVPTX] Attach Range attr to setmaxnreg and fence intrinsics (#144120)
This patch attaches the range attribute to the setmaxnreg
and fence.proxy.tensormap.* intrinsics. The range checks
are now handled generically in the Verifier. So, this patch
removes the per-intrinsic error-handling for range-checks
from the Verifier.
This patch also adds more coverage tests for these cases.
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: 5875fafdc547889fb089c943a881a9ab6d8a23c0
https://github.com/llvm/llvm-project/commit/5875fafdc547889fb089c943a881a9ab6d8a23c0
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/test/Preprocessor/predefined-arch-macros.c
M llvm/lib/Target/X86/X86.td
M llvm/lib/TargetParser/X86TargetParser.cpp
Log Message:
-----------
[X86] Remove CLDEMOTE from Alderlake and later hybrid processors (#144662)
SDM doesn't list any hybrid processors in this feature. Besides,
physical machine also reports not supported.
Commit: 351303c28e8feb85c93d8e9480f534653b032735
https://github.com/llvm/llvm-project/commit/351303c28e8feb85c93d8e9480f534653b032735
Author: Han-Chung Wang <hanhan0912 at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td
M mlir/include/mlir/IR/BuiltinOps.td
Log Message:
-----------
[mlir][docs] Fix broken links to Traits documentation. (#144820)
Commit: 7b989ade35a43357f9152198ee2c76899df9a56d
https://github.com/llvm/llvm-project/commit/7b989ade35a43357f9152198ee2c76899df9a56d
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M lldb/examples/python/crashlog.py
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/altered_threadState.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/json.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/no_threadState.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/skipped_status_interactive_crashlog.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/text.test
Log Message:
-----------
[lldb/crashlog] Make interactive mode the new default (#144839)
This patch makes interactive mode as the default when using the crashlog
command. It replaces the existing `-i|--interactive` flag with a new
`-m|--mode` option, that can either be `interactive` or `batch`.
By default, when the option is not explicitely set by the user, the
interactive mode is selected, however, lldb will fallback to batch mode
if the command interpreter is not interactive or if stdout is not a tty.
This also adds some railguards to prevent users from using interactive
only options with the batch mode and updates the tests accordingly.
rdar://97801509
Differential Revision: https://reviews.llvm.org/D141658
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: 590066bee70db37636311881c5b232464d6d4aec
https://github.com/llvm/llvm-project/commit/590066bee70db37636311881c5b232464d6d4aec
Author: Rajat Bajpai <rbajpai at nvidia.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/docs/NVPTXUsage.rst
M llvm/lib/Target/NVPTX/NVPTX.td
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/test/CodeGen/NVPTX/sm-version.ll
Log Message:
-----------
[NVPTX] Add family-specific architectures support (#141899)
This change adds family-specific architecture variants support added in [PTX ISA
8.8](https://docs.nvidia.com/cuda/parallel-thread-execution/#ptx-isa-version-8-8).
These architecture variants have "f" suffix. For example, sm_100f.
This change doesn't promote existing features to family-specific
architecture.
Commit: 03461c9c6e21e43a6e1c699bfb254ddb3d575c93
https://github.com/llvm/llvm-project/commit/03461c9c6e21e43a6e1c699bfb254ddb3d575c93
Author: Hsiangkai Wang <hsiangkai.wang at arm.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/lib/Conversion/GPUToSPIRV/GPUToSPIRV.cpp
M mlir/test/Conversion/GPUToSPIRV/shuffle.mlir
Log Message:
-----------
[mlir][gpu][spirv] Remove rotation semantics of gpu.shuffle up/down (#139105)
>From the description of gpu.shuffle operation, shuffle up/down rotates
values in the subgroup because it applies modulo on the shifted value to
calculate the result lane ID. It is inconsistent with the definition of
SPIR-V shuffle up/down and NVVM data movement definitions within
subgroup.
In NVVM, it says
"If the computed source lane index j is in range, the returned i32 value
will be the value of %a from lane j; otherwise, it will be the the value
of %a from the current thread."
It will keep the original value if the result land ID is out of range.
In SPIR-V OpGroupNonUniformShuffleUp and OpGroupNonUniformShuffleDown,
it says
"The resulting value is undefined if Delta is greater than the current
invocation’s id within the scope or if the identified invocation is not
in scope restricted tangle."
It's an undefined value if the result land ID is out of range.
Anyway, there is no circular movement in shuffle up/down from these 2
specifications. This patch removes the circular movement in gpu.shuffle
up/down and lower gpu.shuffle up/down to SPIR-V
OpGroupNonUniformShuffleUp and OpGroupNonUniformShuffleDown directly.
Reference:
https://docs.nvidia.com/cuda/archive/12.2.1/nvvm-ir-spec/index.html#data-movement
https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#OpGroupNonUniformShuffleUp
https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#OpGroupNonUniformShuffleDown
Commit: 2c2ad9a096e78e9129f8cb2d4ee260eb7e67473f
https://github.com/llvm/llvm-project/commit/2c2ad9a096e78e9129f8cb2d4ee260eb7e67473f
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/AST/StmtProfile.cpp
M clang/test/SemaCXX/exception-spec.cpp
M clang/test/SemaTemplate/concepts-out-of-line-def.cpp
Log Message:
-----------
Reapply "[Clang] Profile singly-resolved UnresolvedLookupExpr with the declaration" (#140680)
For a dependent variable template specialization, we don't build a
dependent Decl node or a DeclRefExpr to represent it. Instead, we
preserve the UnresolvedLookupExpr until instantiation.
However, this approach isn't ideal for constraint normalization. We
consider the qualifier during profiling, but since that's based on the
written code, it can introduce confusing differences, even when the
expressions resolve to the same declaration.
This change profiles the underlying VarTemplateDecl if
UnresolvedLookupExpr is used to model a dependent use of it.
Fixes https://github.com/llvm/llvm-project/issues/139476
Commit: 9ee55e717308757b580dff182fc23b40d1c18a56
https://github.com/llvm/llvm-project/commit/9ee55e717308757b580dff182fc23b40d1c18a56
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/lib/CIR/Dialect/Transforms/CIRSimplify.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
A clang/test/CIR/Transforms/vector-splat.cir
Log Message:
-----------
[CIR] Implement folder for VecSplatOp (#143771)
This change adds a folder for the VecSplatOp
Issue https://github.com/llvm/llvm-project/issues/136487
Commit: 408e55098d7d8f7064d7a288b5e3fe6fdbbc2ad4
https://github.com/llvm/llvm-project/commit/408e55098d7d8f7064d7a288b5e3fe6fdbbc2ad4
Author: quic_hchandel <quic_hchandel at quicinc.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/test/MC/RISCV/xqciac-valid.s
M llvm/utils/TableGen/CompressInstEmitter.cpp
Log Message:
-----------
[RISCV] Add support for handling one tied operand in the source instruction for compress patterns (#143660)
This update enables compress patterns to handle one tied operand in
source instructions, which was previously unsupported. Qualcomm's uC
extension Xqci includes several instructions with tied operands that can
be compressed into smaller forms. This change adds the necessary support
to enable such compression. Additionally, a compress pattern for the
qc.muliadd instruction has been implemented.
Commit: 3e795c60c73e990fbbf254715cb47855c32bcfae
https://github.com/llvm/llvm-project/commit/3e795c60c73e990fbbf254715cb47855c32bcfae
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M lldb/test/API/python_api/watchpoint/watchlocation/TestTargetWatchAddress.py
Log Message:
-----------
[lldb] Disable TestTargetWatchAddress on Windows x86_64 (#144779)
See #144777 for details.
Commit: a9a71b6d311892d6add6aab3790b20fe945cca38
https://github.com/llvm/llvm-project/commit/a9a71b6d311892d6add6aab3790b20fe945cca38
Author: S. B. Tam <cpplearner at outlook.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M libcxx/test/std/utilities/format/format.functions/escaped_output.unicode.pass.cpp
M libcxx/test/std/utilities/format/format.functions/fill.unicode.pass.cpp
Log Message:
-----------
[libc++][test] Don't pass ill-formed UTF-8 to MAKE_STRING_VIEW (#136403)
Commit: 50a7511138a42d2c7a69b68237ce88cc027b91bc
https://github.com/llvm/llvm-project/commit/50a7511138a42d2c7a69b68237ce88cc027b91bc
Author: Paschalis Mpeis <paschalis.mpeis at arm.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M bolt/test/AArch64/r_aarch64_prelxx.s
Log Message:
-----------
[BOLT][AArch64] Fix PREL Relocs on RHEL8 (#144505)
Commit: e73bff89ef8e3c8cdd8895cdc3d021fc4dcabd76
https://github.com/llvm/llvm-project/commit/e73bff89ef8e3c8cdd8895cdc3d021fc4dcabd76
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
Log Message:
-----------
[AMDGPU] New RegBankSelect: Handle all 32/64 bit pointer types for B32/B64 rule (#142560)
The previous system explicitly enumerated the types. P0 was missing and thus we couldn't handle a select of P0s for example.
Generalize the logic to simply check the width of the pointer for 32/64 bit pointers, this should handle all common address spaces
Commit: db8e6fc64534e986f5bf96cceaa76cc5007ac1c7
https://github.com/llvm/llvm-project/commit/db8e6fc64534e986f5bf96cceaa76cc5007ac1c7
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
Log Message:
-----------
[AMDGPU] New RegBanKSelect: Add S128 types (#142601)
Commit: 26d4b3cb4ca2f882384d940f3dad28f8d79451eb
https://github.com/llvm/llvm-project/commit/26d4b3cb4ca2f882384d940f3dad28f8d79451eb
Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/test/CodeGen/RISCV/xqcibm-extract.ll
Log Message:
-----------
[RISCV] Don't prefer QC_EXT for SEXT_INREG patterns when Zbb is enabled (#144837)
`Zbb` has the `sext.b` and `sext.h` instructions that are compressible.
Commit: 7ceea22a7adad5d21328839facbc6a6d0151e056
https://github.com/llvm/llvm-project/commit/7ceea22a7adad5d21328839facbc6a6d0151e056
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
Log Message:
-----------
[AMDGPU] New RegBankSelect: Add Ptr32/Ptr64/Ptr128 (#142602)
There's quite a few opcodes that do not care about the exact AS of the pointer, just its size.
Adding generic types for these will help reduce duplication in the rule definitions.
I also moved the usual B types to use the new `isAnyPtr` helper I added to make sure they're supersets of the `Ptr` cases
Commit: 52ff58c3300338876ae63126ce0d33331000f1ba
https://github.com/llvm/llvm-project/commit/52ff58c3300338876ae63126ce0d33331000f1ba
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/lib/Headers/CMakeLists.txt
R clang/lib/Headers/cuda_wrappers/bits/c++config.h
Log Message:
-----------
Revert "[CUDA][HIP] Add a __device__ version of std::__glibcxx_assert_fail()" (#144850)
Reverts llvm/llvm-project#136133
Commit: 650b451d0065c8ea6a1f87e7fdc6d07648729549
https://github.com/llvm/llvm-project/commit/650b451d0065c8ea6a1f87e7fdc6d07648729549
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M libcxx/include/__memory/pointer_traits.h
Log Message:
-----------
[libc++] Simplify the implementation of pointer_traits a bit (#142260)
Commit: 1ab0e7dd60e26ac7c7fc64a273485522f5c5ba02
https://github.com/llvm/llvm-project/commit/1ab0e7dd60e26ac7c7fc64a273485522f5c5ba02
Author: Jiachen (Yangyang) Wang <130888597+WanderingAura at users.noreply.github.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll
M llvm/test/Transforms/LICM/call-hoisting.ll
Log Message:
-----------
[LICM] Hoisting writeonly calls (#143799)
Adds support for hoisting `writeonly` calls in LICM.
This patch adds a missing optimization that allows hoisting of
`writeonly` function calls out of loops when it is safe to do so.
Previously, such calls were conservatively retained inside the loop
body, and the redundant calls were only reduced through unrolling,
relying on target-dependent heuristics.
Closes #143267
Testing:
- Modified previously negative tests for hoisting writeonly calls to be
instead positive
- Added test cases for hoisting of two writeonly calls where the
pointers do/do not alias
- Added a test case for not argmemonly writeonly calls.
Commit: 0e1aab1ec833d7f8e9897b0940c634385036fdee
https://github.com/llvm/llvm-project/commit/0e1aab1ec833d7f8e9897b0940c634385036fdee
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
Log Message:
-----------
[AMDGPU] Improve test coverage for G_INTTOPTR and G_PTRTOINT (#142603)
Test P0 through P6 + P8 for both S/VGPRs.
Commit: 62fe5e428acc2c5ef9b144c5737d55b17b55feac
https://github.com/llvm/llvm-project/commit/62fe5e428acc2c5ef9b144c5737d55b17b55feac
Author: Sameer Sahasrabuddhe <sameer.sahasrabuddhe at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Log Message:
-----------
[NFC][AMDGPU] print more info when debugging SIInsertWaitcnts pass (#144629)
Commit: 8f82c027c8969d965c43909da639e7790af19956
https://github.com/llvm/llvm-project/commit/8f82c027c8969d965c43909da639e7790af19956
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
Log Message:
-----------
[AMDGPU] New RegBankSelect: Add rules for `G_PTRTOINT` and `G_INTTOPTR` (#142604)
Commit: 681db064d221e9eef024ce0aef6165caa37fbfd2
https://github.com/llvm/llvm-project/commit/681db064d221e9eef024ce0aef6165caa37fbfd2
Author: Kunqiu Chen <camsyn at foxmail.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M compiler-rt/lib/tsan/rtl/tsan_platform.h
M compiler-rt/lib/tsan/rtl/tsan_rtl_access.cpp
Log Message:
-----------
[TSan] Make Shadow/Meta region inclusive-exclusive (#144647)
This commit changes the interval shadow/meta address check from
inclusive-inclusive ( $[\mathrm{start}, \mathrm{end}]$ ) to
inclusive-exclusive ( $[\mathrm{start}, \mathrm{end})$ ), to resolve the
ambiguity of the end point address. This also aligns the logic with the
check for `isAppMem` (i.e., inclusive-exclusive), ensuring consistent
behavior across all memory classifications.
1. The `isShadowMem` and `isMetaMem` checks previously used an
inclusive-inclusive interval, i.e., $[\mathrm{start}, \mathrm{end}]$,
which could lead to a boundary address being incorrectly classified as
both Shadow and Meta memory, e.g., 0x3000_0000_0000 in
`Mapping48AddressSpace`.
- What's more, even when Shadow doesn't border Meta, `ShadowMem::end`
cannot be considered a legal shadow address, as TSan protects the gap,
i.e., `ProtectRange(ShadowEnd(), MetaShadowBeg());`
2. `ShadowMem`/`MetaMem` addresses are derived from `AppMem` using an
affine-like transformation (`* factor + bias`). This transformation
includes two extra modifications: high- and low-order bits are masked
out, and for Shadow Memory, an optional XOR operation may be applied to
prevent conflicts with certain AppMem regions.
- Given that all AppMem regions are defined as inclusive-exclusive
intervals, $[\mathrm{start}, \mathrm{end})$, the resulting Shadow/Meta
regions should logically also be inclusive-exclusive.
Note: This change is purely for improving code consistency and should
have no functional impact. In practice, the exact endpoint addresses of
the Shadow/Meta regions are generally not reached.
Commit: 584cc376870505821b5ff0b0e80be85ee563ff0c
https://github.com/llvm/llvm-project/commit/584cc376870505821b5ff0b0e80be85ee563ff0c
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M libcxx/include/__math/abs.h
M libcxx/include/math.h
M libcxx/include/stdlib.h
M libcxx/test/std/numerics/c.math/abs.verify.cpp
Log Message:
-----------
[libc++] Move std::abs into __math/abs.h (#139586)
`template <class = int>` is also added to our implementations to avoid
an ambiguity between the libc's version and our version when both are
visible.
This avoids including `<stdlib.h>` in `<math.h>`.
Commit: 20245bbf66977ca9de5a2b6e29e8617a3a5d9fb5
https://github.com/llvm/llvm-project/commit/20245bbf66977ca9de5a2b6e29e8617a3a5d9fb5
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M libcxx/test/std/numerics/c.math/abs.pass.cpp
Log Message:
-----------
[libc++][NFC] Format abs.pass.cpp test
I will modify the test in an upcoming PR. I'm formatting it now to avoid
a bunch of whitespace changes in that PR.
Commit: 6273c5d4d3540204cb0d298cf1cf74ba94ed2a6c
https://github.com/llvm/llvm-project/commit/6273c5d4d3540204cb0d298cf1cf74ba94ed2a6c
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
Log Message:
-----------
[lldb][AArch64] Correctly invalidate svg when vg is written (#140875)
Recently the Linux Kernel has fixed a bunch of issues in SME support and
while testing that, I found two tests failing:
FAIL: test_za_register_dynamic_config_main_disabled
(TestZAThreadedDynamic.AArch64ZAThreadedTestCase)
FAIL: test_za_register_dynamic_config_main_enabled
(TestZAThreadedDynamic.AArch64ZAThreadedTestCase)
These tests write to vg during streaming mode from lldb and expect to
see that za has been resized to match it. Instead, it was unavailable.
lldb-server was sending the correct amount of data but lldb client was
expecting the old size.
Turns out that instead of a write to vg invalidating svg, it was
invalidating... something else. I'm still not sure how these tests ever
worked but with this one line fix, they pass again.
I did not see this issue with SVE or streaming SVE Z registers because
those always resize using the value of vg, and vg always has the value
we just wrote.
(remember that vg is the vector length of the **current** mode, not of
non-streaming mode, whereas svg is the vector length of streaming mode,
even if you are currently in non-streaming mode)
Commit: c0a9c908a697a150f797d0dff7f0bcd3782abed9
https://github.com/llvm/llvm-project/commit/c0a9c908a697a150f797d0dff7f0bcd3782abed9
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
Log Message:
-----------
[MLIR][NVVM-Docs] Fix rendering of a few tables in NVVM Docs (#144764)
This patch corrects the formatting of tables
in the tcgen05 ld/st and smem_descriptor Ops.
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: 97c1a2444574b32dd7a283c53be248c5dbbf62e9
https://github.com/llvm/llvm-project/commit/97c1a2444574b32dd7a283c53be248c5dbbf62e9
Author: Fabian Mora <fmora.dev at gmail.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td
M mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
M mlir/include/mlir/Dialect/Linalg/Utils/Utils.h
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/Padding.cpp
M mlir/lib/Dialect/Linalg/Utils/Utils.cpp
M mlir/test/Dialect/Linalg/transform-op-pad.mlir
Log Message:
-----------
[mlir][linalg] Add option to pad dynamic dims to `linalg::rewriteAsPaddedOp` (#144354)
This patch makes the following changes:
- Add a `ValueRange typeDynDims` argument to
`linalg::makeComposedPadHighOp`, allowing to pad a tensor with dynamic
dimensions using `tensor::createPadHighOp`.
- Add a `DenseMap<std::pair<unsigned, unsigned>, OpFoldResult>
sizeToPadTo;` option to `LinalgPaddingOptions`. This option allows
setting the size to use when padding a dimension of an operand, allowing
to pad operands even in the case they don't have a constant upper
bounding box. If the value is not provided, then the constant upper
bound is used by default.
- Add a `use_prescribed_tensor_shapes` option to
`transform.structured.pad`. If set to true then `tensor.dim` will be
used as dimensions to compute the size of the padded dim instead of
computing the constant upper bound.
- This patch also changes the behavior for computing the padded shape
`linalg::rewriteAsPaddedOp`, by using the newly added options in
`LinalgPaddingOptions`.
- Finally it adds tests verifying the behavior.
Commit: af51c9d9df9d482503fe30c80dd788a02161cea6
https://github.com/llvm/llvm-project/commit/af51c9d9df9d482503fe30c80dd788a02161cea6
Author: David Sherwood <david.sherwood at arm.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/branch-weights.ll
Log Message:
-----------
[LV][NFC] Add branch weight test showing incorrect behaviour (#144682)
This patch adds a test that shows incorrect branch weights being set in
function
EpilogueVectorizerEpilogueLoop::emitMinimumVectorEpilogueIterCountCheck
Commit: 0fe78c4a290517925acc03d59f235926f440f155
https://github.com/llvm/llvm-project/commit/0fe78c4a290517925acc03d59f235926f440f155
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/include/clang/Serialization/ASTReader.h
M clang/include/clang/Serialization/ASTRecordWriter.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
Log Message:
-----------
[NFC] [Serialization] Some Code Cleanups for Name lookup table things
Commit: 5bee2c34bde1aa8b0fb5aed7d5ce330f094f6436
https://github.com/llvm/llvm-project/commit/5bee2c34bde1aa8b0fb5aed7d5ce330f094f6436
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.h
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/lib/Object/IRSymtab.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
Log Message:
-----------
RuntimeLibcalls: Pass in FloatABI and EABI type (#144691)
We need the full set of ABI options to accurately compute
the full set of libcalls. This partially resolves missing
information required to compute the set of ARM calls.
Commit: 305953a32ded8a43b22f65cf73d9214729feb1fc
https://github.com/llvm/llvm-project/commit/305953a32ded8a43b22f65cf73d9214729feb1fc
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/include/llvm/MC/MCTargetOptions.h
M llvm/include/llvm/Support/CodeGen.h
Log Message:
-----------
MC: Move ExceptionHandling enum to Support (#144692)
Similar to b5967264b0fbfd502b3a7edec27409e966fb68be, we need
to use this in RuntimeLibcalls to compute the set of library
calls.
Commit: 1c35fe4e6b2596d153da82b23d04a3779fb12730
https://github.com/llvm/llvm-project/commit/1c35fe4e6b2596d153da82b23d04a3779fb12730
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.h
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/lib/Target/VE/VEISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
RuntimeLibcalls: Pass in exception handling type (#144696)
All of the ABI options that influence libcall decisions need
to be passed in.
Commit: 74054cab7a3e04b323828850409343932e975737
https://github.com/llvm/llvm-project/commit/74054cab7a3e04b323828850409343932e975737
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/include/llvm/Analysis/HashRecognize.h
M llvm/lib/Analysis/HashRecognize.cpp
M llvm/lib/Passes/PassRegistry.def
Log Message:
-----------
[HashRecognize] Make it a non-PM analysis (#144742)
Make HashRecognize a non-PassManager analysis that can be called to get
the result on-demand, creating a new getResult() entry-point. The issue
was discovered when attempting to use the analysis to perform a
transform in LoopIdiomRecognize.
Commit: 30824c449a893771c3f25f0eb29cfa9d2cfd4f15
https://github.com/llvm/llvm-project/commit/30824c449a893771c3f25f0eb29cfa9d2cfd4f15
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
Log Message:
-----------
[lldb][DWARFASTParserClang] GetCXXObjectParameter to take DeclContext DIE parameter (#144876)
I'm trying to call `GetCXXObjectParameter` from unit-tests in a
follow-up patch and taking a `DWARFDIE` instead of `clang::DeclContext`
makes that much simpler. These should be equivalent, since all we're
trying to check is that the parent context is a record type.
Commit: 046e2f545ef568b2ce577c9172a0f147dc376071
https://github.com/llvm/llvm-project/commit/046e2f545ef568b2ce577c9172a0f147dc376071
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
A llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-interleave.ll
Log Message:
-----------
[LV] Add interleaving test with partial reductions and non-const start.
Add test coverage for mis-compile after
https://github.com/llvm/llvm-project/pull/142290.
Commit: e33f13ba4824d807e846e7783a48efd6c0bf58ee
https://github.com/llvm/llvm-project/commit/e33f13ba4824d807e846e7783a48efd6c0bf58ee
Author: Matthias Springer <me at m-sp.org>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td
M mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
M mlir/test/Dialect/Arith/ops.mlir
Log Message:
-----------
[mlir][arith] Add overflow flags to `arith.trunci` (#144863)
LLVM already supports overflow flags on `llvm.trunc` for a while. This
commit adds support for these flags to `arith.trunci`.
Commit: b73720cf6c5380854bf27d4453abf21cc87ae642
https://github.com/llvm/llvm-project/commit/b73720cf6c5380854bf27d4453abf21cc87ae642
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/StaticAnalyzer/Checkers/DynamicTypePropagation.cpp
Log Message:
-----------
[analyzer] Conversion to CheckerFamily: DynamicTypePropagation (#144735)
This commit converts the class DynamicTypePropagation to a very simple
checker family, which has only one checker frontend -- but also supports
enabling the backend ("modeling checker") without the frontend.
As a tangentially related change, this commit adds the backend of
DynamicTypePropagation as a dependency of alpha.core.DynamicTypeChecker
in Checkers.td, because the header comment of DynamicTypeChecker.cpp
claims that it depends on DynamicTypePropagation and the source code
seems to confirm this.
(The lack of this dependency relationship didn't cause problems, because
'core.DynamicTypePropagation' is in the group 'core', so it is
practically always active. However, explicitly declaring the dependency
clarifies the fact that the separate existence of the modeling checker
is warranted.)
Commit: 2b4d757290226e0185e17294339aae1588efd07e
https://github.com/llvm/llvm-project/commit/2b4d757290226e0185e17294339aae1588efd07e
Author: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M bolt/include/bolt/Passes/PAuthGadgetScanner.h
M bolt/lib/Passes/PAuthGadgetScanner.cpp
A bolt/test/binary-analysis/AArch64/gs-pauth-authentication-oracles.s
M bolt/test/binary-analysis/AArch64/gs-pauth-debug-output.s
Log Message:
-----------
[BOLT] Gadget scanner: detect authentication oracles (#135663)
Implement the detection of authentication instructions whose results can
be inspected by an attacker to know whether authentication succeeded.
As the properties of output registers of authentication instructions are
inspected, add a second set of analysis-related classes to iterate over
the instructions in reverse order.
Commit: 936c5566db013225dc098ff961395bb19e1bf2a4
https://github.com/llvm/llvm-project/commit/936c5566db013225dc098ff961395bb19e1bf2a4
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Semantics/CMakeLists.txt
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
R flang/lib/Semantics/rewrite-directives.cpp
R flang/lib/Semantics/rewrite-directives.h
M flang/lib/Semantics/rewrite-parse-tree.cpp
A flang/test/Lower/OpenMP/requires-admo-acqrel.f90
A flang/test/Lower/OpenMP/requires-admo-invalid1.f90
A flang/test/Lower/OpenMP/requires-admo-invalid2.f90
R flang/test/Semantics/OpenMP/requires-atomic01.f90
R flang/test/Semantics/OpenMP/requires-atomic02.f90
Log Message:
-----------
[flang][OpenMP] Handle REQUIRES ADMO in lowering (#144362)
The previous approach rewrote the atomic constructs in the AST based on
the REQUIRES ATOMIC_DEFAULT_MEM_ORDER directives. The new approach
checks for incorrect uses of REQUIRED ADMO in the semantic analysis, and
applies it in lowering, eliminating the need for a separate
tree-rewriting procedure.
Commit: e478a22d540d336632fb3c110c5377447cd7f3b2
https://github.com/llvm/llvm-project/commit/e478a22d540d336632fb3c110c5377447cd7f3b2
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/test/CodeGen/builtin_vectorelements.c
M llvm/include/llvm/IR/IRBuilder.h
M llvm/lib/IR/IRBuilder.cpp
M llvm/test/Analysis/ValueTracking/phi-known-bits.ll
M llvm/test/Instrumentation/AddressSanitizer/asan-masked-load-store.ll
M llvm/test/Instrumentation/AddressSanitizer/asan-vp-load-store.ll
M llvm/test/Instrumentation/AddressSanitizer/vector-load-store.ll
M llvm/test/Instrumentation/BoundsChecking/simple.ll
M llvm/test/Instrumentation/HWAddressSanitizer/vector-load-store.ll
M llvm/test/Instrumentation/MemorySanitizer/vector-load-store.ll
M llvm/test/Instrumentation/MemorySanitizer/vscale.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-counting-elems.ll
M llvm/test/Transforms/InstCombine/gep-vector.ll
M llvm/test/Transforms/InstCombine/gepofconstgepi8.ll
M llvm/test/Transforms/InstCombine/getelementptr.ll
M llvm/test/Transforms/InstCombine/icmp-gep.ll
M llvm/test/Transforms/InstCombine/masked_intrinsics.ll
M llvm/test/Transforms/InstCombine/opaque-ptr.ll
M llvm/test/Transforms/InstCombine/scalable-vector-array.ll
M llvm/test/Transforms/InstCombine/scalable-vector-struct.ll
M llvm/test/Transforms/InstCombine/sub-gep.ll
M llvm/test/Transforms/InstCombine/vscale_gep.ll
M llvm/test/Transforms/LoopVectorize/AArch64/clamped-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/divs-with-scalable-vfs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/eliminate-tail-predication.ll
M llvm/test/Transforms/LoopVectorize/AArch64/gather-do-not-vectorize-addressing.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll
M llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_prefer_scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
M llvm/test/Transforms/LoopVectorize/AArch64/pr60831-sve-inv-store-crash.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-avoid-scalarization.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-reduction-inloop-cond.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
M llvm/test/Transforms/LoopVectorize/AArch64/simple_early_exit.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-inloop-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-no-remaining-iterations.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-strict-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-extract-last-veclane.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-fneg.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inv-store.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-live-out-pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-multiexit.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-runtime-check-size-based-threshold.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-forced.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-optsize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-unroll.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-vscale-based-trip-counts.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-gep.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-too-many-deps.ll
M llvm/test/Transforms/LoopVectorize/AArch64/tail-folding-styles.ll
M llvm/test/Transforms/LoopVectorize/AArch64/uniform-args-call-variants.ll
M llvm/test/Transforms/LoopVectorize/AArch64/wider-VF-for-callinst.ll
M llvm/test/Transforms/LoopVectorize/RISCV/bf16.ll
M llvm/test/Transforms/LoopVectorize/RISCV/blend-any-of-reduction-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/defaults.ll
M llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
M llvm/test/Transforms/LoopVectorize/RISCV/f16.ll
M llvm/test/Transforms/LoopVectorize/RISCV/fminimumnum.ll
M llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-masked-access.ll
M llvm/test/Transforms/LoopVectorize/RISCV/lmul.ll
M llvm/test/Transforms/LoopVectorize/RISCV/low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/RISCV/mask-index-type.ll
M llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll
M llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/RISCV/remark-reductions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse-output.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/RISCV/safe-dep-distance.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-basics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-tailfold.ll
M llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-bin-unary-ops-args.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cond-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-div.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-interleave.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-intermediate-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-iv32.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-known-no-overflow.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-masked-loadstore.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-ordered-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-safe-dep-distance.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-uniform-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_scalable.ll
M llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/scalable-inductions.ll
M llvm/test/Transforms/LoopVectorize/scalable-iv-outside-user.ll
M llvm/test/Transforms/LoopVectorize/scalable-lifetime.ll
M llvm/test/Transforms/LoopVectorize/scalable-loop-unpredicated-body-scalar-tail.ll
M llvm/test/Transforms/LoopVectorize/scalable-reduction-inloop.ll
M llvm/test/Transforms/LoopVectorize/scalable-trunc-min-bitwidth.ll
M llvm/test/Transforms/LoopVectorize/vectorize-force-tail-with-evl.ll
M llvm/test/Transforms/MemCpyOpt/vscale-crashes.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/sve-interleave-vectorization.ll
M llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-exp.ll
Log Message:
-----------
[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532)
This put the onus on the caller to ensure the result type is big enough.
In the unlikely event a cropped result is required then explicitly
truncate a safe value.
Commit: c4c2d777f4aea07c59ff85ade75816df24b05389
https://github.com/llvm/llvm-project/commit/c4c2d777f4aea07c59ff85ade75816df24b05389
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-interleave.ll
Log Message:
-----------
[VPlan] Fix handling of ReductionStartVector for rdxs when unrolling.
Update handling of ReductionStartVector in VPlanUnroll for partial
reductions. The new code makes sure all parts are properly set to the
cloned ReductionStartVector.
Fixes a mis-compile reported for
https://github.com/llvm/llvm-project/pull/142290.
Commit: 5148e085386fb1808fba055e170d88e3344220ca
https://github.com/llvm/llvm-project/commit/5148e085386fb1808fba055e170d88e3344220ca
Author: Karlo Basioli <k.basioli at gmail.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/include/clang/Serialization/ASTRecordWriter.h
Log Message:
-----------
Fix build issue caused by commit #0fe78c4 (#144888)
Noticed internally in blaze build.
Commit: dae5104eed451fdd0354ff9639feba10f9dc5440
https://github.com/llvm/llvm-project/commit/dae5104eed451fdd0354ff9639feba10f9dc5440
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.h
M lldb/unittests/SymbolFile/DWARF/DWARFASTParserClangTests.cpp
Log Message:
-----------
[lldb][DWARFASTParserClang] Make GetCXXObjectParameter public and call it from unit-tests (#144879)
My goal is to remove the `object_pointer` member on
`ParsedDWARFTypeAttributes` since it's duplicating information that we
retrieve with `GetCXXObjectParameter` anyway. To continue having
coverage for the `DW_AT_object_pointer` code-paths, instead of checking
the
`attrs.object_pointer` I'm now calling `GetCXXObjectParameter` directly.
We could find some very roundabout way to go via the Clang AST to check
that the object parameter was parsed correctly, but that quickly became
quite painful.
Depends on https://github.com/llvm/llvm-project/pull/144876
Commit: c079040eea5ce75a97285003948d141ebaac69e6
https://github.com/llvm/llvm-project/commit/c079040eea5ce75a97285003948d141ebaac69e6
Author: Charles Zablit <c_zablit at apple.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M lldb/include/lldb/Core/DemangledNameInfo.h
M lldb/unittests/Core/MangledTest.cpp
Log Message:
-----------
[lldb] add has methods to all DemangledNameInfo attributes (#144549)
Add `hasX` methods to all the attributes of `DemangledNameInfo`.
Commit: 09e794c4bb138e14b3156d7dbdac0164d9c0327b
https://github.com/llvm/llvm-project/commit/09e794c4bb138e14b3156d7dbdac0164d9c0327b
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.cpp
Log Message:
-----------
[HIP] Emit the CUID value in the module with the new driver (#144570)
Summary:
This is a weird point of divergence that was not updated when the new
driver
switched to using the CUID method, which is also apparently critical
for SPIR-V compilation not failing? Somehow if we don't emit this global
than the `llvm.compiler.used` global uses AS(0) which makes SPIR-V
unhappy, but with this global it's AS(4) which makes it happy. Either
way, this should be fixed.
Commit: e873fd157eda617ffd42edad3c4a6ab495e6e375
https://github.com/llvm/llvm-project/commit/e873fd157eda617ffd42edad3c4a6ab495e6e375
Author: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M bolt/lib/Passes/PAuthGadgetScanner.cpp
M bolt/test/binary-analysis/AArch64/gs-pauth-debug-output.s
Log Message:
-----------
[BOLT] Gadget scanner: do not crash on debug-printing CFI instructions (#136151)
Some instruction-printing code used under LLVM_DEBUG does not handle CFI
instructions well. While CFI instructions seem to be harmless for the
correctness of the analysis results, they do not convey any useful
information to the analysis either, so skip them early.
Commit: 493a359237e824216d5c572656481c42165a2cb7
https://github.com/llvm/llvm-project/commit/493a359237e824216d5c572656481c42165a2cb7
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M lldb/test/API/commands/register/register/aarch64_mte_ctrl_register/TestMTECtrlRegister.py
Log Message:
-----------
[lldb][AArch64] Fix live process test for Linux's mte_ctrl register
I forgot to update this when I changed the presentation of the
"TCF" field.
Commit: 83381ba832a5cf34b09e27a6154c7179fed2fc80
https://github.com/llvm/llvm-project/commit/83381ba832a5cf34b09e27a6154c7179fed2fc80
Author: Ilia Kuklin <ikuklin at accesssoftek.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M lldb/source/ValueObject/DILParser.cpp
M lldb/test/API/commands/frame/var-dil/basics/ArraySubscript/TestFrameVarDILArraySubscript.py
M lldb/test/API/commands/frame/var-dil/basics/ArraySubscript/main.cpp
Log Message:
-----------
[LLDB] Add negative number parsing to DIL (#144557)
Commit: 5645d6710904107d66a45f1c3ee0ee25924ff08a
https://github.com/llvm/llvm-project/commit/5645d6710904107d66a45f1c3ee0ee25924ff08a
Author: Aly ElAshram <71949028+AlyElashram at users.noreply.github.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
A libc/config/darwin/aarch64/config.json
M libc/config/darwin/aarch64/entrypoints.txt
M libc/config/darwin/aarch64/headers.txt
M libc/src/setjmp/CMakeLists.txt
A libc/src/setjmp/darwin/CMakeLists.txt
A libc/src/setjmp/darwin/sigsetjmp_epilogue.cpp
M libc/test/src/CMakeLists.txt
Log Message:
-----------
Implement `sigsetjmp` and `siglongjmp` for darwin/aarch64 (#139555)
Commit: bf79d4819edeb54c6cf528db63676110992908a8
https://github.com/llvm/llvm-project/commit/bf79d4819edeb54c6cf528db63676110992908a8
Author: zhijian lin <zhijian at ca.ibm.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/lib/Basic/Targets/PPC.cpp
M clang/test/CodeGenCXX/cxx11-thread-local-reference.cpp
M clang/test/Driver/aix-shared-lib-tls-model-opt.c
M clang/test/Driver/aix-small-local-exec-dynamic-tls.c
M clang/test/Driver/ppc-crbits.cpp
M clang/test/Driver/ppc-isa-features.cpp
M llvm/include/llvm/TargetParser/CMakeLists.txt
M llvm/include/llvm/TargetParser/PPCTargetParser.h
M llvm/include/llvm/TargetParser/TargetParser.h
M llvm/lib/Target/PowerPC/PPC.td
M llvm/lib/TargetParser/PPCTargetParser.cpp
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/utils/TableGen/Basic/CMakeLists.txt
A llvm/utils/TableGen/Basic/TargetFeaturesEmitter.cpp
A llvm/utils/TableGen/Basic/TargetFeaturesEmitter.h
M llvm/utils/TableGen/SubtargetEmitter.cpp
Log Message:
-----------
[Reland] [PowerPC] frontend get target feature from backend with cpu name (#144594)
1. The PR proceeds with a backend target hook to allow front-ends to
determine what target features are available in a compilation based on
the CPU name.
2. Fix a backend target feature bug that supports HTM for
Power8/9/10/11. However, HTM is only supported on Power8/9 according to
the ISA.
3. All target features that are hardcoded in PPC.cpp can be retrieved
from the backend target feature. I have double-checked that the
hardcoded logic for inferring target features from the CPU in the
frontend(PPC.cpp) is the same as in PPC.td.
The reland patch addressed the comment
https://github.com/llvm/llvm-project/pull/137670#discussion_r2143541120
Commit: f87b6625d64c4ba95cf26b249ce6bdbcb31d65c9
https://github.com/llvm/llvm-project/commit/f87b6625d64c4ba95cf26b249ce6bdbcb31d65c9
Author: Abdul Raheem <abdulraheembeigh at gmail.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M mlir/include/mlir/IR/Operation.h
Log Message:
-----------
[MLIR][NFC] Fixed some Typos (#144263)
-- Fixed some typos in Operation.h
Signed-off: Abdul Raheem Beigh abdulraheembeigh at gmail.com
Commit: e75e2485f2e5e627d0bdf0306df4672f69ddd6eb
https://github.com/llvm/llvm-project/commit/e75e2485f2e5e627d0bdf0306df4672f69ddd6eb
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
A llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-gfx12-fake16.mir
A llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-gfx12-true16.mir
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-fake16.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
Log Message:
-----------
[AMDGPU][True16][Codegen] keep srcmod/clamp/omod from v_s_xxx_f16 when moved to VALU (#144781)
https://github.com/llvm/llvm-project/pull/141152 causes an issue in
v_s_xxx_f16 lowering in both true16/fake16 flow.
V_S_XXX_F16 are special insts which has scalar input/output but in VALU
VOP3 format. Need to keep the srcmod/clamp/omod when lower it to its
corresponding VALU inst with vector input/output.
Commit: 278ece7c80d36bb1074fa53e655a5ca8f31145dd
https://github.com/llvm/llvm-project/commit/278ece7c80d36bb1074fa53e655a5ca8f31145dd
Author: Abhishek Kaushik <abhishek.kaushik at intel.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
A llvm/test/Transforms/InstCombine/bitcast-known-bits.ll
Log Message:
-----------
[InstCombine][NFC] Pre-commit tests for #125935 (#144111)
Pre-commit tests for #125935
---------
Co-authored-by: Simon Pilgrim <llvm-dev at redking.me.uk>
Commit: a4e4527c4b44be9a88168c0a4758de58fd1a770d
https://github.com/llvm/llvm-project/commit/a4e4527c4b44be9a88168c0a4758de58fd1a770d
Author: Matthias Springer <me at m-sp.org>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M mlir/lib/Conversion/FuncToLLVM/FuncToLLVM.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
Log Message:
-----------
[mlir][Transforms] Fix replaceUsesOfBlockArgument API (#144706)
Before this PR, users had to pass the "old" block argument when
replacing the uses of a block argument in a newly converted block. Users
can now pass the actual block argument that should be replaced.
Note for LLVM integration: Make sure to pass the current block argument
instead of the old one.
Commit: 802fa92aee3565768887615108aa3e924d4e0fc7
https://github.com/llvm/llvm-project/commit/802fa92aee3565768887615108aa3e924d4e0fc7
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Utils/PredicateInfo.cpp
Log Message:
-----------
[PredicateInfo] Avoid duplicate hash lookup (NFC)
Use try_emplace to either look up the existing entry or insert it.
Commit: 7e8f1f5f72753a1d9d3ae2810da52b82a787600b
https://github.com/llvm/llvm-project/commit/7e8f1f5f72753a1d9d3ae2810da52b82a787600b
Author: Siu Chi Chan <siuchi.chan at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/test/Driver/hip-runtime-libs-linux.hip
Log Message:
-----------
[HIP] Remove dots in HIP runtime path (#143792)
Remove the dots in the HIP path before passing to the rpath flag
Commit: 4c6f398b866030c17fd94dcdca04f4df03c5214c
https://github.com/llvm/llvm-project/commit/4c6f398b866030c17fd94dcdca04f4df03c5214c
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Driver/ToolChains/HIPAMD.h
A clang/test/Driver/spirv-amd-toolchain.c
Log Message:
-----------
[Clang] Add standalone AMDGPU SPIR-V toolchain (#144576)
Summary:
The AMDGPU toolchain uses a different set of tools than the standard
SPIR-V toolchain. The linker wrapper prefers to invoke a linker via a
clang toolchain. To make that work we introduce
`--target=spirv64-amd-amdhsa` so that it creates the linking phases that
HIP prefers. Additionally, this can be used to make LLVM-IR / SPIR-V
from C/C++ that can be linked with the HIP output.
Commit: 19360e62d0d1a1dabf9f01736927ab8f1b72c7df
https://github.com/llvm/llvm-project/commit/19360e62d0d1a1dabf9f01736927ab8f1b72c7df
Author: Nico Weber <thakis at chromium.org>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/include/llvm/TargetParser/BUILD.gn
M llvm/utils/gn/secondary/llvm/utils/TableGen/Basic/BUILD.gn
Log Message:
-----------
[gn build] port bf79d4819ede (ppc -gen-target-features)
Commit: 89efae916a5de0387710b7dc06938423817e1503
https://github.com/llvm/llvm-project/commit/89efae916a5de0387710b7dc06938423817e1503
Author: Jack Styles <jack.styles at arm.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
A flang/test/Lower/OpenMP/target-enter-data-default-openmp52.f90
Log Message:
-----------
[Flang][OpenMP] Update default MapType for Map Clauses and OpenMP 5.2 (#144715)
In OpenMP 5.2, the `target enter data` and `target exit data` constructs
now have default map types if the user does not define them in the Map
clause. For `target enter data`, this is `to` and `target exit data`
this is `from`. This behaviour is now enabled when OpenMP 5.2 or greater
is used when compiling. To enable this, the default value is now set in
the `processMap` clause, with any previous behaviour being maintained
for either older versions of OpenMP or other directives.
See also #110008
Commit: eb694b28461fdbd5e347fca59829e8a9ad021773
https://github.com/llvm/llvm-project/commit/eb694b28461fdbd5e347fca59829e8a9ad021773
Author: Tobias Gysi <tobias.gysi at nextsilicon.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/test/Dialect/Arith/canonicalize.mlir
Log Message:
-----------
[mlir][arith] Delete mul ext canonicalizations (#144844)
The Arith dialect includes patterns that canonicalize a sequence of:
- trunci(shrui(mul(sext(x), sext(y)), c)) -> mulsi_extended(x, y)
- trunci(shrui(mul(zext(x), zext(y)), c)) -> mului_extended(x, y)
These patterns return the high word of an extended multiplication, which
assumes that the shift amount is equal to the bit width of the original
operands. This check was missing, leading to incorrect canonicalizations
when the shift amount was less than the bit width.
For example, the following code:
```
%x = arith.extui %a: i32 to i33
%y = arith.extui %b: i32 to i33
%m = arith.muli %x, %y: i33
%c1 = arith.constant 1: i33
%sh = arith.shrui %m, %c1 : i33
%hi = arith.trunci %sh: i33 to i32
```
would incorrectly be canonicalized to:
```
_, %hi = arith.mului_extended %a, %b : i32
```
This commit removes the faulty canonicalizations since they are not
believed to be generally beneficial (c.f., the discussion of the
alternative https://github.com/llvm/llvm-project/pull/144787 which fixes
the canonicalizations).
Commit: 3516ad05dfd674d731487cb67bbfe48f7e1fda9c
https://github.com/llvm/llvm-project/commit/3516ad05dfd674d731487cb67bbfe48f7e1fda9c
Author: Mikhail R. Gadelha <mikhail at igalia.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/floating-point.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.s
Log Message:
-----------
[RISCV] Update SpacemiT X60 scheduling latencies based on hardware measurements (#144730)
This patch updates the RISC-V SpacemiT X60 scheduling model with latency
values collected from the X60 hardware. The previous values were
empirically derived but were slightly off.
Changes:
- LoadLatency (baseline for load instructions): 5 --> 3 cycles
- Memory operations: unified at 4 cycles
- Atomic loads/stores: 5 --> 8 cycles
- Atomic RMW operations: 5 --> 12 cycles
Hardware-measured values provide more accurate instruction scheduling
for the in-order X60 core. Testing shows NFC across benchmarks except
for 523.xalancbmk_r (known to be noisy).
https://lnt.lukelau.me/db_default/v4/nts/663?compare_to=657
Commit: fdb572681de7e12b7cd03fd33478022272eb1bae
https://github.com/llvm/llvm-project/commit/fdb572681de7e12b7cd03fd33478022272eb1bae
Author: Karlo Basioli <k.basioli at gmail.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
Fix bazel build after #144594 (#144904)
Commit: 5eb24fde11cd82a08f208509f80f428da90c89c9
https://github.com/llvm/llvm-project/commit/5eb24fde11cd82a08f208509f80f428da90c89c9
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/RISCV/shifts.ll
Log Message:
-----------
[SelectionDAG][RISCV] Preserve nneg flag when folding (trunc (zext X))->(zext X). (#144807)
If X is known non-negative, that's still true if we fold the truncate
to create a smaller zext.
In the i128 tests, SelectionDAGBuilder aggressively truncates the
`zext nneg` to i64 to match `getShiftAmountTy`. If we don't preserve
the `nneg` we can't see that the shift amount argument being `signext`
means we don't need to do any extension
Commit: 3de01d07c33c10dfefc753c87c0a926fd512425b
https://github.com/llvm/llvm-project/commit/3de01d07c33c10dfefc753c87c0a926fd512425b
Author: Karlo Basioli <k.basioli at gmail.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/TargetParser/TargetParser.cpp
Log Message:
-----------
Fix bazel build after #144594, mark variable as potentially unused (#144910)
Commit: 36af7345dfb8e84a1f2971db34089b63321e8467
https://github.com/llvm/llvm-project/commit/36af7345dfb8e84a1f2971db34089b63321e8467
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/docs/CommandGuide/clang.rst
M clang/docs/ReleaseNotes.rst
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/extend-variable-liveness.c
Log Message:
-----------
Reapply "[Clang] Enable -fextend-variable-liveness at -Og (#118026)"
Relands this feature after several fixes:
* Force fake uses to be emitted before musttail calls (#136867)
* Added soften-float legalization for fake uses (#142714)
* Treat fake uses as size-less instructions in a SystemZ assert (#144390)
If further issues with fake uses are found then this may be reverted again,
but all currently-known issues are resolved.
This reverts commit 2dc6e98169baeb1f73036da0ea50fd828d8323d0.
Commit: f4db14229cd975822c41376afda9d56a29f9396c
https://github.com/llvm/llvm-project/commit/f4db14229cd975822c41376afda9d56a29f9396c
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/include/llvm/Transforms/Utils/SCCPSolver.h
M llvm/lib/Transforms/IPO/SCCP.cpp
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
Log Message:
-----------
[SCCP] Move logic for removing ssa.copy into Solver (NFC)
So it can be reused between IPSCCP and SCCP.
Make the implementation a bit more efficient by only lookup the
PredicateInfo once.
Commit: 01d648a42939c834b6b45677e540882222b01c11
https://github.com/llvm/llvm-project/commit/01d648a42939c834b6b45677e540882222b01c11
Author: Steven Perron <stevenperron at google.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/AST/HLSL/vk.spec-constant.usage.hlsl
R clang/test/CodeGenHLSL/inline-spirv/SpirvType.alignment.hlsl
R clang/test/CodeGenHLSL/inline-spirv/SpirvType.hlsl
A clang/test/CodeGenHLSL/vk-features/SpirvType.alignment.hlsl
A clang/test/CodeGenHLSL/vk-features/SpirvType.hlsl
A clang/test/CodeGenHLSL/vk-features/vk.spec-constant.hlsl
A clang/test/SemaHLSL/vk.spec-constant.error.hlsl
Log Message:
-----------
[HLSL][SPIRV] Reapply "[HLSL][SPIRV] Add vk::constant_id attribute." (#144902)
- **Reapply "[HLSL][SPIRV] Add vk::constant_id attribute." (#144812)**
- **Fix memory leak.**
Commit: c1ac87b327861a7387c1ab9e1ffb1c002acbcd6a
https://github.com/llvm/llvm-project/commit/c1ac87b327861a7387c1ab9e1ffb1c002acbcd6a
Author: lntue <lntue at google.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M libc/src/setjmp/CMakeLists.txt
Log Message:
-----------
[libc] Fix setjmp build order. (#144917)
Fix build order issue from
https://github.com/llvm/llvm-project/pull/139555.
Commit: b8337349d9b6143669e8bfa6776926a708cacf99
https://github.com/llvm/llvm-project/commit/b8337349d9b6143669e8bfa6776926a708cacf99
Author: lntue <lntue at google.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M libc/src/__support/FPUtil/FEnvImpl.h
M libc/src/__support/macros/optimization.h
Log Message:
-----------
[libc][math] Skip setting errno and floating point exception for math functions when LIBC_MATH flag has LIBC_MATH_NO_ERRNO and LIBC_MATH_NO_EXCEPT. (#144920)
Commit: 5cf7d871b030212d021ffc9356620551f09ad402
https://github.com/llvm/llvm-project/commit/5cf7d871b030212d021ffc9356620551f09ad402
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/Expr.h
M clang/include/clang/AST/OpenACCClause.h
M clang/include/clang/AST/OpenMPClause.h
M clang/include/clang/AST/StmtOpenACC.h
M clang/include/clang/AST/Type.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/AST/ExprCXX.cpp
M clang/lib/AST/OpenMPClause.cpp
M clang/lib/AST/Type.cpp
Log Message:
-----------
[NFC][Clang][AST] Adopt simplified `getTrailingObjects` in AST (#144432)
Adopt simplified `getTrailingObjects` API in several places in clag/AST
that were missed by earlier changes.
Commit: c0cc81cdc03c97473ba771bbc3a2330bd22396bc
https://github.com/llvm/llvm-project/commit/c0cc81cdc03c97473ba771bbc3a2330bd22396bc
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
Log Message:
-----------
[NFC][Clang] Adopt simplified `getTrailingObjects` in ASTReader (#144438)
Commit: 3fe62682ef9ca514b899d0cecaebb8f1fd97baef
https://github.com/llvm/llvm-project/commit/3fe62682ef9ca514b899d0cecaebb8f1fd97baef
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
Log Message:
-----------
[mlir][vector] Use `result` consistently as the result argument name (#144739)
This patch updates the following ops to use `result` (instead of `res`)
as the name for their result argument:
* `vector.scalable.insert`
* `vector.scalable.extract`
* `vector.insert_strided_slice`
This change ensures naming consistency with other ops in the `vector`
dialect. It addresses part of:
* https://github.com/llvm/llvm-project/issues/131602
Commit: 0816bb32ac37b24d2f895f0c0464b7659fffd4fc
https://github.com/llvm/llvm-project/commit/0816bb32ac37b24d2f895f0c0464b7659fffd4fc
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
Log Message:
-----------
[Matrix] Fix heap-use-after-free after 0fa373c77ded203eddb.
We need to skip instructions in FusedInsts, as they may have been
deleted. Fixes a heap-use-after-free after #141681.
Commit: 6ce86538c11b3ef93a2a8df3bd4f817a724f42bd
https://github.com/llvm/llvm-project/commit/6ce86538c11b3ef93a2a8df3bd4f817a724f42bd
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/ControlFlow/IR/ControlFlowOps.td
M mlir/lib/Dialect/ControlFlow/IR/ControlFlowOps.cpp
M mlir/test/Dialect/ControlFlow/canonicalize.mlir
Log Message:
-----------
[mlir][cf] Preserve branch weights during cf.cond_br canonicalization. (#144822)
Commit: c0c71463f6bca05eb4540b68cdcbd17c916562c9
https://github.com/llvm/llvm-project/commit/c0c71463f6bca05eb4540b68cdcbd17c916562c9
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/include/llvm/IR/PatternMatch.h
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp
A llvm/test/Transforms/InstCombine/sub-sext-add.ll
Log Message:
-----------
[InstCombine] Optimize sub(sext(add(x,y)),sext(add(x,z))). (#144174)
This pattern can be often met in Flang generated LLVM IR,
for example, for the counts of the loops generated for array
expressions like: `a(x:x+y)` or `a(x+z:x+z)` or their variations.
In order to compute the loop count, Flang needs to subtract
the lower bound of the array slice from the upper bound
of the array slice. To avoid the sign wraps, it sign extends
the original values (that may be of any user data type)
to `i64`.
This peephole is really helpful in CPU2017/548.exchange2,
where we have multiple following statements like this:
```
block(row+1:row+2, 7:9, i7) = block(row+1:row+2, 7:9, i7) - 10
```
While this is just a 2x3 iterations loop nest, LLVM cannot
figure it out, ending up vectorizing the inner loop really
hard (with a vector epilog and scalar remainder). This, in turn,
causes problems for LSR that ends up creating too many loop-carried
values in the loop containing the above statement, which are then
causing too many spills/reloads.
Alive2: https://alive2.llvm.org/ce/z/gLgfYX
Related to #143219.
Commit: 0b8179b2adbc821324c425d7cafd269f84e72d5e
https://github.com/llvm/llvm-project/commit/0b8179b2adbc821324c425d7cafd269f84e72d5e
Author: Abhishek Kaushik <abhishek.kaushik at intel.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Transforms/InstCombine/X86/x86-vector-shifts.ll
M llvm/test/Transforms/InstCombine/bitcast-known-bits.ll
Log Message:
-----------
[ValueTracking] Improve `Bitcast` handling to match SDAG (#125935)
Closes #125228
Commit: f780955e1df9105e9c4e67ebd16efded7dd279e2
https://github.com/llvm/llvm-project/commit/f780955e1df9105e9c4e67ebd16efded7dd279e2
Author: Justin King <jcking at google.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M compiler-rt/lib/lsan/lsan_interceptors.cpp
Log Message:
-----------
lsan: fix macos build after #144604 (#144818)
Fixes build failures on macOS, including
https://green.lab.llvm.org/job/llvm.org/job/clang-stage1-RA/
llvm-project/compiler-rt/lib/lsan/lsan_interceptors.cpp:579:3: error: use of undeclared identifier 'LSAN_MAYBE_INTERCEPT_FREE_SIZED'
13:23:58 579 | LSAN_MAYBE_INTERCEPT_FREE_SIZED;
13:23:58 | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
13:23:58 /Users/ec2-user/jenkins/workspace/llvm.org/as-lldb-cmake/llvm-project/compiler-rt/lib/lsan/lsan_interceptors.cpp:580:3: error: use of undeclared identifier 'LSAN_MAYBE_INTERCEPT_FREE_ALIGNED_SIZED'
13:23:58 580 | LSAN_MAYBE_INTERCEPT_FREE_ALIGNED_SIZED;
13:23:58 | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
13:23:58 2 errors generated.
Commit: 836201f1177c38f3ca0457de019bb179a04afe3c
https://github.com/llvm/llvm-project/commit/836201f1177c38f3ca0457de019bb179a04afe3c
Author: Umang Yadav <29876643+umangyadav at users.noreply.github.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/test/Conversion/AMDGPUToROCDL/mfma-gfx950.mlir
Log Message:
-----------
Allow bf16 operands on new MFMAs (#144925)
New gfx950 MFMA allows bf16 operands.
https://github.com/llvm/llvm-project/blob/c0cc81cdc03c97473ba771bbc3a2330bd22396bc/llvm/include/llvm/IR/IntrinsicsAMDGPU.td#L3434
When running `amdgpu-to-rocdl`, Current logic converts bf16 to i16
always which fails to compile for newer bf16 MFMA e.g.
`v_mfma_f32_16x16x32bf16`.
Backend expects bf16 type for the operands for those newer MFMAs. This
patch fixes it.
CC: @krzysz00 @dhernandez0 @giuseros @antiagainst @kuhar
Commit: 74ec1c287a88dffc232c38e0fdd3251f6b167d15
https://github.com/llvm/llvm-project/commit/74ec1c287a88dffc232c38e0fdd3251f6b167d15
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
A llvm/test/Transforms/LoopVectorize/ARM/mve-reductions-interleave.ll
Log Message:
-----------
[LV] Add tests interleaving extended and multiply/accumulate reductions.
Add missing test coverage for interleaving with
VPExtendedReduction/VPMulAccumulateReduction recipes.
Adds missing test coverage in preparation for
https://github.com/llvm/llvm-project/pull/144281.
Commit: 3bee9ba0156ee130fa88379a5a89de0812936a3d
https://github.com/llvm/llvm-project/commit/3bee9ba0156ee130fa88379a5a89de0812936a3d
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/test/CodeGen/AMDGPU/insert-skips-gfx12.mir
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.ll
Log Message:
-----------
AMDGPU/GFX12: Fix s_barrier_signal_isfirst for single-wave workgroups (#143634)
Barrier instructions are no-ops in single-wave workgroups. This includes
s_barrier_signal_isfirst, which will leave SCC unmodified.
Model this correctly (via an implicit use of SCC) and ensure SCC==1
before the barrier instruction (if the wave is the only one of the
workgroup, then it is the first).
---------
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
Commit: 633e740e3453bab06bf535830174c759100257f9
https://github.com/llvm/llvm-project/commit/633e740e3453bab06bf535830174c759100257f9
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/test/Driver/hip-thinlto.hip
M clang/test/Driver/openmp-offload-gpu.c
Log Message:
-----------
[Clang][AMDGPU][Driver] Add `avail-extern-gv-in-addrspace-to-local` option when ThinTLO is enabled (#144914)
On AMDGPU, we need an extra argument
`-avail-extern-gv-in-addrspace-to-local=3`
to privatize LDS global variables when ThinLTO is enabled.
Commit: baf35d7a829efb9688dc0aef6d1e161ef6bc5983
https://github.com/llvm/llvm-project/commit/baf35d7a829efb9688dc0aef6d1e161ef6bc5983
Author: William Huynh <William.Huynh at arm.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M libc/cmake/modules/LLVMLibCCompileOptionRules.cmake
Log Message:
-----------
[libc] Fix bug in LIBC_CONF_ERRNO_MODE being undefined (#144896)
A typo, set() instead of list() would cause the build to not define
LIBC_CONF_ERRNO_MODE, which would cause the wrong configuration to be
used.
Commit: 8631b4f1b4f30edd1f26b20e35b7367517aba359
https://github.com/llvm/llvm-project/commit/8631b4f1b4f30edd1f26b20e35b7367517aba359
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/lib/Optimizer/CodeGen/LowerRepackArrays.cpp
A flang/test/Integration/cold_array_repacking.f90
M flang/test/Transforms/lower-repack-arrays.fir
Log Message:
-----------
[flang] Set low probability for array repacking code. (#144830)
This allows LLVM to place the most probably cold blocks
that do the repacking out of the line of the potentially hot code.
Commit: 28808dda2c53a1dff1076cb83a9b91d0866ebf9a
https://github.com/llvm/llvm-project/commit/28808dda2c53a1dff1076cb83a9b91d0866ebf9a
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M flang/test/Integration/cold_array_repacking.f90
Log Message:
-----------
[flang] Fixed test added in #144830.
Commit: dc058a3d84ed1bc4006416023e8b336f3214bdc7
https://github.com/llvm/llvm-project/commit/dc058a3d84ed1bc4006416023e8b336f3214bdc7
Author: Kazu Hirata <kazu at google.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/utils/TableGen/ClangAttrEmitter.cpp
M clang/utils/TableGen/ClangDiagnosticsEmitter.cpp
Log Message:
-----------
[TableGen] Use ListSeparator (NFC) (#144936)
Note that an instance of ListSeparator evaluates to the empty string
for the first time and then ", " for subsequent references.
Commit: 7349864d2c7c874c17ed546791489a46e896f901
https://github.com/llvm/llvm-project/commit/7349864d2c7c874c17ed546791489a46e896f901
Author: Kazu Hirata <kazu at google.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/include/llvm/ADT/PointerIntPair.h
Log Message:
-----------
[ADT] Remove an extraneous variable (NFC) (#144937)
Without this patch, Int and IntWord have the same value and type.
This patch removes the extraneous copy.
Commit: 3b672e1d7b7375ca2a048cfb252d0e8ff35724e2
https://github.com/llvm/llvm-project/commit/3b672e1d7b7375ca2a048cfb252d0e8ff35724e2
Author: Kazu Hirata <kazu at google.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/unittests/ADT/TestGraph.h
M llvm/unittests/Support/Casting.cpp
Log Message:
-----------
[llvm] Use "= delete" to delete constructors (NFC) (#144938)
None of the constructors touched in this patch has a corresponding
definition. This patch explicitly deletes them with "= delete" while
moving them to the public section of respective classes. Note that "=
delete" itself serves as documentation.
Identified with modernize-use-equals-delete.
Commit: 03692aa40487d0f4090d329ca2904fb888242c94
https://github.com/llvm/llvm-project/commit/03692aa40487d0f4090d329ca2904fb888242c94
Author: Kazu Hirata <kazu at google.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/include/llvm/ProfileData/MemProfReader.h
Log Message:
-----------
[memprof] Use a lambda instead of std::bind (NFC) (#144940)
A lambda is a lot shorter than std::bind here.
Commit: 9fd22cb56d4c626769afd938e0f9ef6157164394
https://github.com/llvm/llvm-project/commit/9fd22cb56d4c626769afd938e0f9ef6157164394
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M flang/include/flang/Evaluate/tools.h
M flang/include/flang/Semantics/tools.h
M flang/lib/Evaluate/tools.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/tools.cpp
Log Message:
-----------
[flang][NFC] Move new code to right place (#144551)
Some new code was added to flang/Semantics that only depends on
facilities in flang/Evaluate. Move it into Evaluate and clean up some
minor stylistic problems.
Commit: 53336ad488c953d41e744d42873d712276be980f
https://github.com/llvm/llvm-project/commit/53336ad488c953d41e744d42873d712276be980f
Author: Ross Brunton <ross at codeplay.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M offload/liboffload/include/OffloadImpl.hpp
M offload/liboffload/src/OffloadImpl.cpp
M offload/liboffload/src/OffloadLib.cpp
M offload/tools/offload-tblgen/EntryPointGen.cpp
Log Message:
-----------
[Offload] Move (most) global state to an `OffloadContext` struct (#144494)
Rather than having a number of static local variables, we now use
a single `OffloadContext` struct to store global state. This is
initialised by `olInit`, but is never deleted (de-initialization of
Offload isn't yet implemented).
The error reporting mechanism has not been moved to the struct, since
that's going to cause issues with teardown (error messages must outlive
liboffload).
Commit: 2f3a8fd0b3322baac25e5595313413ed4cd1158f
https://github.com/llvm/llvm-project/commit/2f3a8fd0b3322baac25e5595313413ed4cd1158f
Author: lntue <lntue at google.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M libc/src/__support/FPUtil/FEnvImpl.h
M libc/src/__support/FPUtil/x86_64/FEnvImpl.h
Log Message:
-----------
[libc] Skip x87 floating point register and only update mxcsr for x86_64 targets when raising exceptions inside math functions. (#144951)
Updating x87 floating point register significantly affect the
performance of the functions.
All the floating point exception reads will merge the results from both
mxcsr and x87 registers anyway.
Commit: 53ea522d1b87c144a1faeffea62d50a4d9907a38
https://github.com/llvm/llvm-project/commit/53ea522d1b87c144a1faeffea62d50a4d9907a38
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[LV] Introduce and use VPBuilder::createScalarZExtOrTrunc [nfc] (#144946)
Reduce redundant code, make the flow slightly easier to read.
Commit: d3a2931d8af87c20aaede991acda0b5f313075c3
https://github.com/llvm/llvm-project/commit/d3a2931d8af87c20aaede991acda0b5f313075c3
Author: lntue <lntue at google.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M libc/src/math/generic/log2f.cpp
Log Message:
-----------
[libc] Use `raise_except_if_required` for log2f. (#144961)
Commit: a9d175f1735a508ac05ab48d83a99071ba97c10e
https://github.com/llvm/llvm-project/commit/a9d175f1735a508ac05ab48d83a99071ba97c10e
Author: Kazu Hirata <kazu at google.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/lib/CodeGen/CGBlocks.cpp
M clang/lib/CodeGen/CGCleanup.cpp
M clang/lib/CodeGen/CGDeclCXX.cpp
M clang/lib/CodeGen/CGException.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGExprConstant.cpp
M clang/lib/CodeGen/CGObjC.cpp
M clang/lib/CodeGen/CGObjCGNU.cpp
M clang/lib/CodeGen/CGObjCMac.cpp
M clang/lib/CodeGen/CGObjCRuntime.cpp
Log Message:
-----------
[CodeGen] Use range-based for loops (NFC) (#144939)
Commit: a8edda195c9fe0d48ee7f6f2438c9575ebbad7f2
https://github.com/llvm/llvm-project/commit/a8edda195c9fe0d48ee7f6f2438c9575ebbad7f2
Author: Kazu Hirata <kazu at google.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/ExecutionEngine/JITLink/COFFDirectiveParser.cpp
M llvm/lib/ExecutionEngine/Orc/UnwindInfoRegistrationPlugin.cpp
M llvm/lib/Linker/IRMover.cpp
M llvm/lib/Target/BPF/BPFPreserveStaticOffset.cpp
Log Message:
-----------
[llvm] Remove unused includes (NFC) (#144941)
These are identified by misc-include-cleaner. I've filtered out those
that break builds. Also, I'm staying away from llvm-config.h,
config.h, and Compiler.h, which likely cause platform- or
compiler-specific build failures.
Commit: dfb5cadf5e816e542e46d3f0551b6a148a93ce3d
https://github.com/llvm/llvm-project/commit/dfb5cadf5e816e542e46d3f0551b6a148a93ce3d
Author: Koakuma <koachan at protonmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/Sparc/Sparc.td
M llvm/lib/Target/Sparc/SparcInstrInfo.td
M llvm/test/CodeGen/SPARC/ctlz.ll
M llvm/test/CodeGen/SPARC/cttz.ll
M llvm/test/CodeGen/SPARC/inlineasm-v9.ll
M llvm/test/CodeGen/SPARC/inlineasm.ll
M llvm/test/MC/Sparc/Relocations/relocation-specifier.s
M llvm/test/MC/Sparc/sparcv9-instructions.s
Log Message:
-----------
[SPARC][IAS] Properly set implied feature sets for ISA levels/extensions (#143232)
Some SPARC ISA levels and/or extensions are defined in a way such that
the availability of it implies the availability of other, more fundamental
ISA features (for example, targeting 64-bit environment implies that
V9 instructions are available).
Properly set those in the TableGen definitions.
Fixes https://github.com/llvm/llvm-project/issues/142388.
Commit: b96370131d1572feb9c51442ac8ba1ccb16d7071
https://github.com/llvm/llvm-project/commit/b96370131d1572feb9c51442ac8ba1ccb16d7071
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[TTI] Plumb CostKind through getPartialReductionCost (#144953)
Purely for the sake of being idiomatic with other TTI costing routines,
no direct motivation beyond that.
Commit: d8e6d74c6905b3032a3dc9b686bd80bb3feb9857
https://github.com/llvm/llvm-project/commit/d8e6d74c6905b3032a3dc9b686bd80bb3feb9857
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV] Consider EVL legality for TTI tail folding preference (#144790)
Commit: dad64877c811dcce7e2c7ebc216161ecf0733fcf
https://github.com/llvm/llvm-project/commit/dad64877c811dcce7e2c7ebc216161ecf0733fcf
Author: Kazu Hirata <kazu at google.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/include/llvm/IR/IntrinsicInst.h
M llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
M llvm/lib/IR/IntrinsicInst.cpp
Log Message:
-----------
[llvm] Remove an extraneous cast (NFC) (#144955)
llvm::CallBase::getArgOperand returns Value *, so we do not need
const_cast<Value *>.
Commit: 6001a8bb945762fd128f025bb8d7969d92096772
https://github.com/llvm/llvm-project/commit/6001a8bb945762fd128f025bb8d7969d92096772
Author: Tianle Liu <tianle.l.liu at intel.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
A llvm/test/Transforms/WholeProgramDevirt/availableexternal-check.ll
Log Message:
-----------
[WholeProgramDevirt] Add check for AvailableExternal and give up icall.branch.funnel (#143468)
When a customer class inherits from a libc++ class, and is built with
"-flto -fwhole-program-vtables -static-libstdc++ \
-Wl,-plugin-opt=-whole-program-visibility", the libc++ class's vtable is
available_externally, meanwhile the customer class vtable is private.
And
both of them are !vcall_visibility == Linkage Unit.
In this case, icall.branch.funnel might be generated.
But the icall.branch.funnel would cause crash in LowerTypeTests because
available_externally Global_Object's GlobalTypeMember would not be
saved and finally leads to a NULL GlobalTypeMember which causes a crash.
Even saving the available_externally GO's GlobalTypeMember so that it is
not NULL to avoid the crash in LowerTypeTests, it still will crash in
SelectionDAGBuilder or Verifier, because operands linkage type
consistency
check of icall.branch.funnel can not pass.
So any one of available externally vtable would stop to generate
icall.branch.funnel.
This patch fixes FullLTO mode and split-LTO-unit ThinLTO mode.
Commit: 91439817e8d19613ac6e25ca9abd5e7534a9d33b
https://github.com/llvm/llvm-project/commit/91439817e8d19613ac6e25ca9abd5e7534a9d33b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
Log Message:
-----------
ARM: Avoid using isTarget wrappers around Triple predicates (#144705)
These are module level properties, and querying them through
a function-level subtarget context is confusing. Plus we don't
need an aliased name. This doesn't avoid all the uses, just the
ones in the TargetLowering constructor.
Commit: efd42b9b1d655a56abb3e6ce1ed4414e9f882912
https://github.com/llvm/llvm-project/commit/efd42b9b1d655a56abb3e6ce1ed4414e9f882912
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.cpp
Log Message:
-----------
WebAssembly: Stop directly using RuntimeLibcalls.def (#143054)
Construct RuntimeLibcallsInfo instead of manually creating a map.
This was repeating the setting of the RETURN_ADDRESS. This removes
an obstacle to generating libcall information with tablegen.
This is also not great, since it's setting a static map which
would be broken if there were ever a triple with a different libcall
configuration.
Commit: fa7646008ef32b38357189ed5752e1a1b8d6d146
https://github.com/llvm/llvm-project/commit/fa7646008ef32b38357189ed5752e1a1b8d6d146
Author: joaosaffran <126493771+joaosaffran at users.noreply.github.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Target/DirectX/DXILRootSignature.cpp
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Error-is-not-function.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Error-is-not-value.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Error-no-root-element-list.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Error-root-element-not-mdnode.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Flags-Error.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Flags.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-MultipleEntryFunctions.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-NullFunction-Error.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Parameters-Invalid-ParameterIsNotString.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Parameters-Validation-Error.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Parameters.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootConstants-Invalid-Num32BitValues.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootConstants-Invalid-RegisterSpace.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootConstants-Invalid-ShaderRegister.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootConstants.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor-Invalid-Flags.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor-Invalid-RegisterKind.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor-Invalid-RegisterSpace.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor-Invalid-RegisterValue.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor_V1.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootElement-Error.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootFlags-VisibilityValidationError.ll
Log Message:
-----------
[DirectX] Add Root Signature Version Support and Update Test IR Format (#144957)
Updates the Root Signature metadata parser to extract version
information. This requirement was added after the initial parser
implementation.
---------
Co-authored-by: joaosaffran <joao.saffran at microsoft.com>
Commit: 5cbed34404a3862c2d7f18e4b4b24f5ce1516a8d
https://github.com/llvm/llvm-project/commit/5cbed34404a3862c2d7f18e4b4b24f5ce1516a8d
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M clang/test/Preprocessor/predefined-arch-macros.c
M llvm/lib/Target/X86/X86.td
M llvm/lib/TargetParser/X86TargetParser.cpp
Log Message:
-----------
[X86] Remove CLDEMOTE from Arrowlake and later hybrid processors (#144833)
Decouple Arrowlake from Sierraforest because the later has CLDEMOTE
feature.
Commit: a05393a879b2950fccca66ff0e1b6c70c39838e4
https://github.com/llvm/llvm-project/commit/a05393a879b2950fccca66ff0e1b6c70c39838e4
Author: Jim Lin <jim at andestech.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV_nonstandard.def
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/RISCVInstrFormats.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
M llvm/test/MC/RISCV/custom_reloc.s
M llvm/test/MC/RISCV/vendor-symbol.s
A llvm/test/MC/RISCV/xandesperf-fixups-diagnostics.s
A llvm/test/MC/RISCV/xandesperf-relocation.s
Log Message:
-----------
[RISCV] Add symbol parsing support for XAndesPerf branch instructions (#137748)
This patch adds support for parsing symbols in the XAndesPerf branch
immediate instructions. The branch immediate instructions use
`R_RISCV_NDS_BRANCH_10` relocation. It uses a 10-bit PC-relative branch
offset.
Commit: 513bcf6d012f7f9483af784de8487ee04cb9971a
https://github.com/llvm/llvm-project/commit/513bcf6d012f7f9483af784de8487ee04cb9971a
Author: Fangrui Song <i at maskray.me>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
A llvm/test/tools/yaml2obj/basic.test
M llvm/tools/yaml2obj/yaml2obj.cpp
Log Message:
-----------
[yaml2obj] Report error when the input filename does not exist
I invoked yaml2obj with a mistyped filename and received no error
message. I nearly thought the program had succeeded, but the shell's
exit code prompt tipped me off.
Pull Request: https://github.com/llvm/llvm-project/pull/144835
Commit: 4f991cc99523e4bb7a0d96cee9f5c3a64bf2bc8e
https://github.com/llvm/llvm-project/commit/4f991cc99523e4bb7a0d96cee9f5c3a64bf2bc8e
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M lldb/include/lldb/Host/Socket.h
M lldb/source/Host/common/Socket.cpp
M lldb/test/API/tools/lldb-dap/server/TestDAP_server.py
M lldb/tools/lldb-dap/Options.td
M lldb/tools/lldb-dap/src-ts/lldb-dap-server.ts
M lldb/tools/lldb-dap/tool/lldb-dap.cpp
Log Message:
-----------
[lldb-dap] Make connection URLs match lldb (#144770)
Use the same scheme as ConnectionFileDescriptor::Connect and use
"listen" and "accept". Addresses feedback from a Pavel in a different PR
[1].
[1] https://github.com/llvm/llvm-project/pull/143628#discussion_r2152225200
Commit: 50c5ecd35402dc734f2a462df5532e77a5ce12b2
https://github.com/llvm/llvm-project/commit/50c5ecd35402dc734f2a462df5532e77a5ce12b2
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M clang/include/clang/Serialization/ASTReader.h
Log Message:
-----------
[NFC] [Serialization] Remove a useless comment
The comments belongs to other WIP patches.
Commit: bb51c5d4b85a655e8c90247a6678e507402703a4
https://github.com/llvm/llvm-project/commit/bb51c5d4b85a655e8c90247a6678e507402703a4
Author: Ming Yan <99472920+NexMing at users.noreply.github.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
Log Message:
-----------
[SDPatternMatch] Add m_Poison matcher (#144860)
Add SDPatternMatch matcher and unit test coverage for ISD::POISON opcode
e.g.
```
m_InsertElt(m_Poison(), m_Value(), m_Zero())
```
Commit: 64fe3236476a9a85977abf5489414bbb2de2109c
https://github.com/llvm/llvm-project/commit/64fe3236476a9a85977abf5489414bbb2de2109c
Author: Kazu Hirata <kazu at google.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[llvm] Migrate away from ArrayRef(std::nullopt) (NFC) (#144967)
ArrayRef has a constructor that accepts std::nullopt. This
constructor dates back to the days when we still had llvm::Optional.
Since the use of std::nullopt outside the context of std::optional is
kind of abuse and not intuitive to new comers, I would like to move
away from the constructor and eventually remove it.
This patch takes care of the llvm side of the migration.
Commit: 69974658f079cec82a9fc13dd4993ab1e072c811
https://github.com/llvm/llvm-project/commit/69974658f079cec82a9fc13dd4993ab1e072c811
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/include/clang/Basic/OffloadArch.h
M clang/lib/Basic/OffloadArch.cpp
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M clang/test/Driver/amdgpu-macros.cl
M clang/test/Driver/amdgpu-mcpu.cl
M clang/test/Misc/target-invalid-cpu-note/amdgcn.c
M clang/test/Misc/target-invalid-cpu-note/nvptx.c
M llvm/docs/AMDGPUUsage.rst
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/TargetParser/TargetParser.h
M llvm/lib/Object/ELFObjectFile.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNProcessors.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll
M llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
M llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll
M llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test
M llvm/tools/llvm-readobj/ELFDumper.cpp
Log Message:
-----------
[AMDGPU] Initial support for gfx1250 target. (#144965)
This is just a stub for now.
Commit: b8d3efa189620bfd48dab5fb05b923560fb1e2d5
https://github.com/llvm/llvm-project/commit/b8d3efa189620bfd48dab5fb05b923560fb1e2d5
Author: Maksim Panchenko <maks at fb.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M bolt/lib/Rewrite/LinuxKernelRewriter.cpp
M bolt/test/X86/linux-version.S
Log Message:
-----------
[BOLT][Linux] Fix linux_banner lookup (#144962)
While detecting the Linux kernel version, look for `linux_banner` symbol
with local visibility if the global one was not found.
Fixes #144847
Commit: 7cbb1411550ef6caab18a9360f1549d6029ffe86
https://github.com/llvm/llvm-project/commit/7cbb1411550ef6caab18a9360f1549d6029ffe86
Author: Kazu Hirata <kazu at google.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/include/clang/AST/TypeProperties.td
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTDiagnostic.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/QualTypeNames.cpp
M clang/lib/Basic/Targets/Xtensa.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/TreeTransform.h
Log Message:
-----------
[clang] Migrate away from ArrayRef(std::nullopt) (NFC) (#144982)
ArrayRef has a constructor that accepts std::nullopt. This
constructor dates back to the days when we still had llvm::Optional.
Since the use of std::nullopt outside the context of std::optional is
kind of abuse and not intuitive to new comers, I would like to move
away from the constructor and eventually remove it.
This patch takes care of the clang side of the migration.
Commit: 0f302f38b0014a0018031ffb3cb898fdc7d90880
https://github.com/llvm/llvm-project/commit/0f302f38b0014a0018031ffb3cb898fdc7d90880
Author: no92 <no92 at users.noreply.github.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M clang/lib/Basic/Targets.cpp
M clang/lib/Basic/Targets/OSTargets.h
M clang/lib/Driver/CMakeLists.txt
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
A clang/lib/Driver/ToolChains/Managarm.cpp
A clang/lib/Driver/ToolChains/Managarm.h
M clang/lib/Lex/InitHeaderSearch.cpp
A clang/test/Driver/Inputs/basic_managarm_tree/lib/aarch64-managarm-mlibc/.keep
A clang/test/Driver/Inputs/basic_managarm_tree/lib/riscv64-managarm-mlibc/.keep
A clang/test/Driver/Inputs/basic_managarm_tree/lib/x86_64-managarm-mlibc/.keep
A clang/test/Driver/Inputs/basic_managarm_tree/lib64/aarch64-managarm-mlibc/.keep
A clang/test/Driver/Inputs/basic_managarm_tree/lib64/riscv64-managarm-mlibc/.keep
A clang/test/Driver/Inputs/basic_managarm_tree/lib64/x86_64-managarm-mlibc/.keep
A clang/test/Driver/Inputs/basic_managarm_tree/usr/include/aarch64-managarm-mlibc/c++/10/.keep
A clang/test/Driver/Inputs/basic_managarm_tree/usr/include/c++/10/.keep
A clang/test/Driver/Inputs/basic_managarm_tree/usr/include/c++/v1/.keep
A clang/test/Driver/Inputs/basic_managarm_tree/usr/include/riscv64-managarm-mlibc/c++/10/.keep
A clang/test/Driver/Inputs/basic_managarm_tree/usr/include/x86_64-managarm-mlibc/c++/10/.keep
A clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/aarch64-managarm-mlibc/.keep
A clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/gcc/aarch64-managarm-mlibc/10/crtbegin.o
A clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/gcc/aarch64-managarm-mlibc/10/crtbeginS.o
A clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/gcc/aarch64-managarm-mlibc/10/crtbeginT.o
A clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/gcc/riscv64-managarm-mlibc/10/crtbegin.o
A clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/gcc/riscv64-managarm-mlibc/10/crtbeginS.o
A clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/gcc/riscv64-managarm-mlibc/10/crtbeginT.o
A clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/gcc/x86_64-managarm-mlibc/10/crtbegin.o
A clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/gcc/x86_64-managarm-mlibc/10/crtbeginS.o
A clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/gcc/x86_64-managarm-mlibc/10/crtbeginT.o
A clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/riscv64-managarm-mlibc/.keep
A clang/test/Driver/Inputs/basic_managarm_tree/usr/lib/x86_64-managarm-mlibc/.keep
A clang/test/Driver/Inputs/basic_managarm_tree/usr/lib64/.keep
A clang/test/Driver/managarm.cpp
M clang/test/Preprocessor/init.c
M clang/test/Preprocessor/predefined-macros-no-warnings.c
Log Message:
-----------
[clang] Add managarm support (#144791)
This is a repost of the quickly reverted #139271. The failing buildbot
tests have been fixed and pass on my machine now.
Commit: 06e08f38e1ec57bf3cb5e08569b52eb6a3c3e166
https://github.com/llvm/llvm-project/commit/06e08f38e1ec57bf3cb5e08569b52eb6a3c3e166
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/unsupported-cc-call.ll
A llvm/test/CodeGen/AArch64/unsupported-cc-func.ll
M llvm/test/MC/AArch64/coff-function-type-info.ll
Log Message:
-----------
AArch64: Use reportFatalUsageError for unsupported calling conv (#144840)
This probably should emit a DiagnosticInfoUnsupported and use the
default calling convention instead, but then we would need to pass
in the context.
Also move where CCAssignFnForCall is called. It was unnecessarily
called for each argument, so the error wouldn't trigger for functions
with 0 arguments.
This only ensures the error occurs for functions defined with the
calling convention. The error is still missed for outgoing calls
with no arguments. The lowering logic here is convoluted, calling
CCAssignFnForCall for each argument and it does not mirror
LowerFormalArguments so I'm not sure what's going on here.
Commit: 090f409538d2b426f11ce5aa22af8c243099aecf
https://github.com/llvm/llvm-project/commit/090f409538d2b426f11ce5aa22af8c243099aecf
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Driver/BUILD.gn
Log Message:
-----------
[gn build] Port 0f302f38b001
Commit: d196124dd22391f6c967ed569b34632840536c45
https://github.com/llvm/llvm-project/commit/d196124dd22391f6c967ed569b34632840536c45
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Utils/PredicateInfo.cpp
Log Message:
-----------
[PredicateInfo] Remove unnecessary EdgeUsesOnly set (NFC) (#144912)
As far as I can tell, this set is pointless: It just represents whether
the target block has multiple predecessors, and the way it is
constructed and queried, we're not even reducing the number of
getSinglePredecessor() calls or something like that.
Commit: cbb5e244f7564091f9169f525fd8456e68bc028a
https://github.com/llvm/llvm-project/commit/cbb5e244f7564091f9169f525fd8456e68bc028a
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Utils/PredicateInfo.cpp
Log Message:
-----------
[PredicateInfo] Remove redundant EdgeOnly member (NFC)
EdgeOnly indicates a phi def, which can already be identified by
LN_Last with non-null PInfo. Most of the code already reasons in
terms of LN_Last instead of EdgeOnly.
Commit: 1cae21da47b1f53c3946534b12507a035fb283d2
https://github.com/llvm/llvm-project/commit/1cae21da47b1f53c3946534b12507a035fb283d2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
Log Message:
-----------
AMDGPU: Remove legacy PM version of AMDGPUPromoteAllocaToVector (#144986)
This is only run in the middle end with the new pass manager now,
so garbage collect the old PM version.
Commit: c361bffa50f1ed790c393ffbab39c2e07dfcb242
https://github.com/llvm/llvm-project/commit/c361bffa50f1ed790c393ffbab39c2e07dfcb242
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUUnifyMetadata.cpp
Log Message:
-----------
AMDGPU: Remove legacy pass manager version of AMDGPUUnifyMetadata (#144985)
This is only run in the new pass manager now.
Commit: 8973be462c49a7b0a24c61f41e07a721706b1ad8
https://github.com/llvm/llvm-project/commit/8973be462c49a7b0a24c61f41e07a721706b1ad8
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Utils/PredicateInfo.cpp
Log Message:
-----------
[PredicateInfo] Avoid duplicate stack in scope check (NFC)
popStackUntilDFSScope() is going to check this itself, there is
no need to do it in advance as well.
Commit: bc14e5e5e9c717a7699cf10b13a7661a9e033594
https://github.com/llvm/llvm-project/commit/bc14e5e5e9c717a7699cf10b13a7661a9e033594
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/test/MC/AMDGPU/gfx12_asm_smem.s
M llvm/test/MC/AMDGPU/gfx12_asm_sopk.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_smem.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp8.txt
Log Message:
-----------
[AMDGPU] Add trivial gfx1250 runlines to MC tests. NFC. (#144988)
Commit: b6b8fa3b15d334c51fcf8763ccda0102a01aeb9c
https://github.com/llvm/llvm-project/commit/b6b8fa3b15d334c51fcf8763ccda0102a01aeb9c
Author: int-zjt <zhangjiatong.0 at bytedance.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
A compiler-rt/test/profile/Posix/gcov-file-change-line.cpp
M compiler-rt/test/profile/Posix/gcov-file-change.cpp
M llvm/include/llvm/ProfileData/GCOV.h
M llvm/lib/ProfileData/GCOV.cpp
M llvm/lib/Transforms/Instrumentation/GCOVProfiling.cpp
Log Message:
-----------
[llvm-cov][gcov] Support multi-files coverage in one basic block (#144504)
In the current gcov implementation, all lines within a basic block are
attributed to the source file of the block's containing function. This
is inaccurate when a block contains lines from other files (e.g., via
#include "foo.inc").
Commit
[406e81b](https://github.com/llvm/llvm-project/commit/406e81b79d26dae6838cc69d10a3e22635da09ef)
attempted to address this by filtering lines based on debug info types,
but this approach has two limitations:
* **Over-filtering**: Some valid lines belonging to the function are
incorrectly excluded.
* **Under-counting**: Lines not belonging to the function are filtered
out and omitted from coverage statistics.
**GCC Reference Behavior**
GCC's gcov implementation handles this case correctly.This change aligns
the LLVM behavior with GCC.
**Proposed Solution**
1. **GCNO Generation**:
* **Current**: Each block stores a single GCOVLines record (filename +
lines).
* **New**: Dynamically create new GCOVLines records whenever consecutive
lines in a block originate from different source files. Group subsequent
lines from the same file under one record.
2. **GCNO Parsing**:
* **Current**: Lines are directly attributed to the function's source
file.
* **New**: Introduce a GCOVLocation type to track filename/line mappings
within blocks. Statistics will reflect the actual source file for each
line.
Commit: 874773635d31501ab21812c05c44caf281c1acc7
https://github.com/llvm/llvm-project/commit/874773635d31501ab21812c05c44caf281c1acc7
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP] NFC: Simplify CandidateVFs initialization (#144882)
Also adds a comment to clarify the meaning of MaxRegVF.
Commit: 14e89b061fdecedcec4bb035060a56588610cb5c
https://github.com/llvm/llvm-project/commit/14e89b061fdecedcec4bb035060a56588610cb5c
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M clang/lib/Sema/SemaModule.cpp
A clang/test/Modules/pr144230.cppm
Log Message:
-----------
[C++20] [Modules] Add exported modules as transitive imported modules
Close https://github.com/llvm/llvm-project/issues/144230
The root cause of the problem is, when we decide the transitive imports,
we didn't deal with exported imports.
Commit: f704782c63ac1d567422f66072bebd49c41723f9
https://github.com/llvm/llvm-project/commit/f704782c63ac1d567422f66072bebd49c41723f9
Author: Matthew Devereau <matthew.devereau at arm.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
Log Message:
-----------
[AArch64][SelectionDAG] Fix UDOT regression (#144907)
Fix broken check in AArch64ISelLowering for bailing from ZExt
optimizations when there is a partial reduction intrinsic.
Commit: b85387dfe8e67ee8a142a1faf25325761c343577
https://github.com/llvm/llvm-project/commit/b85387dfe8e67ee8a142a1faf25325761c343577
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
Log Message:
-----------
[SCCP] Check instruction type before querying PredicateInfo (NFC)
Do the cheap intrinsic check before the hash lookup for the
PredicateInfo.
Commit: eb0f1dc00e5d0e591fe912c1aaf9dd9d01d94b8d
https://github.com/llvm/llvm-project/commit/eb0f1dc00e5d0e591fe912c1aaf9dd9d01d94b8d
Author: Peter Smith <peter.smith at arm.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M lld/ELF/Thunks.cpp
M lld/test/ELF/aarch64-thunk-bti-multipass.s
Log Message:
-----------
[LLD][ELF] Include offset when adding Thunk symbols (#144995)
Include the offset of a thunk in the ThunkSection when adding symbols.
At Thunk creation time the offset is set to 0 as we don't know where in
the ThunkSection the Thunk will end up. The symbol values are updated by
the setOffset() call in assignOffsets().
When we transform a thunk from a short to a long, we sometimes add a
mapping symbol. At this point the offset of the thunk is non zero and we
need to account for that when defining the symbol, as the setOffset()
call subtracts the offset before adding the new one back in.
To test; added a second thunk that is converted to a long thunk to
aarch64-thunk-bit-multipass. This second thunk is given a non zero
offset from the start of the Thunk Section so we can observe the mapping
symbol being put in the wrong place without accounting for the offset.
fixes: https://github.com/llvm/llvm-project/issues/142326
Commit: 61972054f3fcaf59096799342bac9c93dd9aa432
https://github.com/llvm/llvm-project/commit/61972054f3fcaf59096799342bac9c93dd9aa432
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/CodeGen/MachineBlockPlacement.cpp
M llvm/test/CodeGen/RISCV/branch.ll
Log Message:
-----------
[CodeGen] Limit number of analyzed predecessors
MachineBlockPlacement has quadratic runtime in the number of
predecessors: in some situation, for an edge, all predecessors of the
successor are considered.
Limit the number of considered predecessors to bound compile time for
large functions.
Pull Request: https://github.com/llvm/llvm-project/pull/142584
Commit: f577516d91dc1ae5b9c8a3bcad81558bc19ccf65
https://github.com/llvm/llvm-project/commit/f577516d91dc1ae5b9c8a3bcad81558bc19ccf65
Author: Matthias Springer <me at m-sp.org>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
Log Message:
-----------
[mlir][arith] Add back ElementwiseMappable to `arith.trunci` (#145000)
This trait was accidentally dropped in #144863.
Commit: dd4776d429bd20050c80749f669367a0574520c8
https://github.com/llvm/llvm-project/commit/dd4776d429bd20050c80749f669367a0574520c8
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Log Message:
-----------
AMDGPU: Remove AMDGPUInstrInfo class (#144984)
This was never constructed and only provided one static helper
function.
Commit: f75973949b0e51eb4b3852c903d08bc72bf5d459
https://github.com/llvm/llvm-project/commit/f75973949b0e51eb4b3852c903d08bc72bf5d459
Author: Ádám Kallai <kadam at inf.u-szeged.hu>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/include/bolt/Utils/CommandLineOpts.h
M bolt/lib/Profile/DataAggregator.cpp
A bolt/test/perf2bolt/AArch64/perf2bolt-spe.test
A bolt/test/perf2bolt/X86/perf2bolt-spe.test
M bolt/tools/driver/llvm-bolt.cpp
M bolt/unittests/Profile/CMakeLists.txt
A bolt/unittests/Profile/PerfSpeEvents.cpp
Log Message:
-----------
[BOLT][AArch64] Add support for SPE brstack format (#129231)
Since Linux 6.14, Perf gained the ability to report SPE branch events
using the `brstack` format, which matches the layout of LBR/BRBE.
This patch reuses the existing LBR parsing logic to support SPE.
Example SPE brstack format:
```bash
perf script -i perf.data -F pid,brstack --itrace=bl
```
```
PID FROM / TO / PREDICTED
16984 0x72e342e5f4/0x72e36192d0/M/-/-/11/RET/-
16984 0x72e7b8b3b4/0x72e7b8b3b8/PN/-/-/11/COND/-
16984 0x72e7b92b48/0x72e7b92b4c/PN/-/-/8/COND/-
16984 0x72eacc6b7c/0x760cc94b00/P/-/-/9/RET/-
16984 0x72e3f210fc/0x72e3f21068/P/-/-/4//-
16984 0x72e39b8c5c/0x72e3627b24/P/-/-/4//-
16984 0x72e7b89d20/0x72e7b92bbc/P/-/-/4/RET/-
```
SPE brstack flags can be two characters long: `PN` or `MN`:
- `P` = predicted branch
- `M` = mispredicted branch
- `N` = optionally appears when the branch is NOT-TAKEN
- flag is relevant only to conditional branches
Example of usage with BOLT:
1. Capture SPE branch events:
```bash
perf record -e 'arm_spe_0/branch_filter=1/u' -- binary
```
2. Convert profile for BOLT:
```bash
perf2bolt -p perf.data -o perf.fdata --spe binary
```
3. Run BOLT Optimization:
```bash
llvm-bolt binary -o binary.bolted --data perf.fdata ...
```
A unit test verifies the parsing of the 'SPE brstack format'.
---------
Co-authored-by: Paschalis Mpeis <paschalis.mpeis at arm.com>
Commit: 238abf8ba8233ec0f2dab57a3bacbd192e78f8b6
https://github.com/llvm/llvm-project/commit/238abf8ba8233ec0f2dab57a3bacbd192e78f8b6
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/utils/gn/secondary/bolt/unittests/Profile/BUILD.gn
Log Message:
-----------
[gn build] Port f75973949b0e
Commit: 95bd05d7cae327e431ccdaf0a452a0573ade5357
https://github.com/llvm/llvm-project/commit/95bd05d7cae327e431ccdaf0a452a0573ade5357
Author: Matthias Springer <me at m-sp.org>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M mlir/lib/Conversion/FuncToLLVM/FuncToLLVM.cpp
Log Message:
-----------
[mlir][Func][NFC] Simplify implementation after #144706 (#145006)
Commit: a5fa5bd2a890c588b99b07fc0f3fcef236888609
https://github.com/llvm/llvm-project/commit/a5fa5bd2a890c588b99b07fc0f3fcef236888609
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/test/CodeGen/X86/ptest.ll
Log Message:
-----------
[X86] ptest.ll - add test coverage for #144861 load chains
Commit: 7085065c02da6091dca91be201160912e43a63ec
https://github.com/llvm/llvm-project/commit/7085065c02da6091dca91be201160912e43a63ec
Author: Amir Ayupov <aaupov at fb.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/lib/Profile/DataAggregator.cpp
M bolt/test/X86/callcont-fallthru.s
M bolt/test/link_fdata.py
Log Message:
-----------
[BOLT] Support pre-aggregated returns (#143296)
Intel's Architectural LBR supports capturing branch type information
as part of LBR stack (SDM Vol 3B, part 2, October 2024):
```
20.1.3.2 Branch Types
The IA32_LBR_x_INFO.BR_TYPE and IA32_LER_INFO.BR_TYPE fields encode
the branch types as shown in Table 20-3.
Table 20-3. IA32_LBR_x_INFO and IA32_LER_INFO Branch Type Encodings
Encoding | Branch Type
0000B | COND
0001B | NEAR_IND_JMP
0010B | NEAR_REL_JMP
0011B | NEAR_IND_CALL
0100B | NEAR_REL_CALL
0101B | NEAR_RET
011xB | Reserved
1xxxB | OTHER_BRANCH
For a list of branch operations that fall into the categories above,
see Table 20-2.
Table 20-2. Branch Type Filtering Details
Branch Type | Operations Recorded
COND | Jcc, J*CXZ, and LOOP*
NEAR_IND_JMP | JMP r/m*
NEAR_REL_JMP | JMP rel*
NEAR_IND_CALL | CALL r/m*
NEAR_REL_CALL | CALL rel* (excluding CALLs to the next sequential IP)
NEAR_RET | RET (0C3H)
OTHER_BRANCH | JMP/CALL ptr*, JMP/CALL m*, RET (0C8H), SYS*,
interrupts, exceptions (other than debug exceptions), IRET, INT3,
INTn, INTO, TSX Abort, EENTER, ERESUME, EEXIT, AEX, INIT, SIPI, RSM
```
Linux kernel can preserve branch type when `save_type` is enabled,
even if CPU does not support Architectural LBR:
https://github.com/torvalds/linux/blob/f09079bd04a924c72d555cd97942d5f8d7eca98c/tools/perf/Documentation/perf-record.txt#L457-L460
> - save_type: save branch type during sampling in case binary is not
available later.
For the platforms with Intel Arch LBR support (12th-Gen+ client or
4th-Gen Xeon+ server), the save branch type is unconditionally enabled
when the taken branch stack sampling is enabled.
Kernel-reported branch type values:
https://github.com/torvalds/linux/blob/8c6bc74c7f8910ed4c969ccec52e98716f98700a/include/uapi/linux/perf_event.h#L251-L269
This information is needed to disambiguate external returns (from
DSO/JIT) to an entry point or a landing pad, when BOLT can't
disassemble the branch source.
This patch adds new pre-aggregated types:
- return trace (R),
- external return fall-through (r).
For such types, the checks for fall-through start (not an entry or
a landing pad) are relaxed.
Depends on #143295.
Test Plan: updated callcont-fallthru.s
Commit: 00c18d04ab6341022867d3b6674ec3ab30e5de2c
https://github.com/llvm/llvm-project/commit/00c18d04ab6341022867d3b6674ec3ab30e5de2c
Author: Nicolas Vasilache <Nico.Vasilache at amd.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td
M mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt
A mlir/lib/Dialect/Linalg/Transforms/PadTilingInterface.cpp
A mlir/test/Dialect/Linalg/transform-op-pad-tiling-interface-multiple-of.mlir
A mlir/test/Dialect/Linalg/transform-op-pad-tiling-interface.mlir
Log Message:
-----------
[mlir][Transforms] Add a PadTilingInterface transformation and hook i… (#144991)
…t up to the transform dialect
This revision revisits the padding transformation from first principles
and prepares it to work more generally with TilingInterface.
Compared to structured.transform.pad it has the following differences:
- no support for nofold, copy-back, transpose and hoisting: these have
been carried by the padding op in the very early days of StructuredOps
and have since then been separated out as independent transformations
that compose.
- no conflated static bounding box derivation attempts:
pad_tiling_interface composes more naturally with or without tiling.
- properly derives padding size on outputs where multiple dimensions
contribute: this is not supported in structured.transform.pad
- geared towards supporting TilingInterface once the proper control
mechanisms are supported through a PadSizeComputationFunction (supports
LinalgOp by default)
This will gradually replace structured.transform.pad as it is fleshed
out and tested more comprehensively.
In the future this should be moved out of a specific Linalg
implementation file and into a more general "Structured" file.
Commit: 7af545237f8509d40b9ab1dd6526210e09bc76bf
https://github.com/llvm/llvm-project/commit/7af545237f8509d40b9ab1dd6526210e09bc76bf
Author: Nicolas Vasilache <Nico.Vasilache at amd.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M mlir/test/Dialect/Linalg/transform-op-pad-tiling-interface-multiple-of.mlir
Log Message:
-----------
[NFC] Update transform-op-pad-tiling-interface-multiple-of.mlir
Missing NL
Commit: 227cd56e1330e51bc48f4fd71fabfc203b7ca31d
https://github.com/llvm/llvm-project/commit/227cd56e1330e51bc48f4fd71fabfc203b7ca31d
Author: Nicolas Vasilache <Nico.Vasilache at amd.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M mlir/test/Dialect/Linalg/transform-op-pad-tiling-interface.mlir
Log Message:
-----------
[NFC] Update transform-op-pad-tiling-interface.mlir
Missing NL
Commit: 68732ce8e01938227378b4e6f7850ba85c978726
https://github.com/llvm/llvm-project/commit/68732ce8e01938227378b4e6f7850ba85c978726
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/sve-bf16-reductions.ll
Log Message:
-----------
[LLVM][CodeGen][SVE] Add isel for bfloat unordered reductions. (#143540)
The omissions are VECREDUCE_SEQ_* and MUL. The former goes down a
different code path and the latter is unsupported across all element types.
Commit: 4ec6d127c1857e77d70236b15b03d23ba1283a3d
https://github.com/llvm/llvm-project/commit/4ec6d127c1857e77d70236b15b03d23ba1283a3d
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/test/CodeGen/X86/movmsk-cmp.ll
Log Message:
-----------
[X86] movmsk-cmp.ll - regenerate VPTERNLOG asm comments
Commit: 3e99aa6c0a36ec4d6f126882b1a06436767cbf73
https://github.com/llvm/llvm-project/commit/3e99aa6c0a36ec4d6f126882b1a06436767cbf73
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Utils/PredicateInfo.cpp
Log Message:
-----------
[PredicateInfo] Clean up DFS sorting (NFC) (#144943)
The comparison function for ValueDFS was confused in a number of ways.
Most significantly, it had a bunch of logic based on Def -- however, Def
is always null during sorting, it only gets set later. At this point
defs only have PInfo set.
Clean up the implementation to remove various dead code.
Commit: cbd496581fb6953a9a8d8387a010cc3a67d4654b
https://github.com/llvm/llvm-project/commit/cbd496581fb6953a9a8d8387a010cc3a67d4654b
Author: Chris Jackson <chris.jackson at amd.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
Log Message:
-----------
[NFC][AMDGPU] Automate any_extend_vector_inreg.ll check line generation (#145013)
Convert the test to use update_llc_test_checks.py.
Commit: e5559ca45f211f2cdd9c81e46935afe1cc2e22ab
https://github.com/llvm/llvm-project/commit/e5559ca45f211f2cdd9c81e46935afe1cc2e22ab
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M flang/lib/Lower/CMakeLists.txt
A flang/lib/Lower/OpenMP/Atomic.cpp
A flang/lib/Lower/OpenMP/Atomic.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
Log Message:
-----------
[flang][OpenMP] Move lowering of ATOMIC to separate file, NFC (#144960)
Commit: 1b83f10072b322a206ffcaf737b42fe5c2d95b89
https://github.com/llvm/llvm-project/commit/1b83f10072b322a206ffcaf737b42fe5c2d95b89
Author: Vigneshwar Jayakumar <vigneshwar.jayakumar at amd.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/test/CodeGen/AMDGPU/machine-sink-ignorable-exec-use.mir
Log Message:
-----------
[AMDGPU] Fix to prevent sinking of PERMLANE_SWAP instruction (#144423)
Permlane_swap instruction depends on exec mask, added isConvergent flag
to prevent sinking of instruction.
Fixes: SWDEV-537232
Commit: e8be733a3c3347207c162fc83e8dbe02dad2a952
https://github.com/llvm/llvm-project/commit/e8be733a3c3347207c162fc83e8dbe02dad2a952
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/vplan-printing.ll
Log Message:
-----------
[VPlan] Remove redundant ExtractLastElement from vector-to-scalar VPI.
Recipes that are vector-to-scalar are guaranteed to generate a scalar
value, so the extract is redundant after VPlan unrolling. Remove it.
This removes unneeded ExtractLastElement VPInstruction of reduction
result computations.
Commit: 8650c801381d5640018a2fab32932ee41ad27797
https://github.com/llvm/llvm-project/commit/8650c801381d5640018a2fab32932ee41ad27797
Author: NimishMishra <42909663+NimishMishra at users.noreply.github.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
Log Message:
-----------
[flang][OpenMP] Do not skip privatization of linear variable if it is OmpPreDetermined (#144315)
Current implementation of linear clause skips privatisation of all
linear variables during the FIR generation phase, since linear variables
are handled in their entirety by the OpenMP IRBuilder. However,
"implicit" linear variables (like OmpPreDetermined) cannot be skipped,
since FIR generation requires privatized symbols. This patch adds checks
to skip the same.
Fixes https://github.com/llvm/llvm-project/issues/142935
Commit: e970f59e6b20dddc4369735affb79ca9be240c1c
https://github.com/llvm/llvm-project/commit/e970f59e6b20dddc4369735affb79ca9be240c1c
Author: NimishMishra <42909663+NimishMishra at users.noreply.github.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
R flang/test/Lower/OpenMP/wsloop-linear.f90
Log Message:
-----------
[flang][OpenMP] Reintroduce TODO for FIR lowering of linear clause (#144883)
Current design of the linear clause lowering and translation shifts all
responsibility for handling the clause (like privatisation, linear
stepping, finalisation, and emission of synchronisation barriers) to the
IRBuilder. However in certain corner cases (like associated loops in or
before OpenMP version 4.5), variables are are implicitly linear. This
currently causes a problem with the existing linear clause
implementation. Hence, re-introduce TODO on the linear clause until the
linear clause lowering/translation are robust enough to handle such
cases as well.
Fixes https://github.com/llvm/llvm-project/issues/142935
Commit: a5b1093f782729014604f3208550de7400c518ac
https://github.com/llvm/llvm-project/commit/a5b1093f782729014604f3208550de7400c518ac
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td
M mlir/test/Transforms/remove-dead-values.mlir
Log Message:
-----------
[MLIR] Add ReturnLike trait to memref.atomic_yield (#144932)
Without this, the yield isn't considered as the region terminator and
the dataflow framework does not consider it live.
Commit: 5835f1e0a33afcae46a6ca4854373785eb3e7fd6
https://github.com/llvm/llvm-project/commit/5835f1e0a33afcae46a6ca4854373785eb3e7fd6
Author: Tobias Stadler <mail at stadler-tobias.de>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/test/CodeGen/X86/remarks-section.ll
Log Message:
-----------
[AsmPrinter] Fix crash when remarks section is unsupported (#144724)
Emit a warning and bail out instead of segfault-ing when the current
object file format does not have support for emitting a remarks section.
Commit: fd97dfbb78e3c9aea16873617b6d61b5b8a64474
https://github.com/llvm/llvm-project/commit/fd97dfbb78e3c9aea16873617b6d61b5b8a64474
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/dereferenceable-info-from-assumption-constant-size.ll
M llvm/test/Transforms/LoopVectorize/dereferenceable-info-from-assumption-variable-size.ll
M llvm/test/Transforms/LoopVectorize/load-deref-pred-poison-ub-ops-feeding-pointer.ll
Log Message:
-----------
[LV] Don't mark ptrs as safe to speculate if fed by UB/poison op. (#143204)
Add additional checks before marking pointers safe to load
speculatively. If some computations feeding the pointer may trigger UB,
we cannot load the pointer speculatively, because we cannot compute the
address speculatively. The UB triggering instructions will be
predicated, but if the predicated block does not execute the result is
poison.
Similarly, we also cannot load the pointer speculatively if it may be
poison. The patch also checks if any of the operands defined outside the
loop may be poison when entering the loop. We *don't* need to check if
any operation inside the loop may produce poison due to flags, as those
will be dropped if needed.
There are some types of instructions inside the loop that can produce
poison independent of flags. Currently loads are also checked, not sure
if there's a convenient API to check for all such operands.
Fixes https://github.com/llvm/llvm-project/issues/142957.
PR: https://github.com/llvm/llvm-project/pull/143204
Commit: 6c0ac888c59ca34a7f4e1dc2702b30e0db5cbac3
https://github.com/llvm/llvm-project/commit/6c0ac888c59ca34a7f4e1dc2702b30e0db5cbac3
Author: Matthias Springer <me at m-sp.org>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
Log Message:
-----------
[mlir][arith][NFC] Remove redundant trait declaration (#145007)
`Arith_Op` already declares the `ElementwiseMappable` traits, so they
don't have to be declared for `arith.select`.
Commit: 6edf2eb36470b623597668a7a97153544f568a40
https://github.com/llvm/llvm-project/commit/6edf2eb36470b623597668a7a97153544f568a40
Author: Artemiy Bulavin <artemiyb at graphcore.ai>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M mlir/lib/Pass/PassManagerOptions.cpp
A mlir/test/mlir-opt/local-reproducer-with-threading.mlir
Log Message:
-----------
[MLIR] Print more user-friendly error message when generating local reproducer and threading is enabled (#144905)
Commit: b334ffd4f4e70a404a8572b132184583a9d8623a
https://github.com/llvm/llvm-project/commit/b334ffd4f4e70a404a8572b132184583a9d8623a
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
Log Message:
-----------
[VPlan] Refine return types in VPBuilder (NFC) (#108858)
Commit: c8c4bd1ebc6e4451dc835a77bacdbe6a0467f219
https://github.com/llvm/llvm-project/commit/c8c4bd1ebc6e4451dc835a77bacdbe6a0467f219
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
A llvm/test/Transforms/LoopVectorize/predicatedinst-loop-invariant.ll
Log Message:
-----------
[LV] Stengthen loop-invariance checks in isPredicatedInst (#140744)
Check loop-invariance against SCEV as well.
Commit: 349f8d67d4ee2e7a6045b02f6aea0a72165404b1
https://github.com/llvm/llvm-project/commit/349f8d67d4ee2e7a6045b02f6aea0a72165404b1
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
A flang/test/Lower/ignore-target-data.f90
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/omptarget-llvm.mlir
M mlir/test/Target/LLVMIR/omptargetdata-nowait-llvm.mlir
M mlir/test/Target/LLVMIR/openmp-data-target-device.mlir
Log Message:
-----------
[flang][OpenMP] Skip runtime mapping with no offload targets (#144534)
When no offload targets are specified flang will ignore "target"
constructs, but not "target data" constructs. This patch makes the
behavior consistent across all offload-related operations.
While ignoring "target" may produce semantically incorrect code, it may
still be a useful debugging tool.
Commit: 152d4b8a01e8671a676e7cfaf71c70b1edeee7e8
https://github.com/llvm/llvm-project/commit/152d4b8a01e8671a676e7cfaf71c70b1edeee7e8
Author: Graham Hunter <graham.hunter at arm.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/sve-fixed-length-splat-segment.ll
Log Message:
-----------
[AArch64] Use indexed dup for 128b segmented splat (#144688)
Matches a splat of 128b segments into a wider z register expressed as a
concat_vectors sdnode and generate a dup zn.q, zd.q[0] instruction.
Commit: 8db272ffcf9ad97fe5614b34cd978eac30b53cd1
https://github.com/llvm/llvm-project/commit/8db272ffcf9ad97fe5614b34cd978eac30b53cd1
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M mlir/test/Integration/Dialect/SparseTensor/CPU/dense_output_bf16.mlir
M mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sum_bf16.mlir
Log Message:
-----------
[mlir][SparseTensor] Re-enable tests on AArch64 (#143387)
These tests were disabled in https://reviews.llvm.org/D136273, due to:
* https://github.com/llvm/llvm-project/issues/58465
That issue has now been resolved, so we should be able to re-enable
these tests.
Commit: c3929fbf0ef2d0fac05c54237bd9eac4fd57b1d8
https://github.com/llvm/llvm-project/commit/c3929fbf0ef2d0fac05c54237bd9eac4fd57b1d8
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
Log Message:
-----------
[NFC][LLVM] Reorder SVE_SME codegen predicate classes.
Also removes unused HasNonStreamingSVE2p1_or_SSVE_AES predicate.
Commit: 376b71442d03bcc8ec6e2244002e3d62916dcea4
https://github.com/llvm/llvm-project/commit/376b71442d03bcc8ec6e2244002e3d62916dcea4
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[NFC][TableGen][DecoderEmitter] Use structured binding in range for loop (#144890)
Also assign variable names to different elements of `OpMap` for better
readibility, and eliminate `NumberedEncodingsRef` as `std::vector` will
automatically get converted to an `ArrayRef`.
Commit: 269cb22ae82fd83ecc7a7ef7f7a4110e4c7a43ec
https://github.com/llvm/llvm-project/commit/269cb22ae82fd83ecc7a7ef7f7a4110e4c7a43ec
Author: Nicolas Vasilache <Nico.Vasilache at amd.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.td
M mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/PadTilingInterface.cpp
M mlir/test/Dialect/Linalg/transform-op-pad-tiling-interface.mlir
Log Message:
-----------
[mlir][transform] extract a minimal DomainAndOperandsAffineMapT… (#145034)
…ransferInterface out of LinalgStructuredInterface and use that for
PadTilingInterface
Along the way, a bug was found on the handling of scalar values, fix it
and add a test.
Commit: 3ff69c80786e4c2e37fd40a48ee675e33a5b6f76
https://github.com/llvm/llvm-project/commit/3ff69c80786e4c2e37fd40a48ee675e33a5b6f76
Author: Graham Hunter <graham.hunter at arm.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/early_exit_legality.ll
A llvm/test/Transforms/LoopVectorize/early_exit_store_legality.ll
Log Message:
-----------
[LV] Add early-exit-with-store tests (#140899)
Adds some additional LoopVectorizeLegality tests for early exit loops
with a store that we don't vectorize.
Test precommit split from #137774
Commit: 225768d1f9f2e2ccff7dc79b4a4aaeab4c6aafc1
https://github.com/llvm/llvm-project/commit/225768d1f9f2e2ccff7dc79b4a4aaeab4c6aafc1
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
M llvm/test/CodeGen/X86/vector-shift-shl-256.ll
Log Message:
-----------
[X86] combineConcatVectorOps - add tests showing v4i64 shift-by-32 with unnecessary concatenation
On AVX1-only targets, we concat SHL/SRL AVX1 v4i64 by 32-bits as a shuffle. But this is only worth while if the shift source value is free to concatenate.
Commit: bd36f7331a9f575272aebb9e0163194541110912
https://github.com/llvm/llvm-project/commit/bd36f7331a9f575272aebb9e0163194541110912
Author: Andres-Salamanca <andrealebarbaritos at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenRecordLayout.h
M clang/lib/CIR/CodeGen/CIRGenRecordLayoutBuilder.cpp
M clang/lib/CIR/CodeGen/TargetInfo.cpp
M clang/lib/CIR/CodeGen/TargetInfo.h
A clang/test/CIR/CodeGen/bitfields.c
A clang/test/CIR/CodeGen/bitfields.cpp
Log Message:
-----------
[CIR] Add initial support for bitfields in structs (#142041)
This change adds support for bitfields CIR records can now contain bit
fields.
I’ve updated the `CIRGenBitFieldInfo` comment, which originally came
from the incubator and was identical to the one in OGCodeGen, to better
reflect the current implementation.
Support for bitfields in unions big-endian architectures and `get` and
`set` operations remains unimplemented and will be addressed in a future
patch.
Commit: e0633d59b9d0f931d3917e51a51b5aa7d7e775ac
https://github.com/llvm/llvm-project/commit/e0633d59b9d0f931d3917e51a51b5aa7d7e775ac
Author: Ross Brunton <ross at codeplay.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M offload/liboffload/API/Common.td
M offload/liboffload/include/OffloadImpl.hpp
M offload/liboffload/src/OffloadImpl.cpp
M offload/tools/offload-tblgen/EntryPointGen.cpp
M offload/unittests/OffloadAPI/CMakeLists.txt
M offload/unittests/OffloadAPI/common/Environment.cpp
A offload/unittests/OffloadAPI/init/olInit.cpp
Log Message:
-----------
[Offload] Check for initialization (#144370)
All entry points (except olInit) now check that offload has been
initialized. If not, a new `OL_ERRC_UNINITIALIZED` error is returned.
Commit: f242360e156b407902829d694c036b2d22211894
https://github.com/llvm/llvm-project/commit/f242360e156b407902829d694c036b2d22211894
Author: Ross Brunton <ross at codeplay.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M offload/liboffload/src/OffloadImpl.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
Log Message:
-----------
[Offload] Add type information to device info nodes (#144535)
Rather than being "stringly typed", store values as a std::variant that
can hold various types. This means that liboffload doesn't have to do
any string parsing for integer/bool device info keys.
Commit: 96ab74bf175f46de4b6fbfc68deecd3567e42a52
https://github.com/llvm/llvm-project/commit/96ab74bf175f46de4b6fbfc68deecd3567e42a52
Author: Jameson Nash <vtjnash at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M clang/test/Misc/loop-opt-setup.c
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/test/Transforms/InstCombine/and-or-icmps.ll
M llvm/test/Transforms/InstCombine/apint-shift.ll
M llvm/test/Transforms/InstCombine/call-cast-target.ll
A llvm/test/Transforms/InstCombine/dead-alloc-elim.ll
M llvm/test/Transforms/InstCombine/fp-ret-bitcast.ll
M llvm/test/Transforms/InstCombine/getelementptr.ll
M llvm/test/Transforms/InstCombine/malloc-free.ll
M llvm/test/Transforms/InstCombine/multiple-uses-load-bitcast-select.ll
M llvm/test/Transforms/InstCombine/objsize.ll
M llvm/test/Transforms/InstCombine/select-load.ll
M llvm/test/Transforms/InstCombine/shift-amount-reassociation.ll
M llvm/test/Transforms/InstCombine/vscale_gep.ll
Log Message:
-----------
[InstCombine] remove undef loads, such as memcpy from undef (#143958)
Extend `isAllocSiteRemovable` to be able to check if the ModRef info
indicates the alloca is only Ref or only Mod, and be able to remove it
accordingly. It seemed that there were a surprising number of
benchmarks with this pattern which weren't getting optimized previously
(due to MemorySSA walk limits). There were somewhat more existing tests
than I'd like to have modified which were simply doing exactly this
pattern (and thus relying on undef memory). Claude code contributed the
new tests (and found an important typo that I'd made).
This implements the discussion in
https://github.com/llvm/llvm-project/pull/143782#discussion_r2142720376.
Commit: a2b8a93ff9cfdae4a1578c60fe5efc8ebd8c5571
https://github.com/llvm/llvm-project/commit/a2b8a93ff9cfdae4a1578c60fe5efc8ebd8c5571
Author: Luke Lau <luke at igalia.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Pass NumUnrolledElems as operand to VPWidenPointerInductionRecipe. NFC (#119859)
Similarly to VPWidenIntOrFpInductionRecipe, if we want to support it in
EVL tail folding we need to increment the induction by EVL steps instead
of VF*UF steps, but currently this is hard-wired in
VPWidenPointerInductionRecipe.
This adds an operand for the number of elements unrolled and plumbs it
through, so that we can swap it out in
VPlanTransforms::tryAddExplicitVectorLength further down the line.
Commit: 20d57e77f6709ef32791391bc064d3ed5663272a
https://github.com/llvm/llvm-project/commit/20d57e77f6709ef32791391bc064d3ed5663272a
Author: Hemang Gadhavi <hemang.gadhavi at ibm.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M lldb/source/Plugins/Process/AIX/CMakeLists.txt
A lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX.cpp
A lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX.h
Log Message:
-----------
[lldb][AIX] Added base file for AIX Register Context (#144645)
This PR is in reference to porting LLDB on AIX.
Link to discussions on llvm discourse and github:
1. https://discourse.llvm.org/t/port-lldb-to-ibm-aix/80640
2. https://github.com/llvm/llvm-project/issues/101657
The complete changes for porting are present in this draft PR:
https://github.com/llvm/llvm-project/pull/102601
- Added skeleton for Registercontext file for AIX. (Later we will add
implementation respectively)
Commit: 95c6c11c747dee61133cff56f1a7ea7445c7ae79
https://github.com/llvm/llvm-project/commit/95c6c11c747dee61133cff56f1a7ea7445c7ae79
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-fshl-256.ll
M llvm/test/CodeGen/X86/vector-fshr-256.ll
Log Message:
-----------
[X86] combineConcatVectorOps - only always concat logic ops on AVX512 targets (#145036)
We should only concat logic ops if at least one operand will freely
concatenate. We've now addressed the remaining regressions on AVX2
targets, but still have a number on AVX512 targets which can
aggressively use VPTERNLOG in many cases.
Commit: b017b4ce9a45d4c5a339e24142da5d4a7e4c5db1
https://github.com/llvm/llvm-project/commit/b017b4ce9a45d4c5a339e24142da5d4a7e4c5db1
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.h
Log Message:
-----------
[lldb][DWARF] Remove object_pointer from ParsedDWARFAttributes (#144880)
We can just always use `GetCXXObjectParameter` instead. We've only used
this attribute to set the object parameter name on ClangASTMetadata,
which doesn't seem like good enough justification to keep it around.
Depends on https://github.com/llvm/llvm-project/pull/144879
Commit: 9dc59cc95b1766510ab43ec62bb087aa9273341a
https://github.com/llvm/llvm-project/commit/9dc59cc95b1766510ab43ec62bb087aa9273341a
Author: Chao Chen <chao.chen at intel.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/test/mlir-tblgen/op-format.mlir
M mlir/tools/mlir-tblgen/OpFormatGen.cpp
Log Message:
-----------
[MLIR] Incorrect track of usedKey in setPropertiesFromParsedAttr (#144789)
co-authored by @chencha3 and @joker-eph
Commit: 05b4bfe19eaba13b4fdf39fc5541077c255b8e3f
https://github.com/llvm/llvm-project/commit/05b4bfe19eaba13b4fdf39fc5541077c255b8e3f
Author: Prajwal Nadig <pnadig at apple.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M clang/lib/ExtractAPI/Serialization/SymbolGraphSerializer.cpp
M clang/test/ExtractAPI/objc_instancetype.m
Log Message:
-----------
[ExtractAPI] Include +/- symbols for ObjC methods (#145035)
ObjC methods include a +/- prefix to indicate if they are a class or
instance method. This information is valuable, and must be included in
the navigator generated by ExtractAPI.
rdar://150870936
Commit: 71e20c6c86e04863df80e286a004a20070a5a610
https://github.com/llvm/llvm-project/commit/71e20c6c86e04863df80e286a004a20070a5a610
Author: Douglas <Douglas.Gliner at sony.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/cmake/modules/HandleLLVMOptions.cmake
Log Message:
-----------
Fix references to required libraries when building LLVM with ASAN and MultiThreaded[Debug] on Windows (#139657)
After https://github.com/llvm/llvm-project/pull/81677, statically
linking ASAN under Windows is no longer supported. Therefore, when using
Clang built past
https://github.com/llvm/llvm-project/commit/53a81d4d26f0409de8a0655d7af90f2bea222a12
to build LLVM / Clang with
`-DCMAKE_MSVC_RUNTIME_LIBRARY=MultiThreaded[Debug]
-DLLVM_USE_SANITIZER=Address`, a different set of dependent libraries
must be linked. This is mentioned in the description of
https://github.com/llvm/llvm-project/pull/81677 and also in
https://devblogs.microsoft.com/cppblog/msvc-address-sanitizer-one-dll-for-all-runtime-configurations/.
Commit: b533b0ec34ac36d8a6af406d1fb046e07f95f717
https://github.com/llvm/llvm-project/commit/b533b0ec34ac36d8a6af406d1fb046e07f95f717
Author: Jeremy Kun <jkun at google.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
A mlir/include/mlir/Analysis/DataFlow/Utils.h
M mlir/lib/Analysis/DataFlow/LivenessAnalysis.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
M mlir/test/lib/Analysis/DataFlow/TestDenseBackwardDataFlowAnalysis.cpp
M mlir/test/lib/Analysis/DataFlow/TestDenseForwardDataFlowAnalysis.cpp
M mlir/test/lib/Analysis/DataFlow/TestSparseBackwardDataFlowAnalysis.cpp
Log Message:
-----------
Define a DataFlowSolver helper that loads sensible default analyses (#143415)
Cf. https://discourse.llvm.org/t/mlir-dead-code-analysis/67568/10
Custom analysis passes will not work properly unless both
DeadCodeAnalysis and SparseConstantPropagation are loaded to the
DataFlowSolver. This is intended behavior, but surprising to many users
as shown in the thread. In lieu of a longer-term fix (which I am not
knowledgeable enough to implement myself, yet), this commit adds a
helper function that loads these two analyses, as well as providing
breadcrumbs for an explanation of the problem. The existing places in
the codebase where these two analyses are loaded for the purpose of
running other unrelated analyses are replaced by the use of the helper.
---------
Co-authored-by: Jeremy Kun <j2kun at users.noreply.github.com>
Co-authored-by: Oleksandr "Alex" Zinenko <azinenko at amd.com>
Commit: c734377544fc5a854c539fafc9b9b658f12230a3
https://github.com/llvm/llvm-project/commit/c734377544fc5a854c539fafc9b9b658f12230a3
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Log Message:
-----------
[DAG] foldMaskedMerge - fix Wparentheses operator precedence warning. NFC.
Commit: 3f1de197b1c339b311329c02bb739860b32c073f
https://github.com/llvm/llvm-project/commit/3f1de197b1c339b311329c02bb739860b32c073f
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M offload/unittests/CMakeLists.txt
M offload/unittests/OffloadAPI/device_code/CMakeLists.txt
Log Message:
-----------
[Offload] Rework compiling device code for unit test suites (#144776)
Summary:
I'll probably want to use this as a more generic utility in the future.
This patch reworks it to make it a top level function. I also tried to
decouple this from the OpenMP utilities to make that easier in the
future. Instead, I just use `-march=native` functionality which is the
same thing. Needed a small hack to skip the linker stage for checking if
that works.
This should still create the same output as far as I'm aware.
Commit: 887222e3526fbe08e748a33f740296ac22bf1ab1
https://github.com/llvm/llvm-project/commit/887222e3526fbe08e748a33f740296ac22bf1ab1
Author: Kazu Hirata <kazu at google.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M mlir/include/mlir/AsmParser/AsmParserState.h
M mlir/include/mlir/Dialect/Linalg/Utils/Utils.h
M mlir/include/mlir/Dialect/Tensor/Utils/Utils.h
M mlir/include/mlir/ExecutionEngine/ExecutionEngine.h
M mlir/include/mlir/IR/BlockSupport.h
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/BuiltinTypes.td
M mlir/include/mlir/IR/PatternMatch.h
M mlir/include/mlir/IR/Region.h
M mlir/include/mlir/IR/SymbolTable.h
M mlir/include/mlir/IR/TypeRange.h
M mlir/include/mlir/IR/ValueRange.h
M mlir/include/mlir/Rewrite/FrozenRewritePatternSet.h
M mlir/include/mlir/Tools/PDLL/AST/Types.h
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/include/mlir/Transforms/Passes.h
M mlir/lib/Dialect/GPU/Transforms/DecomposeMemRefs.cpp
M mlir/lib/Dialect/LLVMIR/IR/TypeDetail.h
M mlir/lib/Pass/PassStatistics.cpp
M mlir/unittests/IR/OperationSupportTest.cpp
M mlir/unittests/IR/ValueTest.cpp
Log Message:
-----------
[mlir] Migrate away from ArrayRef(std::nullopt) (NFC) (#144989)
ArrayRef has a constructor that accepts std::nullopt. This
constructor dates back to the days when we still had llvm::Optional.
Since the use of std::nullopt outside the context of std::optional is
kind of abuse and not intuitive to new comers, I would like to move
away from the constructor and eventually remove it.
This patch takes care of the mlir side of the migration, starting with
straightforward places where I see ArrayRef or ValueRange nearby.
Note that ValueRange has a constructor that forwards arguments to an
ArrayRef constructor.
Commit: 9524bfb27020d31b9474f595b7c0e5d2e1ac65f5
https://github.com/llvm/llvm-project/commit/9524bfb27020d31b9474f595b7c0e5d2e1ac65f5
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M lldb/cmake/modules/LLDBConfig.cmake
M lldb/include/lldb/Core/Debugger.h
M lldb/include/lldb/Core/PluginManager.h
A lldb/include/lldb/Core/ProtocolServer.h
M lldb/include/lldb/Interpreter/CommandOptionArgumentTable.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/include/lldb/lldb-forward.h
M lldb/include/lldb/lldb-private-interfaces.h
M lldb/source/Commands/CMakeLists.txt
A lldb/source/Commands/CommandObjectProtocolServer.cpp
A lldb/source/Commands/CommandObjectProtocolServer.h
M lldb/source/Core/CMakeLists.txt
M lldb/source/Core/Debugger.cpp
M lldb/source/Core/PluginManager.cpp
A lldb/source/Core/ProtocolServer.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Plugins/CMakeLists.txt
A lldb/source/Plugins/Protocol/CMakeLists.txt
A lldb/source/Plugins/Protocol/MCP/CMakeLists.txt
A lldb/source/Plugins/Protocol/MCP/MCPError.cpp
A lldb/source/Plugins/Protocol/MCP/MCPError.h
A lldb/source/Plugins/Protocol/MCP/Protocol.cpp
A lldb/source/Plugins/Protocol/MCP/Protocol.h
A lldb/source/Plugins/Protocol/MCP/ProtocolServerMCP.cpp
A lldb/source/Plugins/Protocol/MCP/ProtocolServerMCP.h
A lldb/source/Plugins/Protocol/MCP/Tool.cpp
A lldb/source/Plugins/Protocol/MCP/Tool.h
M lldb/unittests/CMakeLists.txt
M lldb/unittests/DAP/ProtocolTypesTest.cpp
A lldb/unittests/Protocol/CMakeLists.txt
A lldb/unittests/Protocol/ProtocolMCPServerTest.cpp
A lldb/unittests/Protocol/ProtocolMCPTest.cpp
M lldb/unittests/TestingSupport/TestUtilities.h
Log Message:
-----------
[lldb] Add Model Context Protocol (MCP) support to LLDB (#143628)
This PR adds an MCP (Model Context Protocol ) server to LLDB. For
motivation and background, please refer to the corresponding RFC:
https://discourse.llvm.org/t/rfc-adding-mcp-support-to-lldb/86798
I implemented this as a new kind of plugin. The idea is that we could
support multiple protocol servers (e.g. if we want to support DAP from
within LLDB). This also introduces a corresponding top-level command
(`protocol-server`) with two subcommands to `start` and `stop` the
server.
```
(lldb) protocol-server start MCP tcp://localhost:1234
MCP server started with connection listeners: connection://[::1]:1234, connection://[127.0.0.1]:1234
```
The MCP sever supports one tool (`lldb_command`) which executes a
command, but can easily be extended with more commands.
Commit: 78971916da04895838ff043f4fc71760dcca5bac
https://github.com/llvm/llvm-project/commit/78971916da04895838ff043f4fc71760dcca5bac
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Commands/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Core/BUILD.gn
Log Message:
-----------
[gn build] Port 9524bfb27020
Commit: 6e86b7e34b9494a01bf7164825c3d72ff21a4c7f
https://github.com/llvm/llvm-project/commit/6e86b7e34b9494a01bf7164825c3d72ff21a4c7f
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
Log Message:
-----------
[AMDGPU] Do not replace SALU floating point multiply with VALU-only ldexp (#145048)
Commit: 749e4a53d252e23e870d4a1638ff9d846af58e7f
https://github.com/llvm/llvm-project/commit/749e4a53d252e23e870d4a1638ff9d846af58e7f
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M lldb/source/Commands/CommandObjectProtocolServer.cpp
M lldb/source/Commands/CommandObjectProtocolServer.h
Log Message:
-----------
[lldb] Fix ASCII art in CommandObjectProtocolServer (NFC)
Commit: 151ee0faad427651304b51b8af77704be26bb485
https://github.com/llvm/llvm-project/commit/151ee0faad427651304b51b8af77704be26bb485
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll
Log Message:
-----------
[X86] SimplifyDemandedVectorEltsForTargetNode - ensure X86ISD::VPERMILPV node use v2f64/v4f32 types
When reducing v4f64/v8f32 non-lane crossing X86ISD::VPERMV nodes, we use X86ISD::VPERMILPV nodes for 128-bits, but these are only available for fp types.
Fixes #145046
Commit: 32fc625a3fa27fa325c75b0fc841db4ce8e06805
https://github.com/llvm/llvm-project/commit/32fc625a3fa27fa325c75b0fc841db4ce8e06805
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M clang/lib/AST/ByteCode/ByteCodeEmitter.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Descriptor.cpp
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/Floating.h
M clang/lib/AST/ByteCode/Integral.h
M clang/lib/AST/ByteCode/IntegralAP.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
M clang/lib/AST/ByteCode/InterpState.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ByteCode/PrimType.h
M clang/lib/AST/ByteCode/Program.h
M clang/test/AST/ByteCode/builtin-bit-cast-long-double.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
Log Message:
-----------
Reapply "Reapply "[clang][bytecode] Allocate IntegralAP and Floating … (#145014)
…types usi… (#144676)"
This reverts commit 68471d29eed2c49f9b439e505b3f24d387d54f97.
IntegralAP contains a union:
union {
uint64_t *Memory = nullptr;
uint64_t Val;
};
On 64bit systems, both Memory and Val have the same size. However, on 32
bit system, Val is 64bit and Memory only 32bit. Which means the default
initializer for Memory will only zero half of Val. We fixed this by
zero-initializing Val explicitly in the IntegralAP(unsigned BitWidth)
constructor.
See also the discussion in
https://github.com/llvm/llvm-project/pull/144246
Commit: 770b16cd4939054e30f5bba40765cfe1f5895f74
https://github.com/llvm/llvm-project/commit/770b16cd4939054e30f5bba40765cfe1f5895f74
Author: Amir Ayupov <aaupov at fb.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M bolt/test/perf2bolt/X86/perf2bolt-spe.test
Log Message:
-----------
[BOLT][test] Update X86/perf2bolt-spe.test (#145061)
Address NFC mismatches caused by running perf2bolt from under the
wrapper script:
https://lab.llvm.org/buildbot/#/builders/92/builds/20938
> <stdin>:2:64: note: possible intended match here
>
/home/worker/bolt-worker2/bolt-x86_64-ubuntu-nfc/build/bin/llvm-bolt.old:
-spe is available only on AArch64.
Test Plan:
ninja check-bolt
Commit: 72de0e45846bab293a0b07e5aeda65a5e6590a87
https://github.com/llvm/llvm-project/commit/72de0e45846bab293a0b07e5aeda65a5e6590a87
Author: Chenguang Wang <w3cing at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/docs/TableGen/ProgRef.rst
Log Message:
-----------
[TableGen][Docs] Fix empty list syntax in TableGen doc. (#145041)
`[]<list<int>>` actually produces `list<list<int>>`.
Commit: 6ba1955ba22c0bea4d2fb76c6dfcad0f5354be72
https://github.com/llvm/llvm-project/commit/6ba1955ba22c0bea4d2fb76c6dfcad0f5354be72
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
A flang/test/Lower/OpenMP/ignore-target-data.f90
R flang/test/Lower/ignore-target-data.f90
Log Message:
-----------
[flang][OpenMP] Fix ignore-target-data.f90 test
Allow the function definition line to match with and without attrbute
set number.
This fixes build break after PR144534:
https://lab.llvm.org/buildbot/#/builders/157/builds/31331
Also move the test to the OpenMP subdirectory where it should have
been from the beginning.
Commit: bfef8732be1b7b3a7ba7b3ccd93d043fd044293e
https://github.com/llvm/llvm-project/commit/bfef8732be1b7b3a7ba7b3ccd93d043fd044293e
Author: Justin King <jcking at google.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M compiler-rt/lib/msan/msan_interceptors.cpp
M compiler-rt/test/sanitizer_common/TestCases/Linux/free_aligned_sized.c
M compiler-rt/test/sanitizer_common/TestCases/Linux/free_sized.c
Log Message:
-----------
msan: Support free_sized and free_aligned_sized from C23 (#144529)
Adds support to MSan for `free_sized` and `free_aligned_sized` from C23.
Other sanitizers will be handled with their own separate PRs.
For https://github.com/llvm/llvm-project/issues/144435
Signed-off-by: Justin King <jcking at google.com>
Commit: 877511920dcf36463e06746d626e8876583a6abd
https://github.com/llvm/llvm-project/commit/877511920dcf36463e06746d626e8876583a6abd
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.h
Log Message:
-----------
Revert "[lldb][DWARF] Remove object_pointer from ParsedDWARFAttributes" (#145065)
Reverts llvm/llvm-project#144880
Caused `TestObjCIvarsInBlocks.py` to fail on macOS CI.
Commit: 940ff110d78ba1eea7e0004275e098024cfd87c4
https://github.com/llvm/llvm-project/commit/940ff110d78ba1eea7e0004275e098024cfd87c4
Author: Jameson Nash <vtjnash at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
Log Message:
-----------
[InstCombine] fix hwasan mistake in "remove dead loads" (#145057)
Detected by CI after #143958.
Commit: 379a609dadc1733c2b62d2bf3bab6e8032236836
https://github.com/llvm/llvm-project/commit/379a609dadc1733c2b62d2bf3bab6e8032236836
Author: Muzammil <55665739+Muzammiluddin-Syed-ECE at users.noreply.github.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/Arith/Transforms/Passes.h
M mlir/include/mlir/Dialect/Arith/Transforms/Passes.td
M mlir/lib/Dialect/Arith/Transforms/ExpandOps.cpp
M mlir/test/Dialect/Arith/expand-ops.mlir
A mlir/test/Integration/Dialect/Arith/CPU/test-arith-expand-truncf-extf.mlir
Log Message:
-----------
[mlir][arith][transforms] Adds f4E2M1FN support to truncf and extf (#144157)
See work detail: https://github.com/iree-org/iree/issues/20920
Add support for f4E2M1FN in `arith.truncf` and `arith.extf` ops though a software emulation
---------
Signed-off-by: Muzammiluddin Syed <muzasyed at amd.com>
Commit: edbaf19c46c678e080d5a43e719bc19a02b44ca9
https://github.com/llvm/llvm-project/commit/edbaf19c46c678e080d5a43e719bc19a02b44ca9
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
A llvm/test/CodeGen/AMDGPU/gcn-reg-pressure-true16-integer-overflow.mir
Log Message:
-----------
[AMDGPU] Fix a potential integer overflow in GCNRegPressure when true16 is enabled (#144968)
Fixes SWDEV-537014.
Commit: 945ce1aa3d29e24c49720ae9e0bcfbac88f2defd
https://github.com/llvm/llvm-project/commit/945ce1aa3d29e24c49720ae9e0bcfbac88f2defd
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M libcxx/include/version
M libcxx/test/std/language.support/support.limits/support.limits.general/expected.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/optional.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/tuple.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/utility.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/variant.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
M libcxx/utils/generate_feature_test_macro_components.py
Log Message:
-----------
[libc++] Update the value of __cpp_lib_constrained_equality after P3379R0 (#144553)
https://wg21.link/P3379R0 updated the value of __cpp_lib_constrained_equality,
but we forgot to update it when we implemented the paper.
Commit: 6ddb3a69c15963b7cf1cbb0323dd3e467b71cefc
https://github.com/llvm/llvm-project/commit/6ddb3a69c15963b7cf1cbb0323dd3e467b71cefc
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
Log Message:
-----------
[AMDGPU] Add another test showing unwanted VALU codegen (#145062)
Commit: 7157f33c6c88143acb8bc02bc26a0d6786136419
https://github.com/llvm/llvm-project/commit/7157f33c6c88143acb8bc02bc26a0d6786136419
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M libcxx/test/libcxx/depr/exception.unexpected/unexpected_disabled_cpp17.verify.cpp
Log Message:
-----------
[libc++] Disable a std::unexpected test in modules build (#144466)
This patch disables unexpected_disabled_cpp17.verify.cpp under clang
modules builds because it changes diagnostics criteria post #143423,
causing the test to fail.
This patch follows a similar style to 853059a15011fd8b57dd0.
This was found when working on trying to land #144033.
Commit: 8d6e29d0d3e3acb67adaa61648f35a38a9d196b3
https://github.com/llvm/llvm-project/commit/8d6e29d0d3e3acb67adaa61648f35a38a9d196b3
Author: Uzair Nawaz <uzairnawaz at google.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M libc/src/__support/wchar/character_converter.cpp
M libc/src/__support/wchar/character_converter.h
M libc/src/__support/wchar/mbstate.h
M libc/test/src/__support/wchar/utf32_to_8_test.cpp
M libc/test/src/__support/wchar/utf8_to_32_test.cpp
Log Message:
-----------
[libc] Reworked CharacterConverter isComplete into isFull and isEmpty (#144799)
isComplete previously meant different things for different conversion
directions.
Refactored bytes_processed to bytes_stored which now consistently
increments on every push and decrements on pop making both directions
more consistent with each other
Commit: 65cb3bcf327da8f9740e56897bc9954364e59eb6
https://github.com/llvm/llvm-project/commit/65cb3bcf327da8f9740e56897bc9954364e59eb6
Author: Maryam Moghadas <maryammo at ca.ibm.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsPPC.def
M clang/include/clang/Basic/PPCTypes.def
M clang/lib/AST/ASTContext.cpp
M clang/test/AST/ast-dump-ppc-types.c
A clang/test/CodeGen/PowerPC/builtins-ppc-dmf.c
A clang/test/CodeGen/PowerPC/ppc-dmf-paired-vec-memops-builtin-err.c
A clang/test/CodeGen/PowerPC/ppc-dmf-types.c
A clang/test/CodeGen/PowerPC/ppc-future-mma-builtin-err.c
M clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
A clang/test/Sema/ppc-dmf-types.c
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
Log Message:
-----------
[Clang][PowerPC] Add __dmr1024 type and DMF integer calculation builtins (#142480)
Define the __dmr1024 type used to manipulate the new DMR registers
introduced by the Dense Math Facility (DMF) on PowerPC, and add six
Clang builtins that correspond to the integer outer-product accumulate
to ACC PowerPC instructions:
* __builtin_mma_dmxvi8gerx4
* __builtin_mma_pmdmxvi8gerx4
* __builtin_mma_dmxvi8gerx4pp
* __builtin_mma_pmdmxvi8gerx4pp
* __builtin_mma_dmxvi8gerx4spp
* __builtin_mma_pmdmxvi8gerx4spp.
Commit: f8ee5774b612c425051adfc9108d1c52820b193d
https://github.com/llvm/llvm-project/commit/f8ee5774b612c425051adfc9108d1c52820b193d
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
M llvm/test/CodeGen/X86/vector-shift-shl-256.ll
Log Message:
-----------
[X86] combineConcatVectorOps - only concat AVX1 v4i64 shift-by-32 to a shuffle if the concat is free (#145043)
Commit: 33a92af1b2260506356eb838125b356703bf02bb
https://github.com/llvm/llvm-project/commit/33a92af1b2260506356eb838125b356703bf02bb
Author: Thurston Dang <thurston at google.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/partial-poison.ll
Log Message:
-----------
[msan] Add off-by-default flag to fix false negatives from partially undefined constant fixed-length vectors (#143837)
This patch adds an off-by-default flag which, when enabled via `-mllvm -msan-poison-undef-vectors=true`, fixes a false negative in MSan (partially-undefined constant fixed-length vectors). It is currently off by default since, by fixing the false positive, code/tests that previously passed MSan may start failing. The default will be changed in a future patch.
Prior to this patch, MSan computes that partially-undefined constant fixed-length vectors are fully initialized, which leads to false negatives; moreover, benign vector rewriting could theoretically flip MSan's shadow computation from initialized to uninitialized or vice-versa (*). `-msan-poison-undef-vectors=true` calculates the shadow precisely: for each element of the vector, the corresponding shadow is fully uninitialized if the element is undefined/poisoned, otherwise it is fully initialized.
Updates the test from https://github.com/llvm/llvm-project/pull/143823
(*) For example:
```
%x = insertelement <2 x i64> <i64 0, i64 poison>, i64 42, i64 0
%y = insertelement <2 x i64> <i64 poison, i64 poison>, i64 42, i64 0
```
%x and %y are equivalent but, prior to this patch, MSan incorrectly computes the shadow of %x as <0, 0> rather than <0, -1>.
Commit: 0d21c956a5c1640c0f9588b307963bf32b09f6ab
https://github.com/llvm/llvm-project/commit/0d21c956a5c1640c0f9588b307963bf32b09f6ab
Author: Michal Rostecki <vadorovsky at disroot.org>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/BPF/BTFDebug.cpp
A llvm/test/CodeGen/BPF/BTF/map-def-nested.ll
Log Message:
-----------
[BPF] Handle nested wrapper structs in BPF map definition traversal (#144097)
In Aya/Rust, BPF map definitions are nested in two nested types:
* A struct representing the map type (e.g., `HashMap`, `RingBuf`) that
provides methods for interacting with the map type (e.g. `HashMap::get`,
`RingBuf::reserve`).
* An `UnsafeCell`, which informs the Rust compiler that the type is
thread-safe and can be safely mutated even as a global variable. The
kernel guarantees map operation safety.
This leads to a type hierarchy like:
```rust
pub struct HashMap<K, V, const M: usize, const F: usize = 0>(
core::cell::UnsafeCell<HashMapDef<K, V, M, F>>,
);
const BPF_MAP_TYPE_HASH: usize = 1;
pub struct HashMapDef<K, V, const M: usize, const F: usize = 0> {
r#type: *const [i32; BPF_MAP_TYPE_HASH],
key: *const K,
value: *const V,
max_entries: *const [i32; M],
map_flags: *const [i32; F],
}
```
Then used in the BPF program code as a global variable:
```rust
#[link_section = ".maps"]
static HASH_MAP: HashMap<u32, u32, 1337> = HashMap::new();
```
Which is an equivalent of the following BPF map definition in C:
```c
#define BPF_MAP_TYPE_HASH 1
struct {
int (*type)[BPF_MAP_TYPE_HASH];
typeof(int) *key;
typeof(int) *value;
int (*max_entries)[1337];
} map_1 __attribute__((section(".maps")));
```
Accessing the actual map definition requires traversing:
```
HASH_MAP -> __0 -> value
```
Previously, the BPF backend only visited the pointee types of the
outermost struct, and didn’t descend into inner wrappers. This caused
issues when the key/value types were custom structs:
```rust
// Define custom structs for key and values.
pub struct MyKey(u32);
pub struct MyValue(u32);
#[link_section = ".maps"]
#[export_name = "HASH_MAP"]
pub static HASH_MAP: HashMap<MyKey, MyValue, 10> = HashMap::new();
```
These types weren’t fully visited and appeared in BTF as forward
declarations:
```
#30: <FWD> 'MyKey' kind:struct
#31: <FWD> 'MyValue' kind:struct
```
The fix is to enhance `visitMapDefType` to recursively visit inner
composite members. If a member is a composite type (likely a wrapper),
it is now also visited using `visitMapDefType`, ensuring that the
pointee types of the innermost stuct members, like `MyKey` and
`MyValue`, are fully resolved in BTF.
With this fix, the correct BTF entries are emitted:
```
#6: <STRUCT> 'MyKey' sz:4 n:1
#00 '__0' off:0 --> [7]
#7: <INT> 'u32' bits:32 off:0
#8: <PTR> --> [9]
#9: <STRUCT> 'MyValue' sz:4 n:1
#00 '__0' off:0 --> [7]
```
Fixes: #143361
Commit: adc6228ea07eba401481e218c3e0536a4aa6b8ec
https://github.com/llvm/llvm-project/commit/adc6228ea07eba401481e218c3e0536a4aa6b8ec
Author: Charitha Saumya <136391709+charithaintc at users.noreply.github.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/Transforms/Passes.td
M mlir/include/mlir/Dialect/XeGPU/Utils/XeGPUUtils.h
M mlir/lib/Dialect/XeGPU/Transforms/CMakeLists.txt
A mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
A mlir/test/Dialect/XeGPU/propagate-layout.mlir
A mlir/test/Dialect/XeGPU/subgroup-distribute.mlir
R mlir/test/Dialect/XeGPU/subgroup-distribution.mlir
R mlir/test/Dialect/XeGPU/subgroup-map-propagation.mlir
Log Message:
-----------
[mlir][xegpu] Refine layout assignment in XeGPU SIMT distribution. (#142687)
Changes:
* Decouple layout propagation from subgroup distribution and move it to
an independent pass.
* Refine layout assignment to handle control-flow ops correctly (scf.for, scf.while).
* Refine test cases.
Commit: 04e2e581ac000934782398e05853338040bf7c46
https://github.com/llvm/llvm-project/commit/04e2e581ac000934782398e05853338040bf7c46
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmaccbf16.ll
Log Message:
-----------
[RISCV] Treat bf16->f32 as separate ExtKind in combineOp_VLToVWOp_VL. (#144653)
This allows us to better track the narrow type we need and to fix
miscompiles if f16->f32 and bf16->f32 extends are mixed.
Fixes #144651.
Commit: ab8b8c1e138ae705f251626b63ad2cf4d7937003
https://github.com/llvm/llvm-project/commit/ab8b8c1e138ae705f251626b63ad2cf4d7937003
Author: Sam Elliott <quic_aelliott at quicinc.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/cmake/modules/TableGen.cmake
M llvm/include/llvm/TargetParser/CMakeLists.txt
Log Message:
-----------
[TargetParser][cmake] Be Smarter about TableGen Deps (#144848)
This tries to be a bit smarter for the OLD behaviour of CMP0116, to glob
more relevant directories looking for possible dependencies.
The changes are:
- Remove some duplication of lines in the `tablegen` function.
- Put CURRENT_SOURCE_DIR into `tblgen_includes` (at the front)
- Glob all directories in `tblgen_includes`
- Give up on `local_tds` which was wrong when using tablegen to compile
a file in a different directory (as TargetParser does)
- Use `EXTRA_INCLUDES` in TargetParser `tablegen` calls.
This is still an under-approximation of what might be included, at least
comparing the RISCVTargetParserDef.inc.d (after building
`target_parser_gen`), and the list of deps in the ninja file when
explicitly setting CMP0116 to OLD.
Fixes #144639
Commit: 7f74a377d094c34eba1adde1f1edc382d01d2e5e
https://github.com/llvm/llvm-project/commit/7f74a377d094c34eba1adde1f1edc382d01d2e5e
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_and.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_div_urem.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_lshr.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction2.ll
Log Message:
-----------
[LV] Regenerate uniform_across_vf* check lines.
Re-generate check lines to reduce diff in upcoming changes.
Also filters out the code after scalar.ph:, which is dead.
Commit: bae48ac3c0e6f406038833199b185493a67ee08b
https://github.com/llvm/llvm-project/commit/bae48ac3c0e6f406038833199b185493a67ee08b
Author: Yijia Gu <yijiagu at google.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] add missing deps for XeGPUTransforms
Commit: ff6367b47071a7d80e773127e2a798c087e81ff5
https://github.com/llvm/llvm-project/commit/ff6367b47071a7d80e773127e2a798c087e81ff5
Author: Diego Caballero <dieg0ca6aller0 at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Vector/canonicalize.mlir
Log Message:
-----------
[[mlir][Vector] Add simple folders for `vector.from_element`/`vector.to_elements` (#144444)
This PR adds simple folders to remove no-op sequences of
`vector.from_elements` and `vector.to_elements`.
Commit: 521adc9fa270c1524f125f155327bf8f3743bb87
https://github.com/llvm/llvm-project/commit/521adc9fa270c1524f125f155327bf8f3743bb87
Author: Luke Lau <luke at igalia.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll
Log Message:
-----------
[VPlan] Use createScalarZExtOrTrunc when expanding expandVPWidenIntOrFpInduction
Split off from #144666
Commit: 3f42c6bddd2495710331c82ce117ee7d5a58856d
https://github.com/llvm/llvm-project/commit/3f42c6bddd2495710331c82ce117ee7d5a58856d
Author: Deric C. <cheung.deric at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/DirectX/DXILDataScalarization.cpp
A llvm/test/CodeGen/DirectX/scalarize-dynamic-vector-index.ll
Log Message:
-----------
[DirectX] Scalarize `extractelement` and `insertelement` with dynamic indices (#141676)
Fixes #141136
- Implement `visitExtractElementInst` and `visitInsertElementInst` in
`DXILDataScalarizerVisitor` to scalarize `extractelement` and
`insertelement` instructions whose index operand is not a `ConstantInt`
by converting the vector to an array and then loading from the array
- Rename the `replaceVectorWithArray` helper function to
`equivalentArrayTypeFromVector`, relocate the function toward the top of
the file, and remove the unused `Ctx` parameter
Commit: 925dbc798828d78e5300972dfdabb89955216229
https://github.com/llvm/llvm-project/commit/925dbc798828d78e5300972dfdabb89955216229
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M flang/lib/Lower/OpenMP/Atomic.h
Log Message:
-----------
[flang][OpenMP] Fix namespace nesting after PR144960
Newly introduced Atomic.cpp fails to compile on its own, but somehow
compiles fine in the build. Maybe it's because PCH, but it needs to be
fixed nevertheless.
Commit: f159774352c37a75829c04febb89f141175fc2bf
https://github.com/llvm/llvm-project/commit/f159774352c37a75829c04febb89f141175fc2bf
Author: Fabian Mora <fmora.dev at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/Ptr/IR/PtrDialect.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrOps.td
M mlir/include/mlir/IR/BuiltinTypeInterfaces.td
M mlir/include/mlir/IR/BuiltinTypes.h
M mlir/include/mlir/IR/BuiltinTypes.td
M mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp
M mlir/lib/Dialect/Ptr/IR/PtrTypes.cpp
M mlir/lib/IR/BuiltinTypes.cpp
M mlir/test/Dialect/Ptr/canonicalize.mlir
A mlir/test/Dialect/Ptr/invalid.mlir
M mlir/test/Dialect/Ptr/ops.mlir
Log Message:
-----------
[mlir][core|ptr] Add `PtrLikeTypeInterface` and casting ops to the `ptr` dialect (#137469)
This patch adds the `PtrLikeTypeInterface` type interface to identify
pointer-like types. This interface is defined as:
```
A ptr-like type represents an object storing a memory address. This object
is constituted by:
- A memory address called the base pointer. This pointer is treated as a
bag of bits without any assumed structure. The bit-width of the base
pointer must be a compile-time constant. However, the bit-width may remain
opaque or unavailable during transformations that do not depend on the
base pointer. Finally, it is considered indivisible in the sense that as
a `PtrLikeTypeInterface` value, it has no metadata.
- Optional metadata about the pointer. For example, the size of the memory
region associated with the pointer.
Furthermore, all ptr-like types have two properties:
- The memory space associated with the address held by the pointer.
- An optional element type. If the element type is not specified, the
pointer is considered opaque.
```
This patch adds this interface to `!ptr.ptr` and the `memref` type.
Furthermore, this patch adds necessary ops and type to handle casting
between `!ptr.ptr` and ptr-like types.
First, it defines the `!ptr.ptr_metadata` type. An opaque type to
represent the metadata of a ptr-like type. The rationale behind adding
this type, is that at high-level the metadata of a type like `memref`
cannot be specified, as its structure is tied to its lowering.
The `ptr.get_metadata` operation was added to extract the opaque pointer
metadata. The concrete structure of the metadata is only known when the
op is lowered.
Finally, this patch adds the `ptr.from_ptr` and `ptr.to_ptr` operations.
Allowing to cast back and forth between `!ptr.ptr` and ptr-like types.
```mlir
func.func @func(%mr: memref<f32, #ptr.generic_space>) -> memref<f32, #ptr.generic_space> {
%ptr = ptr.to_ptr %mr : memref<f32, #ptr.generic_space> -> !ptr.ptr<#ptr.generic_space>
%mda = ptr.get_metadata %mr : memref<f32, #ptr.generic_space>
%res = ptr.from_ptr %ptr metadata %mda : !ptr.ptr<#ptr.generic_space> -> memref<f32, #ptr.generic_space>
return %res : memref<f32, #ptr.generic_space>
}
```
It's future work to replace and remove the `bare-ptr-convention` through
the use of these ops.
---------
Co-authored-by: Mehdi Amini <joker.eph at gmail.com>
Commit: c103bbc836691d637c249ca19d38bdb0034437c6
https://github.com/llvm/llvm-project/commit/c103bbc836691d637c249ca19d38bdb0034437c6
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/tail-folding-styles.ll
M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cond-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-interleave.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-intermediate-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-iv32.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-known-no-overflow.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-masked-loadstore.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-ordered-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-uniform-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll
A llvm/test/Transforms/LoopVectorize/scalable-predication.ll
Log Message:
-----------
[LV] Consider whether vscale is a known power of two for iteration check (#144963)
Going mostly by the comment here - but it says "vscale is not
necessarily a power-of-2". Both in tree targets have vscale as a power
of two, and we have an existing TTI hook for that.
Commit: 8d2eea96b391c5346543eceae5c8d24efe4f4497
https://github.com/llvm/llvm-project/commit/8d2eea96b391c5346543eceae5c8d24efe4f4497
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/test/MC/AMDGPU/gfx12_asm_sopp.s
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopp.txt
Log Message:
-----------
[AMDGPU] gfx1250 SOPP MC tests. NFC. (#145082)
Commit: b5d5708128e99f69add50c322bfbed5f4905c23d
https://github.com/llvm/llvm-project/commit/b5d5708128e99f69add50c322bfbed5f4905c23d
Author: joaosaffran <126493771+joaosaffran at users.noreply.github.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/include/llvm/BinaryFormat/DXContainer.h
M llvm/include/llvm/BinaryFormat/DXContainerConstants.def
M llvm/lib/Target/DirectX/DXILRootSignature.cpp
M llvm/lib/Target/DirectX/DXILRootSignature.h
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-AllValidFlagCombinations.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-AllValidFlagCombinationsV1.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-Invalid-Flag.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-Invalid-RangeType.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-Invalid-RegisterSpace.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Parameters.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor-Invalid-Flags.ll
Log Message:
-----------
[HLSL] Add descriptor table metadata parsing (#142492)
Implements descriptor table parsing from root signature metadata. This
is required to support root signatures in hlsl.
Closes: #[126640](https://github.com/llvm/llvm-project/issues/126640)
---------
Co-authored-by: joaosaffran <joao.saffran at microsoft.com>
Commit: 958dc8602651261f8285b59d352a1c4b4da2e90c
https://github.com/llvm/llvm-project/commit/958dc8602651261f8285b59d352a1c4b4da2e90c
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
Log Message:
-----------
[AMDGPU] Don't insert wait instructions that are not supported by gfx1250 (#145084)
No tests yet, but it will allow further tests not to be
polluted with these waits.
Commit: 2a4207e7322c90176814b17870051f9692f9994f
https://github.com/llvm/llvm-project/commit/2a4207e7322c90176814b17870051f9692f9994f
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/DirectX/DXILDataScalarization.cpp
M llvm/test/CodeGen/DirectX/scalarize-alloca.ll
Log Message:
-----------
[DirectX] Don't limit visitGetElementPtrInst to global ptrs (#144959)
fixes #144608
- there is a getPointerOperandIndex function so we don't need to iterate
the operands trying to find the pointer. This resulted in a small
cleanup to visitStoreInst and visitLoadInst.
- The meat of this change was in visitGetElementPtrInst to account for
allocas and not bail when we don't find a global.
Commit: affcc5e728c86260590ae398c136d43ac6cfbfb0
https://github.com/llvm/llvm-project/commit/affcc5e728c86260590ae398c136d43ac6cfbfb0
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SOPInstructions.td
A llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s
A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sopp.txt
Log Message:
-----------
[AMDGPU] Add s_wait_xcnt gfx1250 instruction (#145086)
Commit: 227f759644bbc208045178c54633df241f27da7f
https://github.com/llvm/llvm-project/commit/227f759644bbc208045178c54633df241f27da7f
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M mlir/lib/Bindings/Python/IRCore.cpp
Log Message:
-----------
[mlir][python] expose operation.block (#145088)
Expose `operation-getBlock()` in python.
Commit: 6d8c6ef90c1a4d17d764c4479d5165251bf07c95
https://github.com/llvm/llvm-project/commit/6d8c6ef90c1a4d17d764c4479d5165251bf07c95
Author: Amir Ayupov <aaupov at fb.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M bolt/lib/Profile/BoltAddressTranslation.cpp
M bolt/lib/Profile/DataAggregator.cpp
Log Message:
-----------
[BOLT][NFC] Simplify doTrace in BAT mode (#143233)
`BoltAddressTranslation::getFallthroughsInTrace` iterates over address
translation map entries and therefore has direct access to both original
and translated offsets. Return the translated offsets in fall-throughs
list to avoid duplicate address translation inside `doTrace`.
Test Plan: NFC
Commit: 4959e8a1dadd96499d701bcf02cd9b25dba98c98
https://github.com/llvm/llvm-project/commit/4959e8a1dadd96499d701bcf02cd9b25dba98c98
Author: Amir Ayupov <aaupov at fb.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/test/X86/register-fragments-bolt-symbols.s
Log Message:
-----------
[BOLT][NFCI] Use heuristic for matching split global functions (#90429)
This change speeds up fragment matching for large BOLTed binaries where
all fragments of global parent functions are put under `bolt-pseudo.o`
file symbol:
- before: iterating over symbols under `bolt-pseudo.o` only to fail
to find a parent,
- after: bail out immediately and use a global parent by name.
Test Plan: NFC, updated register-fragments-bolt-symbols.s
Commit: d8924d4da78fc980b720b328897b1bd5efba348a
https://github.com/llvm/llvm-project/commit/d8924d4da78fc980b720b328897b1bd5efba348a
Author: nerix <nerixdev at outlook.de>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M lldb/source/API/CMakeLists.txt
Log Message:
-----------
[LLDB] Explicitly use python for version fixup (#144217)
On Windows, the post build command would open the script in the default
editor, since it doesn't know about shebangs. This effectively adds
`python3` in front of the command.
Amends https://github.com/llvm/llvm-project/pull/142871 /
https://github.com/llvm/llvm-project/pull/141116
Commit: 3a66e2065296b3e0b27f0a14431eba1d74e7f8c4
https://github.com/llvm/llvm-project/commit/3a66e2065296b3e0b27f0a14431eba1d74e7f8c4
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt
Log Message:
-----------
[AMDGPU] Add gfx1250 runlines to vop3 dpp tests. NFC. (#145089)
dpp8 disasm test does not work yet.
Commit: d078ce7c98a3f9371d01d526e20f671ca2231667
https://github.com/llvm/llvm-project/commit/d078ce7c98a3f9371d01d526e20f671ca2231667
Author: sribee8 <sriya.pratipati at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/mbstate_t.h
M libc/include/llvm-libc-types/mbstate_t.h
M libc/include/wchar.yaml
M libc/src/__support/wchar/CMakeLists.txt
A libc/src/__support/wchar/mbrtowc.cpp
A libc/src/__support/wchar/mbrtowc.h
M libc/src/__support/wchar/mbstate.h
M libc/src/wchar/CMakeLists.txt
A libc/src/wchar/mbrtowc.cpp
A libc/src/wchar/mbrtowc.h
M libc/test/src/wchar/CMakeLists.txt
A libc/test/src/wchar/mbrtowc_test.cpp
Log Message:
-----------
[libc] mbrtowc implementation (#144760)
implemented the internal and public mbrtowc as well as tests for the
public function.
---------
Co-authored-by: Sriya Pratipati <sriyap at google.com>
Commit: f8ffb4e7cd94b661c3edd323f3dd85dc77892c16
https://github.com/llvm/llvm-project/commit/f8ffb4e7cd94b661c3edd323f3dd85dc77892c16
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-dead-instructions.ll
Log Message:
-----------
[VPlan] Simplify ExtractLastElement(Broadcast(A)) -> A.
Remove trivial ExtractLastElement VPInstructions.
Commit: 3b9795b3d3b249a5a3052a44f2c1ad7268ed34c6
https://github.com/llvm/llvm-project/commit/3b9795b3d3b249a5a3052a44f2c1ad7268ed34c6
Author: Rodolfo Wottrich <rgwott at users.noreply.github.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
A llvm/test/CodeGen/AArch64/cpa-globalisel.ll
A llvm/test/CodeGen/AArch64/cpa-selectiondag.ll
Log Message:
-----------
[AArch64] Add CodeGen support for scalar FEAT_CPA (#105669)
CPA stands for Checked Pointer Arithmetic and is part of the 2023 MTE
architecture extensions for A-profile.
The new CPA instructions perform regular pointer arithmetic (such as
base register + offset) but check for overflow in the most significant
bits of the result, enhancing security by detecting address tampering.
In this patch we intend to capture the semantics of pointer arithmetic
when it is not folded into loads/stores, then generate the appropriate
scalar CPA instructions. In order to preserve pointer arithmetic
semantics through the backend, we use the PTRADD SelectionDAG node type.
Use backend option `-aarch64-use-featcpa-codegen=true` to enable CPA
CodeGen (for a target with CPA enabled).
The story of this PR is that initially it introduced the PTRADD
SelectionDAG node and the respective visitPTRADD() function, adapted
from the CHERI/Morello LLVM tree. The original authors are
@davidchisnall, @jrtc27, @arichardson.
After a while, @ritter-x2a took the part of the code that was
target-independent and merged it separately in #140017. This PR thus
remains as the AArch64-part only.
Mode details about the CPA extension can be found at:
-
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023
- https://developer.arm.com/documentation/ddi0602/2023-09/ (e.g ADDPT
instruction)
This PR follows #79569.
It does not address vector FEAT_CPA instructions.
Commit: 491b82a5ec1add78d2c93370580a2f1897b6a364
https://github.com/llvm/llvm-project/commit/491b82a5ec1add78d2c93370580a2f1897b6a364
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M lld/ELF/Arch/AArch64.cpp
A lld/ELF/Arch/TargetImpl.h
M lld/ELF/Arch/X86_64.cpp
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/Options.td
M lld/ELF/Relocations.cpp
M lld/ELF/Target.h
M lld/docs/ReleaseNotes.rst
M lld/docs/ld.lld.1
A lld/test/ELF/aarch64-branch-to-branch.s
A lld/test/ELF/x86-64-branch-to-branch.s
Log Message:
-----------
ELF: Add branch-to-branch optimization.
When code calls a function which then immediately tail calls another
function there is no need to go via the intermediate function. By
branching directly to the target function we reduce the program's working
set for a slight increase in runtime performance.
Normally it is relatively uncommon to have functions that just tail call
another function, but with LLVM control flow integrity we have jump tables
that replace the function itself as the canonical address. As a result,
when a function address is taken and called directly, for example after
a compiler optimization resolves the indirect call, or if code built
without control flow integrity calls the function, the call will go via
the jump table.
The impact of this optimization was measured using a large internal
Google benchmark. The results were as follows:
CFI enabled: +0.1% ± 0.05% queries per second
CFI disabled: +0.01% queries per second [not statistically significant]
The optimization is enabled by default at -O2 but may also be enabled
or disabled individually with --{,no-}branch-to-branch.
This optimization is implemented for AArch64 and X86_64 only.
lld's runtime performance (real execution time) after adding this
optimization was measured using firefox-x64 from lld-speed-test [1]
with ldflags "-O2 -S" on an Apple M2 Ultra. The results are as follows:
```
N Min Max Median Avg Stddev
x 512 1.2264546 1.3481076 1.2970261 1.2965788 0.018620888
+ 512 1.2561196 1.3839965 1.3214632 1.3209327 0.019443971
Difference at 95.0% confidence
0.0243538 +/- 0.00233202
1.87831% +/- 0.179859%
(Student's t, pooled s = 0.0190369)
```
[1] https://discourse.llvm.org/t/improving-the-reproducibility-of-linker-benchmarking/86057
Pull Request: https://github.com/llvm/llvm-project/pull/138366
Commit: 6110dead894bec37d6373eda4cba2d5dc426f824
https://github.com/llvm/llvm-project/commit/6110dead894bec37d6373eda4cba2d5dc426f824
Author: Michael Spencer <bigcheesegs at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningFilesystem.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningService.h
M clang/lib/Tooling/DependencyScanning/DependencyScanningFilesystem.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningService.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
M clang/tools/clang-scan-deps/Opts.td
M clang/unittests/Tooling/DependencyScanning/DependencyScannerTest.cpp
M clang/unittests/Tooling/DependencyScanning/DependencyScanningFilesystemTest.cpp
Log Message:
-----------
[clang][scan-deps] Add option to disable caching stat failures (#144000)
While the source code isn't supposed to change during a build, in some
environments it does. This adds an option that disables caching of stat
failures, meaning that source files can be added to the build during
scanning.
This adds a `-no-cache-negative-stats` option to clang-scan-deps to
enable this behavior. There are no tests for clang-scan-deps as there's
no reliable way to do so from it. A unit test has been added that
modifies the filesystem between scans to test it.
Commit: 58f48011b3229b568d3a23a6f4853128712d5f8b
https://github.com/llvm/llvm-project/commit/58f48011b3229b568d3a23a6f4853128712d5f8b
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M lldb/examples/python/templates/scripted_process.py
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/Inputs/a.out.ips
Log Message:
-----------
[lldb] Add support for x86_64h to scripted process (#145099)
This patch adds support to the haswell sub-architecture (x86_64h) to
scripted processes.
rdar://147208252
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: b6445ac0c54992993b154875d6afb04eeaa13910
https://github.com/llvm/llvm-project/commit/b6445ac0c54992993b154875d6afb04eeaa13910
Author: David Green <david.green at arm.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/include/llvm/Target/GlobalISel/Combine.td
Log Message:
-----------
[GlobalISel] Create a common register_vector_matchinfo (#144306)
Several combiner use MatchInfo that are just SmallVector<Register>. This
creates a common register_vector_matchinfo that they can all use.
Commit: 9c1ce31f546368d6296bc881e9f576ad25c20c73
https://github.com/llvm/llvm-project/commit/9c1ce31f546368d6296bc881e9f576ad25c20c73
Author: Nishant Patel <nishant.b.patel at intel.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorUnroll.cpp
M mlir/test/Dialect/Vector/vector-unroll-options.mlir
M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
Log Message:
-----------
[mlir][vector] Add unroll patterns for vector.load and vector.store (#143420)
This PR adds unroll patterns for vector.load and vector.store. This PR is follow up of #137558
Commit: 4c97a91dc085fba40e5a86c4da8feeffd15b1f8a
https://github.com/llvm/llvm-project/commit/4c97a91dc085fba40e5a86c4da8feeffd15b1f8a
Author: sribee8 <sriya.pratipati at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M libc/hdr/types/mbstate_t.h
Log Message:
-----------
[libc] Added closing quote (#145101)
Error message was missing a closing quote, added it.
Co-authored-by: Sriya Pratipati <sriyap at google.com>
Commit: 0c2191b3a79d91d1115b1dbc1a9bd39daed1d9c5
https://github.com/llvm/llvm-project/commit/0c2191b3a79d91d1115b1dbc1a9bd39daed1d9c5
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Log Message:
-----------
[AMDGPU] Omit image waits in function prologue on gfx1250 (#145097)
Commit: 5886f0a18342457f142871ef73f40fc27f936d9b
https://github.com/llvm/llvm-project/commit/5886f0a18342457f142871ef73f40fc27f936d9b
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vle_vid-vfcvt.ll
Log Message:
-----------
[RISCV] Allow larger offset when matching build_vector as vid sequence (#144756)
I happened to notice that when legalizing get.active.lane.mask with
large vectors we were materializing via constant pool instead of just
shifting by a constant.
We should probably be doing a full cost comparison for the different
lowering strategies as opposed to our current adhoc heuristics, but the
few cases this regresses seem pretty minor. (Given the reduction in vset
toggles, they might not be regressions at all.)
---------
Co-authored-by: Craig Topper <craig.topper at sifive.com>
Commit: f0d32575a1193741bc9ca90e5beced693cba28b0
https://github.com/llvm/llvm-project/commit/f0d32575a1193741bc9ca90e5beced693cba28b0
Author: Amir Ayupov <aaupov at fb.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
Log Message:
-----------
[BOLT][NFCI] Use FileSymbols for local symbol disambiguation (#89088)
Remove SymbolToFileName mapping from every local symbol to its
containing FILE symbol name, and reuse FileSymbols to disambiguate
local symbols instead.
Also removes the check for `ld-temp.o` file symbol which was added to
prevent LTO build mode from affecting the disambiguated name. This may
cause incompatibility when using the profile collected on a binary built
in a different mode than the input binary.
Addresses #90661.
Speeds up discover file objects by 5-10% for large binaries:
- binary with ~1.2M symbols: 12.6422s -> 12.0297s
- binary with ~4.5M symbols: 48.8851s -> 43.7315s
Commit: a91154343780dae022bb314aa76f0b0affc28b62
https://github.com/llvm/llvm-project/commit/a91154343780dae022bb314aa76f0b0affc28b62
Author: Uzair Nawaz <uzairnawaz at google.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/wchar.yaml
M libc/src/__support/wchar/CMakeLists.txt
A libc/src/__support/wchar/wcrtomb.cpp
A libc/src/__support/wchar/wcrtomb.h
M libc/src/wchar/CMakeLists.txt
A libc/src/wchar/wcrtomb.cpp
A libc/src/wchar/wcrtomb.h
M libc/test/src/wchar/CMakeLists.txt
A libc/test/src/wchar/wcrtomb_test.cpp
Log Message:
-----------
[libc] Implemented wcrtomb internal function and public libc function (#144596)
Implemented internal wcrtomb function using the CharacterConverter class
public libc function calls this internal function to perform the
conversion
Commit: e6ee2c7c7b36825331b39e221725780167457e6d
https://github.com/llvm/llvm-project/commit/e6ee2c7c7b36825331b39e221725780167457e6d
Author: Finn Plummer <finn.c.plum at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/SemaHLSL/RootSignature-resource-ranges-err.hlsl
A clang/test/SemaHLSL/RootSignature-resource-ranges.hlsl
M llvm/include/llvm/Frontend/HLSL/HLSLRootSignatureUtils.h
M llvm/lib/Frontend/HLSL/HLSLRootSignatureUtils.cpp
Log Message:
-----------
[HLSL][RootSignature] Implement validation of resource ranges for `RootDescriptors` (#140962)
As was established
[previously](https://github.com/llvm/llvm-project/pull/140957), we
created a structure to model a resource range and to detect an overlap
in a given set of these.
However, a resource range only overlaps with another resource range if
they have:
- equivalent ResourceClass (SRV, UAV, CBuffer, Sampler)
- equivalent resource name-space
- overlapping shader visibility
For instance, the following don't overlap even though they have the same
register range:
- `CBV(b0)` and `SRV(t0)` (different resource class)
- `CBV(b0, space = 0)` and `CBV(b0, space = 1)` (different space)
- `CBV(b0, visibility = Pixel)` and `CBV(b0, visibility = Domain)`
(non-overlapping visibility)
The first two clauses are naturally modelled by grouping all the
`RangeInfo`s that have the equivalent `ResourceClass` and `Space` values
together and check if there is any overlap on a `ResourceRange` for all
these `RangeInfo`s. However, `Visibility` is not quite as easily mapped
(`Visibility = All` would overlap with any other visibility). So we will
instead need to track a `ResourceRange` for each of the `Visibility`
types in a group. Then we can determine when inserting a range of the
same group if it would overlap with any overlapping visibilities.
The collection of `RangeInfo` for `RootDescriptor`s, sorting of the
`RangeInfo`s into the groups and finally the insertion of each point
into their respective `ResourceRange`s are implemented. Furthermore, we
integrate this into `SemaHLSL` to provide a diagnostic for each entry
function that uses the invalid root signature.
- Implements collection of `RangeInfo` for `RootDescriptors`
- Implements resource range validation in `SemaHLSL`
- Add diagnostic testing of error production in
`RootSignature-resource-ranges-err.hlsl`
- Add testing to ensure no errors are raised in valid root signatures
`RootSignature-resource-ranges.hlsl`
Part 2 of https://github.com/llvm/llvm-project/issues/129942
A final pr will be produced to integrate the analysis of
`DescriptorTable`, `StaticSampler` and `RootConstants` by defining how
to construct the `RangeInfo` from their elements respectively.
Commit: 94865edfa85a61dd4ad985d2fb86990a1bba357b
https://github.com/llvm/llvm-project/commit/94865edfa85a61dd4ad985d2fb86990a1bba357b
Author: Anshil Gandhi <95053726+gandhi56 at users.noreply.github.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
A llvm/test/Transforms/InstCombine/AMDGPU/ptr-replace-alloca.ll
Log Message:
-----------
[Reland][InstCombine] Iterative replacement in PtrReplacer (#144626)
This patch enhances the PtrReplacer as follows:
1. Users are now collected iteratively to be generous on the stack. In the case of PHIs with incoming values which have not yet been visited, they are pushed back into the stack for reconsideration.
2. Replace users of the pointer root in a reverse-postorder traversal, instead of a simpletraversal over the collected users. This reordering ensures that the uses of an instruction are replaced before replacing the instruction itself.
3. During the replacement of PHI, use the same incoming value if it does not have a replacement.
This patch specifically fixes the case when an incoming value of a PHI
is addrspacecasted.
This is a reland of https://github.com/llvm/llvm-project/pull/137215.
Commit: b7be8786af42d131974ec9cfc3ba79b264511b7b
https://github.com/llvm/llvm-project/commit/b7be8786af42d131974ec9cfc3ba79b264511b7b
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M .ci/compute_projects.py
M .ci/compute_projects_test.py
M .ci/monolithic-linux.sh
M .github/workflows/premerge.yaml
Log Message:
-----------
Reapply "[CI] Migrate to runtimes build" (#143612)
This reverts commit 6f62979a5a5bcf70d65f23e0991a274e6df5955b.
The reapplies commit 80ea5f46df3e365a0a2112889bb91732167b6214.
That commit was reverted because it was causing compiler-rt test
failures due to tysan not having its dependencies set up properly within
CMake. That situation has since been rectified in
3cef099ceddccefca8e11268624397cde9e04af6.
Reviewers: lnihlen, rnk, gburgessiv, cmtice
Reviewed By: rnk, cmtice
Pull Request: https://github.com/llvm/llvm-project/pull/144033
Commit: 1db9afb102acbb447ee374851d11fcdbea7fe5ec
https://github.com/llvm/llvm-project/commit/1db9afb102acbb447ee374851d11fcdbea7fe5ec
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M lldb/examples/python/crashlog.py
M lldb/examples/python/crashlog_scripted_process.py
A lldb/test/Shell/ScriptInterpreter/Python/Crashlog/interactive_crashlog_arm64_register.test
Log Message:
-----------
[lldb/crashlog] Make registers always available & fix x29/x30 parsing (#145104)
This patch addresses 2 issues:
1. It makes registers available on non-crashed threads all the time
2. It fixes arm64 registers parsing for registers that don't use the `x`
prefix (`fp` -> `x29` / `lr` -> `x30`)
---------
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: 1753aba0342bd286d65d1c8465b9fa2659424766
https://github.com/llvm/llvm-project/commit/1753aba0342bd286d65d1c8465b9fa2659424766
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-21 (Sat, 21 Jun 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/oddshuffles.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
Log Message:
-----------
[X86] combineINSERT_SUBVECTOR - directly fold to X86ISD::SUBV_BROADCAST_LOAD to prevent vector split infinite loop (#145077)
This reverts #140919 / f1d03dedfbe87119cfcafb07e0e0f90ec291cb97 - which
could result in another fold trying to split the concatenation apart
again before it was folded to a SUBV_BROADCAST_LOAD
Commit: ad36800d65250618b1c1446ae0f97d250bf09df8
https://github.com/llvm/llvm-project/commit/ad36800d65250618b1c1446ae0f97d250bf09df8
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2025-06-21 (Sat, 21 Jun 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/lld/BUILD.bazel
Log Message:
-----------
[bazel][lld] Follow up 491b82a5ec1a (llvmorg-21-init-16192-g491b82a5ec1a)
Commit: be7e4113c84317feda055cac68a855429e46e381
https://github.com/llvm/llvm-project/commit/be7e4113c84317feda055cac68a855429e46e381
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Transforms/IPO/ElimAvailExtern.cpp
Log Message:
-----------
[NFC] Add comment to describe the intention use of newly added `avail-extern-gv-in-addrspace-to-local` (#144911)
Commit: 6b9fe9e0bc7421d89f38ade857c91f0ae153ad9c
https://github.com/llvm/llvm-project/commit/6b9fe9e0bc7421d89f38ade857c91f0ae153ad9c
Author: Justin Bogner <mail at justinbogner.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/test/CodeGenHLSL/RootSignature.hlsl
M llvm/lib/Target/DirectX/DXILRootSignature.cpp
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Error.ll
Log Message:
-----------
[HLSL] Emit a version in the dx.rootsignatures metadata (#145113)
In #144957 the backend was updated to expect a version in the metadata,
but since the frontend wasn't updated this breaks compilation. This is a
somewhat temporary fix to that until #144813 lands.
Commit: 2dfcc4375faa5e3692bd82a022d33bdd6fe55f10
https://github.com/llvm/llvm-project/commit/2dfcc4375faa5e3692bd82a022d33bdd6fe55f10
Author: Erick Velez <erickvelez7 at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
A clang-tools-extra/test/clang-doc/json/class-requires.cpp
A clang-tools-extra/test/clang-doc/json/concept.cpp
A clang-tools-extra/test/clang-doc/json/function-requires.cpp
Log Message:
-----------
[clang-doc] Precommit concept tests (#144160)
Commit: 8050a6e0732c6614ce3e5296fdeb5a3c36bde26d
https://github.com/llvm/llvm-project/commit/8050a6e0732c6614ce3e5296fdeb5a3c36bde26d
Author: Erick Velez <erickvelez7 at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M clang-tools-extra/clang-doc/BitcodeReader.cpp
M clang-tools-extra/clang-doc/BitcodeWriter.cpp
M clang-tools-extra/clang-doc/BitcodeWriter.h
M clang-tools-extra/clang-doc/HTMLGenerator.cpp
M clang-tools-extra/clang-doc/HTMLMustacheGenerator.cpp
M clang-tools-extra/clang-doc/JSONGenerator.cpp
M clang-tools-extra/clang-doc/MDGenerator.cpp
M clang-tools-extra/clang-doc/Mapper.cpp
M clang-tools-extra/clang-doc/Mapper.h
M clang-tools-extra/clang-doc/Representation.cpp
M clang-tools-extra/clang-doc/Representation.h
M clang-tools-extra/clang-doc/Serialize.cpp
M clang-tools-extra/clang-doc/Serialize.h
M clang-tools-extra/clang-doc/YAMLGenerator.cpp
M clang-tools-extra/test/clang-doc/json/class-requires.cpp
A clang-tools-extra/test/clang-doc/json/compound-constraints.cpp
M clang-tools-extra/test/clang-doc/json/concept.cpp
M clang-tools-extra/test/clang-doc/json/function-requires.cpp
M clang-tools-extra/unittests/clang-doc/BitcodeTest.cpp
Log Message:
-----------
[clang-doc] add support for concepts (#144430)
Add support for documenting concepts. This handles concepts and constraints on function and class templates.
Atomic constraints are not considered yet. We don't order constraints based on their conjunctive or disjunctive properties.
Commit: 72979093e79ca905eac7ce951423f8b0f81c28a8
https://github.com/llvm/llvm-project/commit/72979093e79ca905eac7ce951423f8b0f81c28a8
Author: Anshil Gandhi <95053726+gandhi56 at users.noreply.github.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
R llvm/test/Transforms/InstCombine/AMDGPU/ptr-replace-alloca.ll
Log Message:
-----------
Revert "[Reland][InstCombine] Iterative replacement in PtrReplacer" (#145137)
Reverts llvm/llvm-project#144626
Commit: 17e8465a3eb0cae48b9f62d27fd26f2b070f1f9b
https://github.com/llvm/llvm-project/commit/17e8465a3eb0cae48b9f62d27fd26f2b070f1f9b
Author: Fangrui Song <i at maskray.me>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64MCInstLower.cpp
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFObjectWriter.cpp
Log Message:
-----------
AArch64: Replace AArch64MCExpr with MCSpecifierExpr
Replace AArch64MCExpr, which encodes expressions with relocation
specifiers, with the new generic MCSpecifierExpr interface, aligning
with other targets by phasing out target-specific XXXMCExpr classes.
Temporarily convert AArch64MCExpr to a namespace to avoid renaming
`AArch64MCExpr::VK_` constants in this PR. A follow-up patch will rename
these to `AArch64::S_` to match the convention used by other targets.
Move helper functions to AArch64MCAsmInfo.h, with the goal of eventually
removing AArch64MCExpr.h.
Pull Request: https://github.com/llvm/llvm-project/pull/144632
Commit: 95fbfc9be5d2842a945c04a20fe6244df9b10e18
https://github.com/llvm/llvm-project/commit/95fbfc9be5d2842a945c04a20fe6244df9b10e18
Author: Fangrui Song <i at maskray.me>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M .ci/compute_projects.py
M .ci/compute_projects_test.py
M .ci/monolithic-linux.sh
M .github/workflows/libcxx-restart-preempted-jobs.yaml
M .github/workflows/premerge.yaml
M bolt/include/bolt/Passes/PAuthGadgetScanner.h
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/include/bolt/Utils/CommandLineOpts.h
M bolt/lib/Passes/PAuthGadgetScanner.cpp
M bolt/lib/Profile/BoltAddressTranslation.cpp
M bolt/lib/Profile/DataAggregator.cpp
M bolt/lib/Rewrite/LinuxKernelRewriter.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/test/AArch64/r_aarch64_prelxx.s
M bolt/test/X86/callcont-fallthru.s
M bolt/test/X86/linux-version.S
M bolt/test/X86/register-fragments-bolt-symbols.s
A bolt/test/binary-analysis/AArch64/gs-pauth-authentication-oracles.s
M bolt/test/binary-analysis/AArch64/gs-pauth-debug-output.s
M bolt/test/link_fdata.py
A bolt/test/perf2bolt/AArch64/perf2bolt-spe.test
A bolt/test/perf2bolt/X86/perf2bolt-spe.test
M bolt/tools/driver/llvm-bolt.cpp
M bolt/unittests/Profile/CMakeLists.txt
A bolt/unittests/Profile/PerfSpeEvents.cpp
M clang-tools-extra/clang-doc/BitcodeReader.cpp
M clang-tools-extra/clang-doc/BitcodeWriter.cpp
M clang-tools-extra/clang-doc/BitcodeWriter.h
M clang-tools-extra/clang-doc/HTMLGenerator.cpp
M clang-tools-extra/clang-doc/HTMLMustacheGenerator.cpp
M clang-tools-extra/clang-doc/JSONGenerator.cpp
M clang-tools-extra/clang-doc/MDGenerator.cpp
M clang-tools-extra/clang-doc/Mapper.cpp
M clang-tools-extra/clang-doc/Mapper.h
M clang-tools-extra/clang-doc/Representation.cpp
M clang-tools-extra/clang-doc/Representation.h
M clang-tools-extra/clang-doc/Serialize.cpp
M clang-tools-extra/clang-doc/Serialize.h
M clang-tools-extra/clang-doc/YAMLGenerator.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/CMakeLists.txt
M clang-tools-extra/clang-tidy/cppcoreguidelines/CppCoreGuidelinesTidyModule.cpp
A clang-tools-extra/clang-tidy/cppcoreguidelines/UseEnumClassCheck.cpp
A clang-tools-extra/clang-tidy/cppcoreguidelines/UseEnumClassCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines/use-enum-class.rst
M clang-tools-extra/docs/clang-tidy/checks/list.rst
A clang-tools-extra/test/clang-doc/json/class-requires.cpp
A clang-tools-extra/test/clang-doc/json/compound-constraints.cpp
A clang-tools-extra/test/clang-doc/json/concept.cpp
A clang-tools-extra/test/clang-doc/json/function-requires.cpp
A clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/use-enum-class.cpp
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M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/Floating.h
M clang/lib/AST/ByteCode/Integral.h
M clang/lib/AST/ByteCode/IntegralAP.h
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M clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
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M clang/lib/CodeGen/CGCleanup.cpp
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M clang/lib/CodeGen/CGHLSLRuntime.cpp
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M clang/lib/CodeGen/CGObjCGNU.cpp
M clang/lib/CodeGen/CGObjCMac.cpp
M clang/lib/CodeGen/CGObjCRuntime.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
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M clang/lib/CodeGen/Targets/NVPTX.cpp
M clang/lib/CodeGen/Targets/SPIR.cpp
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M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
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A clang/lib/Driver/ToolChains/Managarm.cpp
A clang/lib/Driver/ToolChains/Managarm.h
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R clang/lib/Headers/cuda_wrappers/bits/c++config.h
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A clang/test/CIR/Transforms/vector-splat.cir
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A clang/test/CodeGen/PowerPC/ppc-dmf-paired-vec-memops-builtin-err.c
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M clang/test/CodeGen/builtin_vectorelements.c
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A clang/test/Driver/Inputs/basic_managarm_tree/usr/lib64/.keep
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M clang/test/Driver/amdgpu-mcpu.cl
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M clang/test/Driver/hip-thinlto.hip
A clang/test/Driver/managarm.cpp
M clang/test/Driver/openmp-offload-gpu.c
M clang/test/Driver/ppc-crbits.cpp
M clang/test/Driver/ppc-isa-features.cpp
A clang/test/Driver/spirv-amd-toolchain.c
M clang/test/ExtractAPI/objc_instancetype.m
M clang/test/Misc/loop-opt-setup.c
M clang/test/Misc/target-invalid-cpu-note/amdgcn.c
M clang/test/Misc/target-invalid-cpu-note/nvptx.c
A clang/test/Modules/pr144230.cppm
M clang/test/PCH/ignored-pch.c
M clang/test/Preprocessor/init.c
M clang/test/Preprocessor/predefined-arch-macros.c
M clang/test/Preprocessor/predefined-macros-no-warnings.c
A clang/test/Sema/ppc-dmf-types.c
M clang/test/SemaCXX/exception-spec.cpp
A clang/test/SemaHLSL/RootSignature-resource-ranges-err.hlsl
A clang/test/SemaHLSL/RootSignature-resource-ranges.hlsl
A clang/test/SemaHLSL/vk.spec-constant.error.hlsl
M clang/test/SemaObjCXX/arc-type-conversion.mm
M clang/test/SemaTemplate/concepts-out-of-line-def.cpp
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
M clang/tools/clang-scan-deps/Opts.td
M clang/unittests/Tooling/DependencyScanning/DependencyScannerTest.cpp
M clang/unittests/Tooling/DependencyScanning/DependencyScanningFilesystemTest.cpp
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M clang/utils/TableGen/ClangDiagnosticsEmitter.cpp
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M compiler-rt/lib/lsan/lsan_allocator.h
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M compiler-rt/lib/lsan/lsan_malloc_mac.cpp
M compiler-rt/lib/msan/msan_interceptors.cpp
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A compiler-rt/test/profile/Posix/gcov-file-change-line.cpp
M compiler-rt/test/profile/Posix/gcov-file-change.cpp
A compiler-rt/test/sanitizer_common/TestCases/Linux/free_aligned_sized.c
A compiler-rt/test/sanitizer_common/TestCases/Linux/free_sized.c
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M flang/include/flang/Optimizer/Dialect/FIROps.td
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M flang/include/flang/Support/Fortran-features.h
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A flang/lib/Lower/OpenMP/Atomic.cpp
A flang/lib/Lower/OpenMP/Atomic.h
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
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M libc/cmake/modules/LLVMLibCCompileOptionRules.cmake
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M libcxx/test/std/containers/sequences/list/list.cons/input_iterator.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/move.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/move_alloc.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/op_equal_initializer_list.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/size_type.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/size_value_alloc.pass.cpp
M libcxx/test/std/containers/sequences/list/list.erasure/erase.pass.cpp
M libcxx/test/std/containers/sequences/list/list.erasure/erase_if.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/append_range.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/assign_range.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/clear.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/emplace.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/emplace_back.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/emplace_front.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/erase_iter.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/erase_iter_iter.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/insert_iter_initializer_list.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/insert_iter_iter_iter.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/insert_iter_rvalue.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/insert_iter_size_value.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/insert_iter_value.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/insert_range.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/pop_back.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/pop_front.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/prepend_range.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/push_back.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/push_back_rvalue.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/push_front.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/push_front_rvalue.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/merge.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/merge_comp.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/remove.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/remove_if.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/reverse.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/sort.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/sort_comp.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/splice_pos_list.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/splice_pos_list_iter.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/splice_pos_list_iter_iter.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/unique.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/unique_pred.pass.cpp
M libcxx/test/std/containers/sequences/list/list.special/swap.pass.cpp
M libcxx/test/std/containers/sequences/list/list.special/swap_noexcept.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/expected.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/list.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/optional.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/tuple.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/utility.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/variant.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
M libcxx/test/std/numerics/c.math/abs.pass.cpp
M libcxx/test/std/numerics/c.math/abs.verify.cpp
M libcxx/test/std/utilities/format/format.functions/escaped_output.unicode.pass.cpp
M libcxx/test/std/utilities/format/format.functions/fill.unicode.pass.cpp
M libcxx/test/support/min_allocator.h
M libcxx/utils/generate_feature_test_macro_components.py
M lld/ELF/Arch/AArch64.cpp
A lld/ELF/Arch/TargetImpl.h
M lld/ELF/Arch/X86_64.cpp
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/Options.td
M lld/ELF/Relocations.cpp
M lld/ELF/Target.h
M lld/ELF/Thunks.cpp
M lld/docs/ReleaseNotes.rst
M lld/docs/ld.lld.1
A lld/test/ELF/aarch64-branch-to-branch.s
M lld/test/ELF/aarch64-thunk-bti-multipass.s
A lld/test/ELF/x86-64-branch-to-branch.s
M lldb/cmake/modules/LLDBConfig.cmake
M lldb/examples/python/crashlog.py
M lldb/examples/python/crashlog_scripted_process.py
M lldb/examples/python/templates/scripted_process.py
M lldb/include/lldb/Core/Debugger.h
M lldb/include/lldb/Core/DemangledNameInfo.h
M lldb/include/lldb/Core/PluginManager.h
A lldb/include/lldb/Core/ProtocolServer.h
M lldb/include/lldb/Host/Socket.h
M lldb/include/lldb/Interpreter/CommandOptionArgumentTable.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/include/lldb/lldb-forward.h
M lldb/include/lldb/lldb-private-interfaces.h
M lldb/source/API/CMakeLists.txt
M lldb/source/Breakpoint/Breakpoint.cpp
M lldb/source/Commands/CMakeLists.txt
A lldb/source/Commands/CommandObjectProtocolServer.cpp
A lldb/source/Commands/CommandObjectProtocolServer.h
M lldb/source/Core/CMakeLists.txt
M lldb/source/Core/CoreProperties.td
M lldb/source/Core/Debugger.cpp
M lldb/source/Core/PluginManager.cpp
A lldb/source/Core/ProtocolServer.cpp
M lldb/source/Host/common/Socket.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Plugins/CMakeLists.txt
M lldb/source/Plugins/Process/AIX/CMakeLists.txt
A lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX.cpp
A lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX.h
M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
A lldb/source/Plugins/Protocol/CMakeLists.txt
A lldb/source/Plugins/Protocol/MCP/CMakeLists.txt
A lldb/source/Plugins/Protocol/MCP/MCPError.cpp
A lldb/source/Plugins/Protocol/MCP/MCPError.h
A lldb/source/Plugins/Protocol/MCP/Protocol.cpp
A lldb/source/Plugins/Protocol/MCP/Protocol.h
A lldb/source/Plugins/Protocol/MCP/ProtocolServerMCP.cpp
A lldb/source/Plugins/Protocol/MCP/ProtocolServerMCP.h
A lldb/source/Plugins/Protocol/MCP/Tool.cpp
A lldb/source/Plugins/Protocol/MCP/Tool.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.h
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/ValueObject/DILParser.cpp
M lldb/test/API/commands/frame/var-dil/basics/ArraySubscript/TestFrameVarDILArraySubscript.py
M lldb/test/API/commands/frame/var-dil/basics/ArraySubscript/main.cpp
M lldb/test/API/commands/register/register/aarch64_mte_ctrl_register/TestMTECtrlRegister.py
M lldb/test/API/python_api/watchpoint/watchlocation/TestTargetWatchAddress.py
A lldb/test/API/terminal/TestDisabledBreakpoints.py
M lldb/test/API/tools/lldb-dap/memory/TestDAP_memory.py
M lldb/test/API/tools/lldb-dap/server/TestDAP_server.py
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/Inputs/a.out.ips
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/altered_threadState.test
A lldb/test/Shell/ScriptInterpreter/Python/Crashlog/interactive_crashlog_arm64_register.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/json.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/no_threadState.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/skipped_status_interactive_crashlog.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/text.test
M lldb/test/Shell/SymbolFile/DWARF/x86/explicit-member-function-quals.cpp
M lldb/tools/lldb-dap/Handler/ReadMemoryRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
M lldb/tools/lldb-dap/Options.td
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
M lldb/tools/lldb-dap/src-ts/lldb-dap-server.ts
M lldb/tools/lldb-dap/tool/lldb-dap.cpp
M lldb/unittests/CMakeLists.txt
M lldb/unittests/Core/MangledTest.cpp
M lldb/unittests/DAP/ProtocolTypesTest.cpp
A lldb/unittests/Protocol/CMakeLists.txt
A lldb/unittests/Protocol/ProtocolMCPServerTest.cpp
A lldb/unittests/Protocol/ProtocolMCPTest.cpp
M lldb/unittests/SymbolFile/DWARF/DWARFASTParserClangTests.cpp
M lldb/unittests/TestingSupport/TestUtilities.h
M llvm/cmake/modules/HandleLLVMOptions.cmake
M llvm/cmake/modules/TableGen.cmake
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/CommandGuide/llvm-opt-report.rst
M llvm/docs/NVPTXUsage.rst
M llvm/docs/Remarks.rst
M llvm/docs/TableGen/ProgRef.rst
M llvm/include/llvm/ADT/PointerIntPair.h
M llvm/include/llvm/Analysis/HashRecognize.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/BinaryFormat/DXContainer.h
M llvm/include/llvm/BinaryFormat/DXContainerConstants.def
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV_nonstandard.def
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/FunctionLoweringInfo.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/include/llvm/DebugInfo/LogicalView/Core/LVElement.h
M llvm/include/llvm/DebugInfo/LogicalView/Core/LVScope.h
M llvm/include/llvm/DebugInfo/LogicalView/Core/LVSupport.h
M llvm/include/llvm/Frontend/HLSL/HLSLRootSignatureUtils.h
M llvm/include/llvm/IR/IRBuilder.h
M llvm/include/llvm/IR/IntrinsicInst.h
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/PatternMatch.h
M llvm/include/llvm/IR/RuntimeLibcalls.h
M llvm/include/llvm/MC/MCTargetOptions.h
M llvm/include/llvm/ProfileData/GCOV.h
M llvm/include/llvm/ProfileData/MemProfReader.h
M llvm/include/llvm/Remarks/RemarkFormat.h
M llvm/include/llvm/Remarks/RemarkLinker.h
M llvm/include/llvm/Remarks/RemarkParser.h
M llvm/include/llvm/Remarks/YAMLRemarkSerializer.h
M llvm/include/llvm/Support/CodeGen.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/include/llvm/Target/TargetOptions.h
M llvm/include/llvm/TargetParser/CMakeLists.txt
M llvm/include/llvm/TargetParser/PPCTargetParser.h
M llvm/include/llvm/TargetParser/TargetParser.h
M llvm/include/llvm/Transforms/IPO/Attributor.h
M llvm/include/llvm/Transforms/Scalar/JumpThreading.h
M llvm/include/llvm/Transforms/Utils/SCCPSolver.h
M llvm/lib/Analysis/HashRecognize.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
M llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
M llvm/lib/CodeGen/MachineBlockPlacement.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/ExecutionEngine/JITLink/COFFDirectiveParser.cpp
M llvm/lib/ExecutionEngine/Orc/UnwindInfoRegistrationPlugin.cpp
M llvm/lib/Frontend/HLSL/HLSLRootSignatureUtils.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/IRBuilder.cpp
M llvm/lib/IR/IntrinsicInst.cpp
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Linker/IRMover.cpp
M llvm/lib/Object/ELFObjectFile.cpp
M llvm/lib/Object/IRSymtab.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/ProfileData/GCOV.cpp
M llvm/lib/Remarks/BitstreamRemarkParser.cpp
M llvm/lib/Remarks/BitstreamRemarkParser.h
M llvm/lib/Remarks/RemarkFormat.cpp
M llvm/lib/Remarks/RemarkLinker.cpp
M llvm/lib/Remarks/RemarkParser.cpp
M llvm/lib/Remarks/RemarkSerializer.cpp
M llvm/lib/Remarks/RemarkStreamer.cpp
M llvm/lib/Remarks/YAMLRemarkParser.cpp
M llvm/lib/Remarks/YAMLRemarkParser.h
M llvm/lib/Remarks/YAMLRemarkSerializer.cpp
M llvm/lib/Support/BLAKE3/CMakeLists.txt
M llvm/lib/Target/AArch64/AArch64.td
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64Processors.td
A llvm/lib/Target/AArch64/AArch64SchedA320.td
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUUnifyMetadata.cpp
M llvm/lib/Target/AMDGPU/GCNProcessors.td
M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMAsmPrinter.h
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
M llvm/lib/Target/BPF/BPFPreserveStaticOffset.cpp
M llvm/lib/Target/BPF/BTFDebug.cpp
M llvm/lib/Target/DirectX/DXILDataScalarization.cpp
M llvm/lib/Target/DirectX/DXILRootSignature.cpp
M llvm/lib/Target/DirectX/DXILRootSignature.h
M llvm/lib/Target/NVPTX/NVPTX.td
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/PowerPC/PPC.td
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.h
M llvm/lib/Target/PowerPC/PPCInstrMMA.td
M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/RISCVCallingConv.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVInstrFormats.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/lib/Target/Sparc/Sparc.td
M llvm/lib/Target/Sparc/SparcInstrInfo.td
M llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
M llvm/lib/Target/VE/VEISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86AsmPrinter.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/TargetParser/PPCTargetParser.cpp
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/lib/Transforms/IPO/Attributor.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/IPO/ElimAvailExtern.cpp
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
M llvm/lib/Transforms/IPO/SCCP.cpp
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Instrumentation/GCOVProfiling.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
M llvm/lib/Transforms/Utils/PredicateInfo.cpp
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/test/Analysis/HashRecognize/cyclic-redundancy-check.ll
M llvm/test/Analysis/ValueTracking/phi-known-bits.ll
A llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmov-gpr32.ll
R llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmov.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-splat-scalable.ll
A llvm/test/CodeGen/AArch64/cpa-globalisel.ll
A llvm/test/CodeGen/AArch64/cpa-selectiondag.ll
M llvm/test/CodeGen/AArch64/min-jump-table.ll
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/stack-hazard.ll
A llvm/test/CodeGen/AArch64/sve-bf16-reductions.ll
A llvm/test/CodeGen/AArch64/sve-fixed-length-splat-segment.ll
A llvm/test/CodeGen/AArch64/sve2p1-vector-shuffles.ll
M llvm/test/CodeGen/AArch64/trampoline.ll
A llvm/test/CodeGen/AArch64/unsupported-cc-call.ll
A llvm/test/CodeGen/AArch64/unsupported-cc-func.ll
A llvm/test/CodeGen/AArch64/vector-ldst-offset.ll
M llvm/test/CodeGen/AArch64/zext-to-tbl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
M llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll
M llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
A llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-gfx12-fake16.mir
A llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-gfx12-true16.mir
A llvm/test/CodeGen/AMDGPU/gcn-reg-pressure-true16-integer-overflow.mir
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/insert-skips-gfx12.mir
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-ignorable-exec-use.mir
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-fake16.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
A llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
A llvm/test/CodeGen/BPF/BTF/map-def-nested.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-AllValidFlagCombinations.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-AllValidFlagCombinationsV1.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-Invalid-Flag.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-Invalid-RangeType.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-Invalid-RegisterSpace.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Error-is-not-function.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Error-is-not-value.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Error-no-root-element-list.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Error-root-element-not-mdnode.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Error.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Flags-Error.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Flags.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-MultipleEntryFunctions.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-NullFunction-Error.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Parameters-Invalid-ParameterIsNotString.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Parameters-Validation-Error.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Parameters.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootConstants-Invalid-Num32BitValues.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootConstants-Invalid-RegisterSpace.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootConstants-Invalid-ShaderRegister.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootConstants.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor-Invalid-Flags.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor-Invalid-RegisterKind.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor-Invalid-RegisterSpace.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor-Invalid-RegisterValue.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor_V1.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootElement-Error.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootFlags-VisibilityValidationError.ll
M llvm/test/CodeGen/DirectX/scalarize-alloca.ll
A llvm/test/CodeGen/DirectX/scalarize-dynamic-vector-index.ll
M llvm/test/CodeGen/NVPTX/sm-version.ll
M llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll
M llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
M llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
M llvm/test/CodeGen/PowerPC/aix-cc-byval-mir.ll
M llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-mir.ll
M llvm/test/CodeGen/PowerPC/aix-vec-arg-spills.ll
M llvm/test/CodeGen/PowerPC/aix-vector-vararg-caller.ll
M llvm/test/CodeGen/PowerPC/aix-vector-vararg-fixed-caller.ll
A llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg-mir.ll
M llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
A llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg-mir.ll
M llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll
M llvm/test/CodeGen/PowerPC/all-atomics.ll
M llvm/test/CodeGen/PowerPC/dmr-spill.ll
A llvm/test/CodeGen/PowerPC/dmrp-spill.ll
M llvm/test/CodeGen/PowerPC/f128-arith.ll
M llvm/test/CodeGen/PowerPC/loop-comment.ll
M llvm/test/CodeGen/RISCV/branch.ll
A llvm/test/CodeGen/RISCV/icmp-non-byte-sized.ll
M llvm/test/CodeGen/RISCV/interrupt-attr.ll
M llvm/test/CodeGen/RISCV/memcmp-optsize.ll
M llvm/test/CodeGen/RISCV/memcmp.ll
M llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmaccbf16.ll
M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
A llvm/test/CodeGen/RISCV/rvv/interrupt-attr-nocall.ll
M llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
M llvm/test/CodeGen/RISCV/rvv/vle_vid-vfcvt.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
M llvm/test/CodeGen/RISCV/shifts.ll
M llvm/test/CodeGen/RISCV/xqcibm-extract.ll
M llvm/test/CodeGen/SPARC/ctlz.ll
M llvm/test/CodeGen/SPARC/cttz.ll
M llvm/test/CodeGen/SPARC/inlineasm-v9.ll
M llvm/test/CodeGen/SPARC/inlineasm.ll
A llvm/test/CodeGen/SPIRV/linkage/link-attribute-vk.ll
A llvm/test/CodeGen/SystemZ/fake-use-size.ll
M llvm/test/CodeGen/Thumb2/mve-shuffle.ll
M llvm/test/CodeGen/Thumb2/mve-vld3.ll
M llvm/test/CodeGen/Thumb2/schedm7-hazard.ll
A llvm/test/CodeGen/X86/fold-masked-merge-demorgan.ll
M llvm/test/CodeGen/X86/kcfi-arity.ll
M llvm/test/CodeGen/X86/movmsk-cmp.ll
M llvm/test/CodeGen/X86/oddshuffles.ll
M llvm/test/CodeGen/X86/ptest.ll
M llvm/test/CodeGen/X86/remarks-section.ll
M llvm/test/CodeGen/X86/vector-fshl-256.ll
M llvm/test/CodeGen/X86/vector-fshr-256.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
M llvm/test/CodeGen/X86/vector-shift-shl-256.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll
M llvm/test/Instrumentation/AddressSanitizer/asan-masked-load-store.ll
M llvm/test/Instrumentation/AddressSanitizer/asan-vp-load-store.ll
M llvm/test/Instrumentation/AddressSanitizer/vector-load-store.ll
M llvm/test/Instrumentation/BoundsChecking/simple.ll
M llvm/test/Instrumentation/HWAddressSanitizer/vector-load-store.ll
M llvm/test/Instrumentation/MemorySanitizer/partial-poison.ll
M llvm/test/Instrumentation/MemorySanitizer/vector-load-store.ll
M llvm/test/Instrumentation/MemorySanitizer/vscale.ll
M llvm/test/Instrumentation/ThreadSanitizer/atomic-non-integer.ll
M llvm/test/MC/AArch64/coff-function-type-info.ll
A llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s
M llvm/test/MC/AMDGPU/gfx12_asm_smem.s
M llvm/test/MC/AMDGPU/gfx12_asm_sopk.s
M llvm/test/MC/AMDGPU/gfx12_asm_sopp.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s
A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sopp.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_smem.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopp.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp8.txt
M llvm/test/MC/RISCV/custom_reloc.s
M llvm/test/MC/RISCV/vendor-symbol.s
A llvm/test/MC/RISCV/xandesperf-fixups-diagnostics.s
A llvm/test/MC/RISCV/xandesperf-relocation.s
M llvm/test/MC/RISCV/xqciac-valid.s
M llvm/test/MC/Sparc/Relocations/relocation-specifier.s
M llvm/test/MC/Sparc/sparcv9-instructions.s
M llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
R llvm/test/Transforms/Attributor/AMDGPU/tag-invariant-loads.ll
M llvm/test/Transforms/Attributor/dereferenceable-1.ll
M llvm/test/Transforms/Attributor/value-simplify-local-remote.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-counting-elems.ll
M llvm/test/Transforms/InstCombine/X86/x86-vector-shifts.ll
M llvm/test/Transforms/InstCombine/and-or-icmps.ll
M llvm/test/Transforms/InstCombine/apint-shift.ll
A llvm/test/Transforms/InstCombine/bitcast-known-bits.ll
M llvm/test/Transforms/InstCombine/call-cast-target.ll
A llvm/test/Transforms/InstCombine/dead-alloc-elim.ll
A llvm/test/Transforms/InstCombine/fmul-tan-cos.ll
M llvm/test/Transforms/InstCombine/fp-ret-bitcast.ll
M llvm/test/Transforms/InstCombine/gep-vector.ll
M llvm/test/Transforms/InstCombine/gepofconstgepi8.ll
M llvm/test/Transforms/InstCombine/getelementptr.ll
M llvm/test/Transforms/InstCombine/icmp-gep.ll
M llvm/test/Transforms/InstCombine/malloc-free.ll
M llvm/test/Transforms/InstCombine/masked_intrinsics.ll
M llvm/test/Transforms/InstCombine/multiple-uses-load-bitcast-select.ll
M llvm/test/Transforms/InstCombine/objsize.ll
M llvm/test/Transforms/InstCombine/opaque-ptr.ll
M llvm/test/Transforms/InstCombine/scalable-vector-array.ll
M llvm/test/Transforms/InstCombine/scalable-vector-struct.ll
M llvm/test/Transforms/InstCombine/select-load.ll
M llvm/test/Transforms/InstCombine/shift-amount-reassociation.ll
M llvm/test/Transforms/InstCombine/sub-gep.ll
A llvm/test/Transforms/InstCombine/sub-sext-add.ll
M llvm/test/Transforms/InstCombine/vp-reverse.ll
M llvm/test/Transforms/InstCombine/vscale_gep.ll
M llvm/test/Transforms/LICM/call-hoisting.ll
M llvm/test/Transforms/LICM/funclet.ll
M llvm/test/Transforms/LoopVectorize/AArch64/clamped-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/divs-with-scalable-vfs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/eliminate-tail-predication.ll
M llvm/test/Transforms/LoopVectorize/AArch64/gather-do-not-vectorize-addressing.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll
M llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_prefer_scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
A llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-interleave.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
M llvm/test/Transforms/LoopVectorize/AArch64/pr60831-sve-inv-store-crash.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-avoid-scalarization.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-reduction-inloop-cond.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
M llvm/test/Transforms/LoopVectorize/AArch64/simple_early_exit.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-inloop-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-no-remaining-iterations.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-strict-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-extract-last-veclane.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-fneg.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inv-store.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-live-out-pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-multiexit.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-runtime-check-size-based-threshold.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-forced.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-optsize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-unroll.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-vscale-based-trip-counts.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-gep.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-too-many-deps.ll
M llvm/test/Transforms/LoopVectorize/AArch64/tail-folding-styles.ll
M llvm/test/Transforms/LoopVectorize/AArch64/uniform-args-call-variants.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vplan-printing.ll
M llvm/test/Transforms/LoopVectorize/AArch64/wider-VF-for-callinst.ll
A llvm/test/Transforms/LoopVectorize/ARM/mve-reductions-interleave.ll
M llvm/test/Transforms/LoopVectorize/RISCV/bf16.ll
M llvm/test/Transforms/LoopVectorize/RISCV/blend-any-of-reduction-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/defaults.ll
M llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
M llvm/test/Transforms/LoopVectorize/RISCV/f16.ll
M llvm/test/Transforms/LoopVectorize/RISCV/first-order-recurrence-scalable-vf1.ll
M llvm/test/Transforms/LoopVectorize/RISCV/fminimumnum.ll
M llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-masked-access.ll
M llvm/test/Transforms/LoopVectorize/RISCV/lmul.ll
M llvm/test/Transforms/LoopVectorize/RISCV/low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/RISCV/mask-index-type.ll
M llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll
M llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
M llvm/test/Transforms/LoopVectorize/RISCV/remark-reductions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse-output.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/RISCV/safe-dep-distance.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-basics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-tailfold.ll
M llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-bin-unary-ops-args.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cond-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-div.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-interleave.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-intermediate-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-iv32.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-known-no-overflow.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-masked-loadstore.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-ordered-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-safe-dep-distance.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-uniform-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/branch-weights.ll
M llvm/test/Transforms/LoopVectorize/dereferenceable-info-from-assumption-constant-size.ll
M llvm/test/Transforms/LoopVectorize/dereferenceable-info-from-assumption-variable-size.ll
M llvm/test/Transforms/LoopVectorize/early_exit_legality.ll
A llvm/test/Transforms/LoopVectorize/early_exit_store_legality.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-dead-instructions.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-scalable-vf1.ll
M llvm/test/Transforms/LoopVectorize/load-deref-pred-poison-ub-ops-feeding-pointer.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_scalable.ll
A llvm/test/Transforms/LoopVectorize/predicatedinst-loop-invariant.ll
M llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/scalable-inductions.ll
M llvm/test/Transforms/LoopVectorize/scalable-iv-outside-user.ll
M llvm/test/Transforms/LoopVectorize/scalable-lifetime.ll
M llvm/test/Transforms/LoopVectorize/scalable-loop-unpredicated-body-scalar-tail.ll
A llvm/test/Transforms/LoopVectorize/scalable-predication.ll
M llvm/test/Transforms/LoopVectorize/scalable-reduction-inloop.ll
M llvm/test/Transforms/LoopVectorize/scalable-trunc-min-bitwidth.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_and.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_div_urem.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_lshr.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction2.ll
M llvm/test/Transforms/LoopVectorize/vectorize-force-tail-with-evl.ll
M llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll
A llvm/test/Transforms/LowerMatrixIntrinsics/phi.ll
M llvm/test/Transforms/LowerMatrixIntrinsics/propagate-backwards-unsupported.ll
M llvm/test/Transforms/MemCpyOpt/memcpy-memcpy-offset.ll
M llvm/test/Transforms/MemCpyOpt/variable-sized-memcpy-memcpy.ll
M llvm/test/Transforms/MemCpyOpt/vscale-crashes.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/sve-interleave-vectorization.ll
A llvm/test/Transforms/PhaseOrdering/X86/fmaddsub.ll
M llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-exp.ll
A llvm/test/Transforms/WholeProgramDevirt/availableexternal-check.ll
A llvm/test/Verifier/NVPTX/fence-proxy.tensormap.ll
M llvm/test/Verifier/NVPTX/setmaxnreg.ll
A llvm/test/tools/llvm-mca/AArch64/Cortex/A320-basic-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Cortex/A320-neon-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Cortex/A320-sve-instructions.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/floating-point.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll
M llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test
A llvm/test/tools/llvm-remarkutil/Inputs/broken-remark-magic.bitstream
M llvm/test/tools/llvm-remarkutil/annotation-count.test
A llvm/test/tools/llvm-remarkutil/broken-bitstream-remark-magic.test
M llvm/test/tools/llvm-remarkutil/empty-file.test
M llvm/test/tools/llvm-remarkutil/instruction-count.test
M llvm/test/tools/llvm-remarkutil/instruction-mix.test
M llvm/test/tools/llvm-remarkutil/size-diff/no-difference.test
A llvm/test/tools/yaml2obj/basic.test
M llvm/tools/llvm-jitlink/llvm-jitlink-executor/CMakeLists.txt
M llvm/tools/llvm-readobj/ELFDumper.cpp
M llvm/tools/llvm-remarkutil/RemarkUtilHelpers.h
M llvm/tools/yaml2obj/yaml2obj.cpp
M llvm/unittests/ADT/TestGraph.h
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
M llvm/unittests/Remarks/RemarksLinkingTest.cpp
M llvm/unittests/Remarks/YAMLRemarksParsingTest.cpp
M llvm/unittests/Remarks/YAMLRemarksSerializerTest.cpp
M llvm/unittests/Support/Casting.cpp
M llvm/utils/TableGen/Basic/CMakeLists.txt
A llvm/utils/TableGen/Basic/TargetFeaturesEmitter.cpp
A llvm/utils/TableGen/Basic/TargetFeaturesEmitter.h
M llvm/utils/TableGen/CompressInstEmitter.cpp
M llvm/utils/TableGen/DecoderEmitter.cpp
M llvm/utils/TableGen/SubtargetEmitter.cpp
M llvm/utils/gn/secondary/bolt/unittests/Profile/BUILD.gn
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/cppcoreguidelines/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Driver/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Commands/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Core/BUILD.gn
M llvm/utils/gn/secondary/llvm/include/llvm/TargetParser/BUILD.gn
M llvm/utils/gn/secondary/llvm/utils/TableGen/Basic/BUILD.gn
A mlir/include/mlir/Analysis/DataFlow/Utils.h
M mlir/include/mlir/AsmParser/AsmParserState.h
M mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.h
M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
M mlir/include/mlir/Dialect/Arith/Transforms/Passes.h
M mlir/include/mlir/Dialect/Arith/Transforms/Passes.td
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationOps.td
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationTypeInterfaces.h
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationTypeInterfaces.td
M mlir/include/mlir/Dialect/Bufferization/IR/UnstructuredControlFlow.h
M mlir/include/mlir/Dialect/ControlFlow/IR/ControlFlowOps.td
M mlir/include/mlir/Dialect/EmitC/IR/CMakeLists.txt
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.h
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
A mlir/include/mlir/Dialect/EmitC/IR/EmitCInterfaces.h
A mlir/include/mlir/Dialect/EmitC/IR/EmitCInterfaces.td
R mlir/include/mlir/Dialect/EmitC/IR/EmitCTraits.h
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.td
M mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td
M mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
M mlir/include/mlir/Dialect/Linalg/Utils/Utils.h
M mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.h
M mlir/include/mlir/Dialect/Mesh/Transforms/Passes.h
M mlir/include/mlir/Dialect/Mesh/Transforms/Passes.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrDialect.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrOps.td
M mlir/include/mlir/Dialect/Tensor/Utils/Utils.h
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/Dialect/XeGPU/Transforms/Passes.td
M mlir/include/mlir/Dialect/XeGPU/Utils/XeGPUUtils.h
M mlir/include/mlir/ExecutionEngine/ExecutionEngine.h
M mlir/include/mlir/IR/BlockSupport.h
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/BuiltinOps.td
M mlir/include/mlir/IR/BuiltinTypeInterfaces.td
M mlir/include/mlir/IR/BuiltinTypes.h
M mlir/include/mlir/IR/BuiltinTypes.td
M mlir/include/mlir/IR/OpBase.td
M mlir/include/mlir/IR/Operation.h
M mlir/include/mlir/IR/PatternMatch.h
M mlir/include/mlir/IR/Region.h
M mlir/include/mlir/IR/SymbolTable.h
M mlir/include/mlir/IR/TypeRange.h
M mlir/include/mlir/IR/ValueRange.h
M mlir/include/mlir/Rewrite/FrozenRewritePatternSet.h
M mlir/include/mlir/Tools/PDLL/AST/Types.h
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/include/mlir/Transforms/Passes.h
M mlir/lib/Analysis/DataFlow/LivenessAnalysis.cpp
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/lib/Conversion/FuncToLLVM/FuncToLLVM.cpp
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
M mlir/lib/Conversion/GPUToSPIRV/GPUToSPIRV.cpp
M mlir/lib/Dialect/AMDGPU/Transforms/EmulateAtomics.cpp
M mlir/lib/Dialect/AMDGPU/Transforms/ResolveStridedMetadata.cpp
M mlir/lib/Dialect/AMDGPU/Transforms/TransferReadToLoad.cpp
M mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/lib/Dialect/Arith/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Arith/Transforms/ExpandOps.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationDialect.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
A mlir/lib/Dialect/Bufferization/IR/BufferizationTypeInterfaces.cpp
M mlir/lib/Dialect/Bufferization/IR/CMakeLists.txt
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
M mlir/lib/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/ControlFlow/IR/ControlFlowOps.cpp
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
M mlir/lib/Dialect/EmitC/Transforms/FormExpressions.cpp
M mlir/lib/Dialect/EmitC/Transforms/Transforms.cpp
M mlir/lib/Dialect/GPU/Transforms/DecomposeMemRefs.cpp
M mlir/lib/Dialect/LLVMIR/IR/TypeDetail.h
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt
M mlir/lib/Dialect/Linalg/Transforms/ConvertToDestinationStyle.cpp
A mlir/lib/Dialect/Linalg/Transforms/PadTilingInterface.cpp
M mlir/lib/Dialect/Linalg/Transforms/Padding.cpp
M mlir/lib/Dialect/Linalg/Utils/Utils.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandOps.cpp
M mlir/lib/Dialect/Mesh/IR/MeshOps.cpp
M mlir/lib/Dialect/Mesh/Transforms/ShardingPropagation.cpp
M mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp
M mlir/lib/Dialect/Ptr/IR/PtrTypes.cpp
M mlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Shape/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseGPUCodegen.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorCodegen.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparsificationAndBufferizationPass.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenUtils.cpp
M mlir/lib/Dialect/Tensor/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorUnroll.cpp
M mlir/lib/Dialect/XeGPU/Transforms/CMakeLists.txt
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
A mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
M mlir/lib/IR/BuiltinTypes.cpp
M mlir/lib/Pass/PassManagerOptions.cpp
M mlir/lib/Pass/PassStatistics.cpp
M mlir/lib/TableGen/Operator.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
M mlir/test/CMakeLists.txt
M mlir/test/Conversion/AMDGPUToROCDL/mfma-gfx950.mlir
M mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
M mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
M mlir/test/Conversion/GPUToSPIRV/shuffle.mlir
M mlir/test/Dialect/Affine/constant-fold.mlir
M mlir/test/Dialect/Arith/canonicalize.mlir
M mlir/test/Dialect/Arith/expand-ops.mlir
M mlir/test/Dialect/Arith/ops.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-bufferize.mlir
M mlir/test/Dialect/ControlFlow/canonicalize.mlir
M mlir/test/Dialect/Linalg/mesh-spmdization.mlir
A mlir/test/Dialect/Linalg/transform-op-pad-tiling-interface-multiple-of.mlir
A mlir/test/Dialect/Linalg/transform-op-pad-tiling-interface.mlir
M mlir/test/Dialect/Linalg/transform-op-pad.mlir
M mlir/test/Dialect/MemRef/expand-ops.mlir
A mlir/test/Dialect/Mesh/backward-sharding-propagation.mlir
A mlir/test/Dialect/Mesh/forward-backward-sharding-propagation.mlir
A mlir/test/Dialect/Mesh/forward-sharding-propagation.mlir
M mlir/test/Dialect/Mesh/spmdization.mlir
M mlir/test/Dialect/Ptr/canonicalize.mlir
A mlir/test/Dialect/Ptr/invalid.mlir
M mlir/test/Dialect/Ptr/ops.mlir
M mlir/test/Dialect/Tensor/mesh-spmdization.mlir
M mlir/test/Dialect/Tosa/constant_folding.mlir
M mlir/test/Dialect/Vector/canonicalize.mlir
M mlir/test/Dialect/Vector/constant-fold.mlir
M mlir/test/Dialect/Vector/invalid.mlir
M mlir/test/Dialect/Vector/ops.mlir
A mlir/test/Dialect/Vector/single-fold.mlir
M mlir/test/Dialect/Vector/vector-unroll-options.mlir
A mlir/test/Dialect/XeGPU/propagate-layout.mlir
A mlir/test/Dialect/XeGPU/subgroup-distribute.mlir
R mlir/test/Dialect/XeGPU/subgroup-distribution.mlir
R mlir/test/Dialect/XeGPU/subgroup-map-propagation.mlir
M mlir/test/Dialect/XeGPU/xegpu-blocking.mlir
A mlir/test/Integration/Dialect/Arith/CPU/test-arith-expand-truncf-extf.mlir
M mlir/test/Integration/Dialect/SparseTensor/CPU/dense_output_bf16.mlir
M mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sum_bf16.mlir
M mlir/test/Integration/GPU/CUDA/dump-ptx.mlir
M mlir/test/Target/LLVMIR/omptarget-llvm.mlir
M mlir/test/Target/LLVMIR/omptargetdata-nowait-llvm.mlir
M mlir/test/Target/LLVMIR/openmp-data-target-device.mlir
M mlir/test/Target/SPIRV/constant.mlir
M mlir/test/Transforms/constant-fold-debuginfo.mlir
M mlir/test/Transforms/constant-fold.mlir
M mlir/test/Transforms/remove-dead-values.mlir
M mlir/test/lib/Analysis/DataFlow/TestDenseBackwardDataFlowAnalysis.cpp
M mlir/test/lib/Analysis/DataFlow/TestDenseForwardDataFlowAnalysis.cpp
M mlir/test/lib/Analysis/DataFlow/TestSparseBackwardDataFlowAnalysis.cpp
M mlir/test/lib/Dialect/Test/TestOpDefs.cpp
M mlir/test/lib/Dialect/Test/TestOps.h
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/test/lib/Dialect/Test/TestTypeDefs.td
M mlir/test/lib/Dialect/Test/TestTypes.cpp
M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
M mlir/test/lib/Dialect/XeGPU/TestXeGPUTransforms.cpp
M mlir/test/lib/Transforms/CMakeLists.txt
R mlir/test/lib/Transforms/TestConstantFold.cpp
A mlir/test/lib/Transforms/TestSingleFold.cpp
M mlir/test/lit.cfg.py
R mlir/test/lit.local.cfg
M mlir/test/lit.site.cfg.py.in
A mlir/test/mlir-opt/local-reproducer-with-threading.mlir
M mlir/test/mlir-tblgen/op-format.mlir
M mlir/tools/mlir-opt/mlir-opt.cpp
M mlir/tools/mlir-tblgen/OpFormatGen.cpp
M mlir/unittests/IR/OperationSupportTest.cpp
M mlir/unittests/IR/ValueTest.cpp
M offload/liboffload/API/Common.td
M offload/liboffload/include/OffloadImpl.hpp
M offload/liboffload/src/OffloadImpl.cpp
M offload/liboffload/src/OffloadLib.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/tools/offload-tblgen/EntryPointGen.cpp
M offload/unittests/CMakeLists.txt
M offload/unittests/OffloadAPI/CMakeLists.txt
M offload/unittests/OffloadAPI/common/Environment.cpp
M offload/unittests/OffloadAPI/device_code/CMakeLists.txt
A offload/unittests/OffloadAPI/init/olInit.cpp
M runtimes/CMakeLists.txt
M utils/bazel/llvm-project-overlay/lld/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.5-bogner
[skip ci]
Commit: b19eb405a9ae68569fa507384982019e3ddf18dc
https://github.com/llvm/llvm-project/commit/b19eb405a9ae68569fa507384982019e3ddf18dc
Author: Fangrui Song <i at maskray.me>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M .ci/compute_projects.py
M .ci/compute_projects_test.py
M .ci/monolithic-linux.sh
M .github/workflows/libcxx-restart-preempted-jobs.yaml
M .github/workflows/premerge.yaml
M bolt/include/bolt/Passes/PAuthGadgetScanner.h
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/include/bolt/Utils/CommandLineOpts.h
M bolt/lib/Passes/PAuthGadgetScanner.cpp
M bolt/lib/Profile/BoltAddressTranslation.cpp
M bolt/lib/Profile/DataAggregator.cpp
M bolt/lib/Rewrite/LinuxKernelRewriter.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/test/AArch64/r_aarch64_prelxx.s
M bolt/test/X86/callcont-fallthru.s
M bolt/test/X86/linux-version.S
M bolt/test/X86/register-fragments-bolt-symbols.s
A bolt/test/binary-analysis/AArch64/gs-pauth-authentication-oracles.s
M bolt/test/binary-analysis/AArch64/gs-pauth-debug-output.s
M bolt/test/link_fdata.py
A bolt/test/perf2bolt/AArch64/perf2bolt-spe.test
A bolt/test/perf2bolt/X86/perf2bolt-spe.test
M bolt/tools/driver/llvm-bolt.cpp
M bolt/unittests/Profile/CMakeLists.txt
A bolt/unittests/Profile/PerfSpeEvents.cpp
M clang-tools-extra/clang-doc/BitcodeReader.cpp
M clang-tools-extra/clang-doc/BitcodeWriter.cpp
M clang-tools-extra/clang-doc/BitcodeWriter.h
M clang-tools-extra/clang-doc/HTMLGenerator.cpp
M clang-tools-extra/clang-doc/HTMLMustacheGenerator.cpp
M clang-tools-extra/clang-doc/JSONGenerator.cpp
M clang-tools-extra/clang-doc/MDGenerator.cpp
M clang-tools-extra/clang-doc/Mapper.cpp
M clang-tools-extra/clang-doc/Mapper.h
M clang-tools-extra/clang-doc/Representation.cpp
M clang-tools-extra/clang-doc/Representation.h
M clang-tools-extra/clang-doc/Serialize.cpp
M clang-tools-extra/clang-doc/Serialize.h
M clang-tools-extra/clang-doc/YAMLGenerator.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/CMakeLists.txt
M clang-tools-extra/clang-tidy/cppcoreguidelines/CppCoreGuidelinesTidyModule.cpp
A clang-tools-extra/clang-tidy/cppcoreguidelines/UseEnumClassCheck.cpp
A clang-tools-extra/clang-tidy/cppcoreguidelines/UseEnumClassCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines/use-enum-class.rst
M clang-tools-extra/docs/clang-tidy/checks/list.rst
A clang-tools-extra/test/clang-doc/json/class-requires.cpp
A clang-tools-extra/test/clang-doc/json/compound-constraints.cpp
A clang-tools-extra/test/clang-doc/json/concept.cpp
A clang-tools-extra/test/clang-doc/json/function-requires.cpp
A clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/use-enum-class.cpp
M clang-tools-extra/unittests/clang-doc/BitcodeTest.cpp
M clang/docs/CommandGuide/clang.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/Expr.h
M clang/include/clang/AST/OpenACCClause.h
M clang/include/clang/AST/OpenMPClause.h
M clang/include/clang/AST/StmtOpenACC.h
M clang/include/clang/AST/StmtOpenMP.h
M clang/include/clang/AST/Type.h
M clang/include/clang/AST/TypeProperties.td
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/BuiltinsPPC.def
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/OffloadArch.h
M clang/include/clang/Basic/PPCTypes.def
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/Interfaces/CIROpInterfaces.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/Sema/SemaHLSL.h
M clang/include/clang/Sema/SemaObjC.h
M clang/include/clang/Serialization/ASTReader.h
M clang/include/clang/Serialization/ASTRecordWriter.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
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M clang/include/clang/Tooling/DependencyScanning/DependencyScanningService.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTDiagnostic.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/ByteCodeEmitter.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Descriptor.cpp
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/Floating.h
M clang/lib/AST/ByteCode/Integral.h
M clang/lib/AST/ByteCode/IntegralAP.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
M clang/lib/AST/ByteCode/InterpState.h
M clang/lib/AST/ByteCode/Opcodes.td
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M clang/lib/AST/ByteCode/Program.h
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M clang/lib/AST/ExprCXX.cpp
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M clang/lib/AST/StmtOpenMP.cpp
M clang/lib/AST/StmtProfile.cpp
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M clang/lib/Basic/Targets/PPC.cpp
M clang/lib/Basic/Targets/Xtensa.h
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M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGCleanup.cpp
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M clang/lib/CodeGen/CGExprConstant.cpp
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M clang/lib/CodeGen/CGHLSLRuntime.cpp
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M clang/lib/CodeGen/CGObjCGNU.cpp
M clang/lib/CodeGen/CGObjCMac.cpp
M clang/lib/CodeGen/CGObjCRuntime.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
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A clang/lib/Driver/ToolChains/Managarm.cpp
A clang/lib/Driver/ToolChains/Managarm.h
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R clang/lib/Headers/cuda_wrappers/bits/c++config.h
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M clang/lib/Sema/SemaCast.cpp
M clang/lib/Sema/SemaConcept.cpp
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M clang/lib/Sema/SemaDeclAttr.cpp
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M clang/lib/Sema/SemaExprObjC.cpp
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A clang/test/AST/HLSL/vk.spec-constant.usage.hlsl
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A clang/test/CIR/CodeGen/bitfields.c
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A clang/test/CIR/Transforms/vector-splat.cir
A clang/test/CodeGen/PowerPC/builtins-ppc-dmf.c
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A clang/test/CodeGen/PowerPC/ppc-future-mma-builtin-err.c
M clang/test/CodeGen/builtin_vectorelements.c
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A clang/test/Driver/Inputs/basic_managarm_tree/usr/lib64/.keep
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M clang/test/Driver/hip-thinlto.hip
A clang/test/Driver/managarm.cpp
M clang/test/Driver/openmp-offload-gpu.c
M clang/test/Driver/ppc-crbits.cpp
M clang/test/Driver/ppc-isa-features.cpp
A clang/test/Driver/spirv-amd-toolchain.c
M clang/test/ExtractAPI/objc_instancetype.m
M clang/test/Misc/loop-opt-setup.c
M clang/test/Misc/target-invalid-cpu-note/amdgcn.c
M clang/test/Misc/target-invalid-cpu-note/nvptx.c
A clang/test/Modules/pr144230.cppm
M clang/test/PCH/ignored-pch.c
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A clang/test/Sema/ppc-dmf-types.c
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A clang/test/SemaHLSL/RootSignature-resource-ranges-err.hlsl
A clang/test/SemaHLSL/RootSignature-resource-ranges.hlsl
A clang/test/SemaHLSL/vk.spec-constant.error.hlsl
M clang/test/SemaObjCXX/arc-type-conversion.mm
M clang/test/SemaTemplate/concepts-out-of-line-def.cpp
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
M clang/tools/clang-scan-deps/Opts.td
M clang/unittests/Tooling/DependencyScanning/DependencyScannerTest.cpp
M clang/unittests/Tooling/DependencyScanning/DependencyScanningFilesystemTest.cpp
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M clang/utils/TableGen/ClangDiagnosticsEmitter.cpp
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M compiler-rt/lib/msan/msan_interceptors.cpp
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A compiler-rt/test/profile/Posix/gcov-file-change-line.cpp
M compiler-rt/test/profile/Posix/gcov-file-change.cpp
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A flang/lib/Lower/OpenMP/Atomic.cpp
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M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
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M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
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A flang/test/HLFIR/fir-local-alloca-block.fir
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M libcxx/test/std/containers/sequences/list/list.modifiers/insert_iter_iter_iter.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/insert_iter_rvalue.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/insert_iter_size_value.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/insert_iter_value.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/insert_range.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/pop_back.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/pop_front.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/prepend_range.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/push_back.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/push_back_rvalue.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/push_front.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/push_front_rvalue.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/merge.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/merge_comp.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/remove.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/remove_if.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/reverse.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/sort.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/sort_comp.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/splice_pos_list.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/splice_pos_list_iter.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/splice_pos_list_iter_iter.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/unique.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/unique_pred.pass.cpp
M libcxx/test/std/containers/sequences/list/list.special/swap.pass.cpp
M libcxx/test/std/containers/sequences/list/list.special/swap_noexcept.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/expected.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/list.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/optional.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/tuple.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/utility.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/variant.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
M libcxx/test/std/numerics/c.math/abs.pass.cpp
M libcxx/test/std/numerics/c.math/abs.verify.cpp
M libcxx/test/std/utilities/format/format.functions/escaped_output.unicode.pass.cpp
M libcxx/test/std/utilities/format/format.functions/fill.unicode.pass.cpp
M libcxx/test/support/min_allocator.h
M libcxx/utils/generate_feature_test_macro_components.py
M lld/ELF/Arch/AArch64.cpp
A lld/ELF/Arch/TargetImpl.h
M lld/ELF/Arch/X86_64.cpp
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/Options.td
M lld/ELF/Relocations.cpp
M lld/ELF/Target.h
M lld/ELF/Thunks.cpp
M lld/docs/ReleaseNotes.rst
M lld/docs/ld.lld.1
A lld/test/ELF/aarch64-branch-to-branch.s
M lld/test/ELF/aarch64-thunk-bti-multipass.s
A lld/test/ELF/x86-64-branch-to-branch.s
M lldb/cmake/modules/LLDBConfig.cmake
M lldb/examples/python/crashlog.py
M lldb/examples/python/crashlog_scripted_process.py
M lldb/examples/python/templates/scripted_process.py
M lldb/include/lldb/Core/Debugger.h
M lldb/include/lldb/Core/DemangledNameInfo.h
M lldb/include/lldb/Core/PluginManager.h
A lldb/include/lldb/Core/ProtocolServer.h
M lldb/include/lldb/Host/Socket.h
M lldb/include/lldb/Interpreter/CommandOptionArgumentTable.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/include/lldb/lldb-forward.h
M lldb/include/lldb/lldb-private-interfaces.h
M lldb/source/API/CMakeLists.txt
M lldb/source/Breakpoint/Breakpoint.cpp
M lldb/source/Commands/CMakeLists.txt
A lldb/source/Commands/CommandObjectProtocolServer.cpp
A lldb/source/Commands/CommandObjectProtocolServer.h
M lldb/source/Core/CMakeLists.txt
M lldb/source/Core/CoreProperties.td
M lldb/source/Core/Debugger.cpp
M lldb/source/Core/PluginManager.cpp
A lldb/source/Core/ProtocolServer.cpp
M lldb/source/Host/common/Socket.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Plugins/CMakeLists.txt
M lldb/source/Plugins/Process/AIX/CMakeLists.txt
A lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX.cpp
A lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX.h
M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
A lldb/source/Plugins/Protocol/CMakeLists.txt
A lldb/source/Plugins/Protocol/MCP/CMakeLists.txt
A lldb/source/Plugins/Protocol/MCP/MCPError.cpp
A lldb/source/Plugins/Protocol/MCP/MCPError.h
A lldb/source/Plugins/Protocol/MCP/Protocol.cpp
A lldb/source/Plugins/Protocol/MCP/Protocol.h
A lldb/source/Plugins/Protocol/MCP/ProtocolServerMCP.cpp
A lldb/source/Plugins/Protocol/MCP/ProtocolServerMCP.h
A lldb/source/Plugins/Protocol/MCP/Tool.cpp
A lldb/source/Plugins/Protocol/MCP/Tool.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.h
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/ValueObject/DILParser.cpp
M lldb/test/API/commands/frame/var-dil/basics/ArraySubscript/TestFrameVarDILArraySubscript.py
M lldb/test/API/commands/frame/var-dil/basics/ArraySubscript/main.cpp
M lldb/test/API/commands/register/register/aarch64_mte_ctrl_register/TestMTECtrlRegister.py
M lldb/test/API/python_api/watchpoint/watchlocation/TestTargetWatchAddress.py
A lldb/test/API/terminal/TestDisabledBreakpoints.py
M lldb/test/API/tools/lldb-dap/memory/TestDAP_memory.py
M lldb/test/API/tools/lldb-dap/server/TestDAP_server.py
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/Inputs/a.out.ips
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/altered_threadState.test
A lldb/test/Shell/ScriptInterpreter/Python/Crashlog/interactive_crashlog_arm64_register.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/json.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/no_threadState.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/skipped_status_interactive_crashlog.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/text.test
M lldb/test/Shell/SymbolFile/DWARF/x86/explicit-member-function-quals.cpp
M lldb/tools/lldb-dap/Handler/ReadMemoryRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
M lldb/tools/lldb-dap/Options.td
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
M lldb/tools/lldb-dap/src-ts/lldb-dap-server.ts
M lldb/tools/lldb-dap/tool/lldb-dap.cpp
M lldb/unittests/CMakeLists.txt
M lldb/unittests/Core/MangledTest.cpp
M lldb/unittests/DAP/ProtocolTypesTest.cpp
A lldb/unittests/Protocol/CMakeLists.txt
A lldb/unittests/Protocol/ProtocolMCPServerTest.cpp
A lldb/unittests/Protocol/ProtocolMCPTest.cpp
M lldb/unittests/SymbolFile/DWARF/DWARFASTParserClangTests.cpp
M lldb/unittests/TestingSupport/TestUtilities.h
M llvm/cmake/modules/HandleLLVMOptions.cmake
M llvm/cmake/modules/TableGen.cmake
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/CommandGuide/llvm-opt-report.rst
M llvm/docs/NVPTXUsage.rst
M llvm/docs/Remarks.rst
M llvm/docs/TableGen/ProgRef.rst
M llvm/include/llvm/ADT/PointerIntPair.h
M llvm/include/llvm/Analysis/HashRecognize.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/BinaryFormat/DXContainer.h
M llvm/include/llvm/BinaryFormat/DXContainerConstants.def
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV_nonstandard.def
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/FunctionLoweringInfo.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/include/llvm/DebugInfo/LogicalView/Core/LVElement.h
M llvm/include/llvm/DebugInfo/LogicalView/Core/LVScope.h
M llvm/include/llvm/DebugInfo/LogicalView/Core/LVSupport.h
M llvm/include/llvm/Frontend/HLSL/HLSLRootSignatureUtils.h
M llvm/include/llvm/IR/IRBuilder.h
M llvm/include/llvm/IR/IntrinsicInst.h
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/PatternMatch.h
M llvm/include/llvm/IR/RuntimeLibcalls.h
M llvm/include/llvm/MC/MCTargetOptions.h
M llvm/include/llvm/ProfileData/GCOV.h
M llvm/include/llvm/ProfileData/MemProfReader.h
M llvm/include/llvm/Remarks/RemarkFormat.h
M llvm/include/llvm/Remarks/RemarkLinker.h
M llvm/include/llvm/Remarks/RemarkParser.h
M llvm/include/llvm/Remarks/YAMLRemarkSerializer.h
M llvm/include/llvm/Support/CodeGen.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/include/llvm/Target/TargetOptions.h
M llvm/include/llvm/TargetParser/CMakeLists.txt
M llvm/include/llvm/TargetParser/PPCTargetParser.h
M llvm/include/llvm/TargetParser/TargetParser.h
M llvm/include/llvm/Transforms/IPO/Attributor.h
M llvm/include/llvm/Transforms/Scalar/JumpThreading.h
M llvm/include/llvm/Transforms/Utils/SCCPSolver.h
M llvm/lib/Analysis/HashRecognize.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
M llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
M llvm/lib/CodeGen/MachineBlockPlacement.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/ExecutionEngine/JITLink/COFFDirectiveParser.cpp
M llvm/lib/ExecutionEngine/Orc/UnwindInfoRegistrationPlugin.cpp
M llvm/lib/Frontend/HLSL/HLSLRootSignatureUtils.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/IRBuilder.cpp
M llvm/lib/IR/IntrinsicInst.cpp
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Linker/IRMover.cpp
M llvm/lib/Object/ELFObjectFile.cpp
M llvm/lib/Object/IRSymtab.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/ProfileData/GCOV.cpp
M llvm/lib/Remarks/BitstreamRemarkParser.cpp
M llvm/lib/Remarks/BitstreamRemarkParser.h
M llvm/lib/Remarks/RemarkFormat.cpp
M llvm/lib/Remarks/RemarkLinker.cpp
M llvm/lib/Remarks/RemarkParser.cpp
M llvm/lib/Remarks/RemarkSerializer.cpp
M llvm/lib/Remarks/RemarkStreamer.cpp
M llvm/lib/Remarks/YAMLRemarkParser.cpp
M llvm/lib/Remarks/YAMLRemarkParser.h
M llvm/lib/Remarks/YAMLRemarkSerializer.cpp
M llvm/lib/Support/BLAKE3/CMakeLists.txt
M llvm/lib/Target/AArch64/AArch64.td
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64Processors.td
A llvm/lib/Target/AArch64/AArch64SchedA320.td
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUUnifyMetadata.cpp
M llvm/lib/Target/AMDGPU/GCNProcessors.td
M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMAsmPrinter.h
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
M llvm/lib/Target/BPF/BPFPreserveStaticOffset.cpp
M llvm/lib/Target/BPF/BTFDebug.cpp
M llvm/lib/Target/DirectX/DXILDataScalarization.cpp
M llvm/lib/Target/DirectX/DXILRootSignature.cpp
M llvm/lib/Target/DirectX/DXILRootSignature.h
M llvm/lib/Target/NVPTX/NVPTX.td
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/PowerPC/PPC.td
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.h
M llvm/lib/Target/PowerPC/PPCInstrMMA.td
M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/RISCVCallingConv.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVInstrFormats.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/lib/Target/Sparc/Sparc.td
M llvm/lib/Target/Sparc/SparcInstrInfo.td
M llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
M llvm/lib/Target/VE/VEISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86AsmPrinter.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/TargetParser/PPCTargetParser.cpp
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/lib/Transforms/IPO/Attributor.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/IPO/ElimAvailExtern.cpp
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
M llvm/lib/Transforms/IPO/SCCP.cpp
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Instrumentation/GCOVProfiling.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
M llvm/lib/Transforms/Utils/PredicateInfo.cpp
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/test/Analysis/HashRecognize/cyclic-redundancy-check.ll
M llvm/test/Analysis/ValueTracking/phi-known-bits.ll
A llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmov-gpr32.ll
R llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmov.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-splat-scalable.ll
A llvm/test/CodeGen/AArch64/cpa-globalisel.ll
A llvm/test/CodeGen/AArch64/cpa-selectiondag.ll
M llvm/test/CodeGen/AArch64/min-jump-table.ll
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/stack-hazard.ll
A llvm/test/CodeGen/AArch64/sve-bf16-reductions.ll
A llvm/test/CodeGen/AArch64/sve-fixed-length-splat-segment.ll
A llvm/test/CodeGen/AArch64/sve2p1-vector-shuffles.ll
M llvm/test/CodeGen/AArch64/trampoline.ll
A llvm/test/CodeGen/AArch64/unsupported-cc-call.ll
A llvm/test/CodeGen/AArch64/unsupported-cc-func.ll
A llvm/test/CodeGen/AArch64/vector-ldst-offset.ll
M llvm/test/CodeGen/AArch64/zext-to-tbl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
M llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll
M llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
A llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-gfx12-fake16.mir
A llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-gfx12-true16.mir
A llvm/test/CodeGen/AMDGPU/gcn-reg-pressure-true16-integer-overflow.mir
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/insert-skips-gfx12.mir
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-ignorable-exec-use.mir
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-fake16.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
A llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
A llvm/test/CodeGen/BPF/BTF/map-def-nested.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-AllValidFlagCombinations.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-AllValidFlagCombinationsV1.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-Invalid-Flag.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-Invalid-RangeType.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-Invalid-RegisterSpace.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Error-is-not-function.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Error-is-not-value.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Error-no-root-element-list.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Error-root-element-not-mdnode.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Error.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Flags-Error.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Flags.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-MultipleEntryFunctions.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-NullFunction-Error.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Parameters-Invalid-ParameterIsNotString.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Parameters-Validation-Error.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Parameters.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootConstants-Invalid-Num32BitValues.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootConstants-Invalid-RegisterSpace.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootConstants-Invalid-ShaderRegister.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootConstants.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor-Invalid-Flags.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor-Invalid-RegisterKind.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor-Invalid-RegisterSpace.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor-Invalid-RegisterValue.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor_V1.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootElement-Error.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootFlags-VisibilityValidationError.ll
M llvm/test/CodeGen/DirectX/scalarize-alloca.ll
A llvm/test/CodeGen/DirectX/scalarize-dynamic-vector-index.ll
M llvm/test/CodeGen/NVPTX/sm-version.ll
M llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll
M llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
M llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
M llvm/test/CodeGen/PowerPC/aix-cc-byval-mir.ll
M llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-mir.ll
M llvm/test/CodeGen/PowerPC/aix-vec-arg-spills.ll
M llvm/test/CodeGen/PowerPC/aix-vector-vararg-caller.ll
M llvm/test/CodeGen/PowerPC/aix-vector-vararg-fixed-caller.ll
A llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg-mir.ll
M llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
A llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg-mir.ll
M llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll
M llvm/test/CodeGen/PowerPC/all-atomics.ll
M llvm/test/CodeGen/PowerPC/dmr-spill.ll
A llvm/test/CodeGen/PowerPC/dmrp-spill.ll
M llvm/test/CodeGen/PowerPC/f128-arith.ll
M llvm/test/CodeGen/PowerPC/loop-comment.ll
M llvm/test/CodeGen/RISCV/branch.ll
A llvm/test/CodeGen/RISCV/icmp-non-byte-sized.ll
M llvm/test/CodeGen/RISCV/interrupt-attr.ll
M llvm/test/CodeGen/RISCV/memcmp-optsize.ll
M llvm/test/CodeGen/RISCV/memcmp.ll
M llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmaccbf16.ll
M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
A llvm/test/CodeGen/RISCV/rvv/interrupt-attr-nocall.ll
M llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
M llvm/test/CodeGen/RISCV/rvv/vle_vid-vfcvt.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
M llvm/test/CodeGen/RISCV/shifts.ll
M llvm/test/CodeGen/RISCV/xqcibm-extract.ll
M llvm/test/CodeGen/SPARC/ctlz.ll
M llvm/test/CodeGen/SPARC/cttz.ll
M llvm/test/CodeGen/SPARC/inlineasm-v9.ll
M llvm/test/CodeGen/SPARC/inlineasm.ll
A llvm/test/CodeGen/SPIRV/linkage/link-attribute-vk.ll
A llvm/test/CodeGen/SystemZ/fake-use-size.ll
M llvm/test/CodeGen/Thumb2/mve-shuffle.ll
M llvm/test/CodeGen/Thumb2/mve-vld3.ll
M llvm/test/CodeGen/Thumb2/schedm7-hazard.ll
A llvm/test/CodeGen/X86/fold-masked-merge-demorgan.ll
M llvm/test/CodeGen/X86/kcfi-arity.ll
M llvm/test/CodeGen/X86/movmsk-cmp.ll
M llvm/test/CodeGen/X86/oddshuffles.ll
M llvm/test/CodeGen/X86/ptest.ll
M llvm/test/CodeGen/X86/remarks-section.ll
M llvm/test/CodeGen/X86/vector-fshl-256.ll
M llvm/test/CodeGen/X86/vector-fshr-256.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
M llvm/test/CodeGen/X86/vector-shift-shl-256.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll
M llvm/test/Instrumentation/AddressSanitizer/asan-masked-load-store.ll
M llvm/test/Instrumentation/AddressSanitizer/asan-vp-load-store.ll
M llvm/test/Instrumentation/AddressSanitizer/vector-load-store.ll
M llvm/test/Instrumentation/BoundsChecking/simple.ll
M llvm/test/Instrumentation/HWAddressSanitizer/vector-load-store.ll
M llvm/test/Instrumentation/MemorySanitizer/partial-poison.ll
M llvm/test/Instrumentation/MemorySanitizer/vector-load-store.ll
M llvm/test/Instrumentation/MemorySanitizer/vscale.ll
M llvm/test/Instrumentation/ThreadSanitizer/atomic-non-integer.ll
M llvm/test/MC/AArch64/coff-function-type-info.ll
A llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s
M llvm/test/MC/AMDGPU/gfx12_asm_smem.s
M llvm/test/MC/AMDGPU/gfx12_asm_sopk.s
M llvm/test/MC/AMDGPU/gfx12_asm_sopp.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s
A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sopp.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_smem.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopp.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp8.txt
M llvm/test/MC/RISCV/custom_reloc.s
M llvm/test/MC/RISCV/vendor-symbol.s
A llvm/test/MC/RISCV/xandesperf-fixups-diagnostics.s
A llvm/test/MC/RISCV/xandesperf-relocation.s
M llvm/test/MC/RISCV/xqciac-valid.s
M llvm/test/MC/Sparc/Relocations/relocation-specifier.s
M llvm/test/MC/Sparc/sparcv9-instructions.s
M llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
R llvm/test/Transforms/Attributor/AMDGPU/tag-invariant-loads.ll
M llvm/test/Transforms/Attributor/dereferenceable-1.ll
M llvm/test/Transforms/Attributor/value-simplify-local-remote.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-counting-elems.ll
M llvm/test/Transforms/InstCombine/X86/x86-vector-shifts.ll
M llvm/test/Transforms/InstCombine/and-or-icmps.ll
M llvm/test/Transforms/InstCombine/apint-shift.ll
A llvm/test/Transforms/InstCombine/bitcast-known-bits.ll
M llvm/test/Transforms/InstCombine/call-cast-target.ll
A llvm/test/Transforms/InstCombine/dead-alloc-elim.ll
A llvm/test/Transforms/InstCombine/fmul-tan-cos.ll
M llvm/test/Transforms/InstCombine/fp-ret-bitcast.ll
M llvm/test/Transforms/InstCombine/gep-vector.ll
M llvm/test/Transforms/InstCombine/gepofconstgepi8.ll
M llvm/test/Transforms/InstCombine/getelementptr.ll
M llvm/test/Transforms/InstCombine/icmp-gep.ll
M llvm/test/Transforms/InstCombine/malloc-free.ll
M llvm/test/Transforms/InstCombine/masked_intrinsics.ll
M llvm/test/Transforms/InstCombine/multiple-uses-load-bitcast-select.ll
M llvm/test/Transforms/InstCombine/objsize.ll
M llvm/test/Transforms/InstCombine/opaque-ptr.ll
M llvm/test/Transforms/InstCombine/scalable-vector-array.ll
M llvm/test/Transforms/InstCombine/scalable-vector-struct.ll
M llvm/test/Transforms/InstCombine/select-load.ll
M llvm/test/Transforms/InstCombine/shift-amount-reassociation.ll
M llvm/test/Transforms/InstCombine/sub-gep.ll
A llvm/test/Transforms/InstCombine/sub-sext-add.ll
M llvm/test/Transforms/InstCombine/vp-reverse.ll
M llvm/test/Transforms/InstCombine/vscale_gep.ll
M llvm/test/Transforms/LICM/call-hoisting.ll
M llvm/test/Transforms/LICM/funclet.ll
M llvm/test/Transforms/LoopVectorize/AArch64/clamped-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/divs-with-scalable-vfs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/eliminate-tail-predication.ll
M llvm/test/Transforms/LoopVectorize/AArch64/gather-do-not-vectorize-addressing.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll
M llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_prefer_scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
A llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-interleave.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
M llvm/test/Transforms/LoopVectorize/AArch64/pr60831-sve-inv-store-crash.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-avoid-scalarization.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-reduction-inloop-cond.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
M llvm/test/Transforms/LoopVectorize/AArch64/simple_early_exit.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-inloop-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-no-remaining-iterations.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-strict-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-extract-last-veclane.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-fneg.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inv-store.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-live-out-pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-multiexit.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-runtime-check-size-based-threshold.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-forced.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-optsize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-unroll.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-vscale-based-trip-counts.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-gep.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-too-many-deps.ll
M llvm/test/Transforms/LoopVectorize/AArch64/tail-folding-styles.ll
M llvm/test/Transforms/LoopVectorize/AArch64/uniform-args-call-variants.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vplan-printing.ll
M llvm/test/Transforms/LoopVectorize/AArch64/wider-VF-for-callinst.ll
A llvm/test/Transforms/LoopVectorize/ARM/mve-reductions-interleave.ll
M llvm/test/Transforms/LoopVectorize/RISCV/bf16.ll
M llvm/test/Transforms/LoopVectorize/RISCV/blend-any-of-reduction-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/defaults.ll
M llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
M llvm/test/Transforms/LoopVectorize/RISCV/f16.ll
M llvm/test/Transforms/LoopVectorize/RISCV/first-order-recurrence-scalable-vf1.ll
M llvm/test/Transforms/LoopVectorize/RISCV/fminimumnum.ll
M llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-masked-access.ll
M llvm/test/Transforms/LoopVectorize/RISCV/lmul.ll
M llvm/test/Transforms/LoopVectorize/RISCV/low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/RISCV/mask-index-type.ll
M llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll
M llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
M llvm/test/Transforms/LoopVectorize/RISCV/remark-reductions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse-output.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/RISCV/safe-dep-distance.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-basics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-tailfold.ll
M llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-bin-unary-ops-args.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cond-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-div.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-interleave.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-intermediate-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-iv32.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-known-no-overflow.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-masked-loadstore.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-ordered-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-safe-dep-distance.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-uniform-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/branch-weights.ll
M llvm/test/Transforms/LoopVectorize/dereferenceable-info-from-assumption-constant-size.ll
M llvm/test/Transforms/LoopVectorize/dereferenceable-info-from-assumption-variable-size.ll
M llvm/test/Transforms/LoopVectorize/early_exit_legality.ll
A llvm/test/Transforms/LoopVectorize/early_exit_store_legality.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-dead-instructions.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-scalable-vf1.ll
M llvm/test/Transforms/LoopVectorize/load-deref-pred-poison-ub-ops-feeding-pointer.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_scalable.ll
A llvm/test/Transforms/LoopVectorize/predicatedinst-loop-invariant.ll
M llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/scalable-inductions.ll
M llvm/test/Transforms/LoopVectorize/scalable-iv-outside-user.ll
M llvm/test/Transforms/LoopVectorize/scalable-lifetime.ll
M llvm/test/Transforms/LoopVectorize/scalable-loop-unpredicated-body-scalar-tail.ll
A llvm/test/Transforms/LoopVectorize/scalable-predication.ll
M llvm/test/Transforms/LoopVectorize/scalable-reduction-inloop.ll
M llvm/test/Transforms/LoopVectorize/scalable-trunc-min-bitwidth.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_and.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_div_urem.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_lshr.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction2.ll
M llvm/test/Transforms/LoopVectorize/vectorize-force-tail-with-evl.ll
M llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll
A llvm/test/Transforms/LowerMatrixIntrinsics/phi.ll
M llvm/test/Transforms/LowerMatrixIntrinsics/propagate-backwards-unsupported.ll
M llvm/test/Transforms/MemCpyOpt/memcpy-memcpy-offset.ll
M llvm/test/Transforms/MemCpyOpt/variable-sized-memcpy-memcpy.ll
M llvm/test/Transforms/MemCpyOpt/vscale-crashes.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/sve-interleave-vectorization.ll
A llvm/test/Transforms/PhaseOrdering/X86/fmaddsub.ll
M llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-exp.ll
A llvm/test/Transforms/WholeProgramDevirt/availableexternal-check.ll
A llvm/test/Verifier/NVPTX/fence-proxy.tensormap.ll
M llvm/test/Verifier/NVPTX/setmaxnreg.ll
A llvm/test/tools/llvm-mca/AArch64/Cortex/A320-basic-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Cortex/A320-neon-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Cortex/A320-sve-instructions.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/floating-point.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll
M llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test
A llvm/test/tools/llvm-remarkutil/Inputs/broken-remark-magic.bitstream
M llvm/test/tools/llvm-remarkutil/annotation-count.test
A llvm/test/tools/llvm-remarkutil/broken-bitstream-remark-magic.test
M llvm/test/tools/llvm-remarkutil/empty-file.test
M llvm/test/tools/llvm-remarkutil/instruction-count.test
M llvm/test/tools/llvm-remarkutil/instruction-mix.test
M llvm/test/tools/llvm-remarkutil/size-diff/no-difference.test
A llvm/test/tools/yaml2obj/basic.test
M llvm/tools/llvm-jitlink/llvm-jitlink-executor/CMakeLists.txt
M llvm/tools/llvm-readobj/ELFDumper.cpp
M llvm/tools/llvm-remarkutil/RemarkUtilHelpers.h
M llvm/tools/yaml2obj/yaml2obj.cpp
M llvm/unittests/ADT/TestGraph.h
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
M llvm/unittests/Remarks/RemarksLinkingTest.cpp
M llvm/unittests/Remarks/YAMLRemarksParsingTest.cpp
M llvm/unittests/Remarks/YAMLRemarksSerializerTest.cpp
M llvm/unittests/Support/Casting.cpp
M llvm/utils/TableGen/Basic/CMakeLists.txt
A llvm/utils/TableGen/Basic/TargetFeaturesEmitter.cpp
A llvm/utils/TableGen/Basic/TargetFeaturesEmitter.h
M llvm/utils/TableGen/CompressInstEmitter.cpp
M llvm/utils/TableGen/DecoderEmitter.cpp
M llvm/utils/TableGen/SubtargetEmitter.cpp
M llvm/utils/gn/secondary/bolt/unittests/Profile/BUILD.gn
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/cppcoreguidelines/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Driver/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Commands/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Core/BUILD.gn
M llvm/utils/gn/secondary/llvm/include/llvm/TargetParser/BUILD.gn
M llvm/utils/gn/secondary/llvm/utils/TableGen/Basic/BUILD.gn
A mlir/include/mlir/Analysis/DataFlow/Utils.h
M mlir/include/mlir/AsmParser/AsmParserState.h
M mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.h
M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
M mlir/include/mlir/Dialect/Arith/Transforms/Passes.h
M mlir/include/mlir/Dialect/Arith/Transforms/Passes.td
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationOps.td
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationTypeInterfaces.h
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationTypeInterfaces.td
M mlir/include/mlir/Dialect/Bufferization/IR/UnstructuredControlFlow.h
M mlir/include/mlir/Dialect/ControlFlow/IR/ControlFlowOps.td
M mlir/include/mlir/Dialect/EmitC/IR/CMakeLists.txt
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.h
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
A mlir/include/mlir/Dialect/EmitC/IR/EmitCInterfaces.h
A mlir/include/mlir/Dialect/EmitC/IR/EmitCInterfaces.td
R mlir/include/mlir/Dialect/EmitC/IR/EmitCTraits.h
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.td
M mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td
M mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
M mlir/include/mlir/Dialect/Linalg/Utils/Utils.h
M mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.h
M mlir/include/mlir/Dialect/Mesh/Transforms/Passes.h
M mlir/include/mlir/Dialect/Mesh/Transforms/Passes.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrDialect.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrOps.td
M mlir/include/mlir/Dialect/Tensor/Utils/Utils.h
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/Dialect/XeGPU/Transforms/Passes.td
M mlir/include/mlir/Dialect/XeGPU/Utils/XeGPUUtils.h
M mlir/include/mlir/ExecutionEngine/ExecutionEngine.h
M mlir/include/mlir/IR/BlockSupport.h
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/BuiltinOps.td
M mlir/include/mlir/IR/BuiltinTypeInterfaces.td
M mlir/include/mlir/IR/BuiltinTypes.h
M mlir/include/mlir/IR/BuiltinTypes.td
M mlir/include/mlir/IR/OpBase.td
M mlir/include/mlir/IR/Operation.h
M mlir/include/mlir/IR/PatternMatch.h
M mlir/include/mlir/IR/Region.h
M mlir/include/mlir/IR/SymbolTable.h
M mlir/include/mlir/IR/TypeRange.h
M mlir/include/mlir/IR/ValueRange.h
M mlir/include/mlir/Rewrite/FrozenRewritePatternSet.h
M mlir/include/mlir/Tools/PDLL/AST/Types.h
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/include/mlir/Transforms/Passes.h
M mlir/lib/Analysis/DataFlow/LivenessAnalysis.cpp
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/lib/Conversion/FuncToLLVM/FuncToLLVM.cpp
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
M mlir/lib/Conversion/GPUToSPIRV/GPUToSPIRV.cpp
M mlir/lib/Dialect/AMDGPU/Transforms/EmulateAtomics.cpp
M mlir/lib/Dialect/AMDGPU/Transforms/ResolveStridedMetadata.cpp
M mlir/lib/Dialect/AMDGPU/Transforms/TransferReadToLoad.cpp
M mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/lib/Dialect/Arith/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Arith/Transforms/ExpandOps.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationDialect.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
A mlir/lib/Dialect/Bufferization/IR/BufferizationTypeInterfaces.cpp
M mlir/lib/Dialect/Bufferization/IR/CMakeLists.txt
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
M mlir/lib/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/ControlFlow/IR/ControlFlowOps.cpp
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
M mlir/lib/Dialect/EmitC/Transforms/FormExpressions.cpp
M mlir/lib/Dialect/EmitC/Transforms/Transforms.cpp
M mlir/lib/Dialect/GPU/Transforms/DecomposeMemRefs.cpp
M mlir/lib/Dialect/LLVMIR/IR/TypeDetail.h
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt
M mlir/lib/Dialect/Linalg/Transforms/ConvertToDestinationStyle.cpp
A mlir/lib/Dialect/Linalg/Transforms/PadTilingInterface.cpp
M mlir/lib/Dialect/Linalg/Transforms/Padding.cpp
M mlir/lib/Dialect/Linalg/Utils/Utils.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandOps.cpp
M mlir/lib/Dialect/Mesh/IR/MeshOps.cpp
M mlir/lib/Dialect/Mesh/Transforms/ShardingPropagation.cpp
M mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp
M mlir/lib/Dialect/Ptr/IR/PtrTypes.cpp
M mlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Shape/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseGPUCodegen.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorCodegen.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparsificationAndBufferizationPass.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenUtils.cpp
M mlir/lib/Dialect/Tensor/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorUnroll.cpp
M mlir/lib/Dialect/XeGPU/Transforms/CMakeLists.txt
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
A mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
M mlir/lib/IR/BuiltinTypes.cpp
M mlir/lib/Pass/PassManagerOptions.cpp
M mlir/lib/Pass/PassStatistics.cpp
M mlir/lib/TableGen/Operator.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
M mlir/test/CMakeLists.txt
M mlir/test/Conversion/AMDGPUToROCDL/mfma-gfx950.mlir
M mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
M mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
M mlir/test/Conversion/GPUToSPIRV/shuffle.mlir
M mlir/test/Dialect/Affine/constant-fold.mlir
M mlir/test/Dialect/Arith/canonicalize.mlir
M mlir/test/Dialect/Arith/expand-ops.mlir
M mlir/test/Dialect/Arith/ops.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-bufferize.mlir
M mlir/test/Dialect/ControlFlow/canonicalize.mlir
M mlir/test/Dialect/Linalg/mesh-spmdization.mlir
A mlir/test/Dialect/Linalg/transform-op-pad-tiling-interface-multiple-of.mlir
A mlir/test/Dialect/Linalg/transform-op-pad-tiling-interface.mlir
M mlir/test/Dialect/Linalg/transform-op-pad.mlir
M mlir/test/Dialect/MemRef/expand-ops.mlir
A mlir/test/Dialect/Mesh/backward-sharding-propagation.mlir
A mlir/test/Dialect/Mesh/forward-backward-sharding-propagation.mlir
A mlir/test/Dialect/Mesh/forward-sharding-propagation.mlir
M mlir/test/Dialect/Mesh/spmdization.mlir
M mlir/test/Dialect/Ptr/canonicalize.mlir
A mlir/test/Dialect/Ptr/invalid.mlir
M mlir/test/Dialect/Ptr/ops.mlir
M mlir/test/Dialect/Tensor/mesh-spmdization.mlir
M mlir/test/Dialect/Tosa/constant_folding.mlir
M mlir/test/Dialect/Vector/canonicalize.mlir
M mlir/test/Dialect/Vector/constant-fold.mlir
M mlir/test/Dialect/Vector/invalid.mlir
M mlir/test/Dialect/Vector/ops.mlir
A mlir/test/Dialect/Vector/single-fold.mlir
M mlir/test/Dialect/Vector/vector-unroll-options.mlir
A mlir/test/Dialect/XeGPU/propagate-layout.mlir
A mlir/test/Dialect/XeGPU/subgroup-distribute.mlir
R mlir/test/Dialect/XeGPU/subgroup-distribution.mlir
R mlir/test/Dialect/XeGPU/subgroup-map-propagation.mlir
M mlir/test/Dialect/XeGPU/xegpu-blocking.mlir
A mlir/test/Integration/Dialect/Arith/CPU/test-arith-expand-truncf-extf.mlir
M mlir/test/Integration/Dialect/SparseTensor/CPU/dense_output_bf16.mlir
M mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sum_bf16.mlir
M mlir/test/Integration/GPU/CUDA/dump-ptx.mlir
M mlir/test/Target/LLVMIR/omptarget-llvm.mlir
M mlir/test/Target/LLVMIR/omptargetdata-nowait-llvm.mlir
M mlir/test/Target/LLVMIR/openmp-data-target-device.mlir
M mlir/test/Target/SPIRV/constant.mlir
M mlir/test/Transforms/constant-fold-debuginfo.mlir
M mlir/test/Transforms/constant-fold.mlir
M mlir/test/Transforms/remove-dead-values.mlir
M mlir/test/lib/Analysis/DataFlow/TestDenseBackwardDataFlowAnalysis.cpp
M mlir/test/lib/Analysis/DataFlow/TestDenseForwardDataFlowAnalysis.cpp
M mlir/test/lib/Analysis/DataFlow/TestSparseBackwardDataFlowAnalysis.cpp
M mlir/test/lib/Dialect/Test/TestOpDefs.cpp
M mlir/test/lib/Dialect/Test/TestOps.h
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/test/lib/Dialect/Test/TestTypeDefs.td
M mlir/test/lib/Dialect/Test/TestTypes.cpp
M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
M mlir/test/lib/Dialect/XeGPU/TestXeGPUTransforms.cpp
M mlir/test/lib/Transforms/CMakeLists.txt
R mlir/test/lib/Transforms/TestConstantFold.cpp
A mlir/test/lib/Transforms/TestSingleFold.cpp
M mlir/test/lit.cfg.py
R mlir/test/lit.local.cfg
M mlir/test/lit.site.cfg.py.in
A mlir/test/mlir-opt/local-reproducer-with-threading.mlir
M mlir/test/mlir-tblgen/op-format.mlir
M mlir/tools/mlir-opt/mlir-opt.cpp
M mlir/tools/mlir-tblgen/OpFormatGen.cpp
M mlir/unittests/IR/OperationSupportTest.cpp
M mlir/unittests/IR/ValueTest.cpp
M offload/liboffload/API/Common.td
M offload/liboffload/include/OffloadImpl.hpp
M offload/liboffload/src/OffloadImpl.cpp
M offload/liboffload/src/OffloadLib.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/tools/offload-tblgen/EntryPointGen.cpp
M offload/unittests/CMakeLists.txt
M offload/unittests/OffloadAPI/CMakeLists.txt
M offload/unittests/OffloadAPI/common/Environment.cpp
M offload/unittests/OffloadAPI/device_code/CMakeLists.txt
A offload/unittests/OffloadAPI/init/olInit.cpp
M runtimes/CMakeLists.txt
M utils/bazel/llvm-project-overlay/lld/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
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