[all-commits] [llvm/llvm-project] adc622: [mlir][xegpu] Refine layout assignment in XeGPU SI...
Aiden Grossman via All-commits
all-commits at lists.llvm.org
Fri Jun 20 15:07:38 PDT 2025
Branch: refs/heads/users/boomanaiden154/ci-test-all-projects-when-ci-scripts-change
Home: https://github.com/llvm/llvm-project
Commit: adc6228ea07eba401481e218c3e0536a4aa6b8ec
https://github.com/llvm/llvm-project/commit/adc6228ea07eba401481e218c3e0536a4aa6b8ec
Author: Charitha Saumya <136391709+charithaintc at users.noreply.github.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/Transforms/Passes.td
M mlir/include/mlir/Dialect/XeGPU/Utils/XeGPUUtils.h
M mlir/lib/Dialect/XeGPU/Transforms/CMakeLists.txt
A mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
A mlir/test/Dialect/XeGPU/propagate-layout.mlir
A mlir/test/Dialect/XeGPU/subgroup-distribute.mlir
R mlir/test/Dialect/XeGPU/subgroup-distribution.mlir
R mlir/test/Dialect/XeGPU/subgroup-map-propagation.mlir
Log Message:
-----------
[mlir][xegpu] Refine layout assignment in XeGPU SIMT distribution. (#142687)
Changes:
* Decouple layout propagation from subgroup distribution and move it to
an independent pass.
* Refine layout assignment to handle control-flow ops correctly (scf.for, scf.while).
* Refine test cases.
Commit: 04e2e581ac000934782398e05853338040bf7c46
https://github.com/llvm/llvm-project/commit/04e2e581ac000934782398e05853338040bf7c46
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmaccbf16.ll
Log Message:
-----------
[RISCV] Treat bf16->f32 as separate ExtKind in combineOp_VLToVWOp_VL. (#144653)
This allows us to better track the narrow type we need and to fix
miscompiles if f16->f32 and bf16->f32 extends are mixed.
Fixes #144651.
Commit: ab8b8c1e138ae705f251626b63ad2cf4d7937003
https://github.com/llvm/llvm-project/commit/ab8b8c1e138ae705f251626b63ad2cf4d7937003
Author: Sam Elliott <quic_aelliott at quicinc.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/cmake/modules/TableGen.cmake
M llvm/include/llvm/TargetParser/CMakeLists.txt
Log Message:
-----------
[TargetParser][cmake] Be Smarter about TableGen Deps (#144848)
This tries to be a bit smarter for the OLD behaviour of CMP0116, to glob
more relevant directories looking for possible dependencies.
The changes are:
- Remove some duplication of lines in the `tablegen` function.
- Put CURRENT_SOURCE_DIR into `tblgen_includes` (at the front)
- Glob all directories in `tblgen_includes`
- Give up on `local_tds` which was wrong when using tablegen to compile
a file in a different directory (as TargetParser does)
- Use `EXTRA_INCLUDES` in TargetParser `tablegen` calls.
This is still an under-approximation of what might be included, at least
comparing the RISCVTargetParserDef.inc.d (after building
`target_parser_gen`), and the list of deps in the ninja file when
explicitly setting CMP0116 to OLD.
Fixes #144639
Commit: 7f74a377d094c34eba1adde1f1edc382d01d2e5e
https://github.com/llvm/llvm-project/commit/7f74a377d094c34eba1adde1f1edc382d01d2e5e
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_and.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_div_urem.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_lshr.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction2.ll
Log Message:
-----------
[LV] Regenerate uniform_across_vf* check lines.
Re-generate check lines to reduce diff in upcoming changes.
Also filters out the code after scalar.ph:, which is dead.
Commit: bae48ac3c0e6f406038833199b185493a67ee08b
https://github.com/llvm/llvm-project/commit/bae48ac3c0e6f406038833199b185493a67ee08b
Author: Yijia Gu <yijiagu at google.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] add missing deps for XeGPUTransforms
Commit: ff6367b47071a7d80e773127e2a798c087e81ff5
https://github.com/llvm/llvm-project/commit/ff6367b47071a7d80e773127e2a798c087e81ff5
Author: Diego Caballero <dieg0ca6aller0 at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Vector/canonicalize.mlir
Log Message:
-----------
[[mlir][Vector] Add simple folders for `vector.from_element`/`vector.to_elements` (#144444)
This PR adds simple folders to remove no-op sequences of
`vector.from_elements` and `vector.to_elements`.
Commit: 521adc9fa270c1524f125f155327bf8f3743bb87
https://github.com/llvm/llvm-project/commit/521adc9fa270c1524f125f155327bf8f3743bb87
Author: Luke Lau <luke at igalia.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll
Log Message:
-----------
[VPlan] Use createScalarZExtOrTrunc when expanding expandVPWidenIntOrFpInduction
Split off from #144666
Commit: 3f42c6bddd2495710331c82ce117ee7d5a58856d
https://github.com/llvm/llvm-project/commit/3f42c6bddd2495710331c82ce117ee7d5a58856d
Author: Deric C. <cheung.deric at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/DirectX/DXILDataScalarization.cpp
A llvm/test/CodeGen/DirectX/scalarize-dynamic-vector-index.ll
Log Message:
-----------
[DirectX] Scalarize `extractelement` and `insertelement` with dynamic indices (#141676)
Fixes #141136
- Implement `visitExtractElementInst` and `visitInsertElementInst` in
`DXILDataScalarizerVisitor` to scalarize `extractelement` and
`insertelement` instructions whose index operand is not a `ConstantInt`
by converting the vector to an array and then loading from the array
- Rename the `replaceVectorWithArray` helper function to
`equivalentArrayTypeFromVector`, relocate the function toward the top of
the file, and remove the unused `Ctx` parameter
Commit: 925dbc798828d78e5300972dfdabb89955216229
https://github.com/llvm/llvm-project/commit/925dbc798828d78e5300972dfdabb89955216229
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M flang/lib/Lower/OpenMP/Atomic.h
Log Message:
-----------
[flang][OpenMP] Fix namespace nesting after PR144960
Newly introduced Atomic.cpp fails to compile on its own, but somehow
compiles fine in the build. Maybe it's because PCH, but it needs to be
fixed nevertheless.
Commit: f159774352c37a75829c04febb89f141175fc2bf
https://github.com/llvm/llvm-project/commit/f159774352c37a75829c04febb89f141175fc2bf
Author: Fabian Mora <fmora.dev at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/Ptr/IR/PtrDialect.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrOps.td
M mlir/include/mlir/IR/BuiltinTypeInterfaces.td
M mlir/include/mlir/IR/BuiltinTypes.h
M mlir/include/mlir/IR/BuiltinTypes.td
M mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp
M mlir/lib/Dialect/Ptr/IR/PtrTypes.cpp
M mlir/lib/IR/BuiltinTypes.cpp
M mlir/test/Dialect/Ptr/canonicalize.mlir
A mlir/test/Dialect/Ptr/invalid.mlir
M mlir/test/Dialect/Ptr/ops.mlir
Log Message:
-----------
[mlir][core|ptr] Add `PtrLikeTypeInterface` and casting ops to the `ptr` dialect (#137469)
This patch adds the `PtrLikeTypeInterface` type interface to identify
pointer-like types. This interface is defined as:
```
A ptr-like type represents an object storing a memory address. This object
is constituted by:
- A memory address called the base pointer. This pointer is treated as a
bag of bits without any assumed structure. The bit-width of the base
pointer must be a compile-time constant. However, the bit-width may remain
opaque or unavailable during transformations that do not depend on the
base pointer. Finally, it is considered indivisible in the sense that as
a `PtrLikeTypeInterface` value, it has no metadata.
- Optional metadata about the pointer. For example, the size of the memory
region associated with the pointer.
Furthermore, all ptr-like types have two properties:
- The memory space associated with the address held by the pointer.
- An optional element type. If the element type is not specified, the
pointer is considered opaque.
```
This patch adds this interface to `!ptr.ptr` and the `memref` type.
Furthermore, this patch adds necessary ops and type to handle casting
between `!ptr.ptr` and ptr-like types.
First, it defines the `!ptr.ptr_metadata` type. An opaque type to
represent the metadata of a ptr-like type. The rationale behind adding
this type, is that at high-level the metadata of a type like `memref`
cannot be specified, as its structure is tied to its lowering.
The `ptr.get_metadata` operation was added to extract the opaque pointer
metadata. The concrete structure of the metadata is only known when the
op is lowered.
Finally, this patch adds the `ptr.from_ptr` and `ptr.to_ptr` operations.
Allowing to cast back and forth between `!ptr.ptr` and ptr-like types.
```mlir
func.func @func(%mr: memref<f32, #ptr.generic_space>) -> memref<f32, #ptr.generic_space> {
%ptr = ptr.to_ptr %mr : memref<f32, #ptr.generic_space> -> !ptr.ptr<#ptr.generic_space>
%mda = ptr.get_metadata %mr : memref<f32, #ptr.generic_space>
%res = ptr.from_ptr %ptr metadata %mda : !ptr.ptr<#ptr.generic_space> -> memref<f32, #ptr.generic_space>
return %res : memref<f32, #ptr.generic_space>
}
```
It's future work to replace and remove the `bare-ptr-convention` through
the use of these ops.
---------
Co-authored-by: Mehdi Amini <joker.eph at gmail.com>
Commit: c103bbc836691d637c249ca19d38bdb0034437c6
https://github.com/llvm/llvm-project/commit/c103bbc836691d637c249ca19d38bdb0034437c6
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/tail-folding-styles.ll
M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cond-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-interleave.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-intermediate-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-iv32.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-known-no-overflow.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-masked-loadstore.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-ordered-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-uniform-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll
A llvm/test/Transforms/LoopVectorize/scalable-predication.ll
Log Message:
-----------
[LV] Consider whether vscale is a known power of two for iteration check (#144963)
Going mostly by the comment here - but it says "vscale is not
necessarily a power-of-2". Both in tree targets have vscale as a power
of two, and we have an existing TTI hook for that.
Commit: 8d2eea96b391c5346543eceae5c8d24efe4f4497
https://github.com/llvm/llvm-project/commit/8d2eea96b391c5346543eceae5c8d24efe4f4497
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/test/MC/AMDGPU/gfx12_asm_sopp.s
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopp.txt
Log Message:
-----------
[AMDGPU] gfx1250 SOPP MC tests. NFC. (#145082)
Commit: b5d5708128e99f69add50c322bfbed5f4905c23d
https://github.com/llvm/llvm-project/commit/b5d5708128e99f69add50c322bfbed5f4905c23d
Author: joaosaffran <126493771+joaosaffran at users.noreply.github.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/include/llvm/BinaryFormat/DXContainer.h
M llvm/include/llvm/BinaryFormat/DXContainerConstants.def
M llvm/lib/Target/DirectX/DXILRootSignature.cpp
M llvm/lib/Target/DirectX/DXILRootSignature.h
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-AllValidFlagCombinations.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-AllValidFlagCombinationsV1.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-Invalid-Flag.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-Invalid-RangeType.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-Invalid-RegisterSpace.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Parameters.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor-Invalid-Flags.ll
Log Message:
-----------
[HLSL] Add descriptor table metadata parsing (#142492)
Implements descriptor table parsing from root signature metadata. This
is required to support root signatures in hlsl.
Closes: #[126640](https://github.com/llvm/llvm-project/issues/126640)
---------
Co-authored-by: joaosaffran <joao.saffran at microsoft.com>
Commit: 958dc8602651261f8285b59d352a1c4b4da2e90c
https://github.com/llvm/llvm-project/commit/958dc8602651261f8285b59d352a1c4b4da2e90c
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
Log Message:
-----------
[AMDGPU] Don't insert wait instructions that are not supported by gfx1250 (#145084)
No tests yet, but it will allow further tests not to be
polluted with these waits.
Commit: 2a4207e7322c90176814b17870051f9692f9994f
https://github.com/llvm/llvm-project/commit/2a4207e7322c90176814b17870051f9692f9994f
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/DirectX/DXILDataScalarization.cpp
M llvm/test/CodeGen/DirectX/scalarize-alloca.ll
Log Message:
-----------
[DirectX] Don't limit visitGetElementPtrInst to global ptrs (#144959)
fixes #144608
- there is a getPointerOperandIndex function so we don't need to iterate
the operands trying to find the pointer. This resulted in a small
cleanup to visitStoreInst and visitLoadInst.
- The meat of this change was in visitGetElementPtrInst to account for
allocas and not bail when we don't find a global.
Commit: affcc5e728c86260590ae398c136d43ac6cfbfb0
https://github.com/llvm/llvm-project/commit/affcc5e728c86260590ae398c136d43ac6cfbfb0
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SOPInstructions.td
A llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s
A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sopp.txt
Log Message:
-----------
[AMDGPU] Add s_wait_xcnt gfx1250 instruction (#145086)
Commit: 227f759644bbc208045178c54633df241f27da7f
https://github.com/llvm/llvm-project/commit/227f759644bbc208045178c54633df241f27da7f
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M mlir/lib/Bindings/Python/IRCore.cpp
Log Message:
-----------
[mlir][python] expose operation.block (#145088)
Expose `operation-getBlock()` in python.
Commit: 6d8c6ef90c1a4d17d764c4479d5165251bf07c95
https://github.com/llvm/llvm-project/commit/6d8c6ef90c1a4d17d764c4479d5165251bf07c95
Author: Amir Ayupov <aaupov at fb.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M bolt/lib/Profile/BoltAddressTranslation.cpp
M bolt/lib/Profile/DataAggregator.cpp
Log Message:
-----------
[BOLT][NFC] Simplify doTrace in BAT mode (#143233)
`BoltAddressTranslation::getFallthroughsInTrace` iterates over address
translation map entries and therefore has direct access to both original
and translated offsets. Return the translated offsets in fall-throughs
list to avoid duplicate address translation inside `doTrace`.
Test Plan: NFC
Commit: 4959e8a1dadd96499d701bcf02cd9b25dba98c98
https://github.com/llvm/llvm-project/commit/4959e8a1dadd96499d701bcf02cd9b25dba98c98
Author: Amir Ayupov <aaupov at fb.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/test/X86/register-fragments-bolt-symbols.s
Log Message:
-----------
[BOLT][NFCI] Use heuristic for matching split global functions (#90429)
This change speeds up fragment matching for large BOLTed binaries where
all fragments of global parent functions are put under `bolt-pseudo.o`
file symbol:
- before: iterating over symbols under `bolt-pseudo.o` only to fail
to find a parent,
- after: bail out immediately and use a global parent by name.
Test Plan: NFC, updated register-fragments-bolt-symbols.s
Commit: d8924d4da78fc980b720b328897b1bd5efba348a
https://github.com/llvm/llvm-project/commit/d8924d4da78fc980b720b328897b1bd5efba348a
Author: nerix <nerixdev at outlook.de>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M lldb/source/API/CMakeLists.txt
Log Message:
-----------
[LLDB] Explicitly use python for version fixup (#144217)
On Windows, the post build command would open the script in the default
editor, since it doesn't know about shebangs. This effectively adds
`python3` in front of the command.
Amends https://github.com/llvm/llvm-project/pull/142871 /
https://github.com/llvm/llvm-project/pull/141116
Commit: 3a66e2065296b3e0b27f0a14431eba1d74e7f8c4
https://github.com/llvm/llvm-project/commit/3a66e2065296b3e0b27f0a14431eba1d74e7f8c4
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt
Log Message:
-----------
[AMDGPU] Add gfx1250 runlines to vop3 dpp tests. NFC. (#145089)
dpp8 disasm test does not work yet.
Commit: d078ce7c98a3f9371d01d526e20f671ca2231667
https://github.com/llvm/llvm-project/commit/d078ce7c98a3f9371d01d526e20f671ca2231667
Author: sribee8 <sriya.pratipati at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/mbstate_t.h
M libc/include/llvm-libc-types/mbstate_t.h
M libc/include/wchar.yaml
M libc/src/__support/wchar/CMakeLists.txt
A libc/src/__support/wchar/mbrtowc.cpp
A libc/src/__support/wchar/mbrtowc.h
M libc/src/__support/wchar/mbstate.h
M libc/src/wchar/CMakeLists.txt
A libc/src/wchar/mbrtowc.cpp
A libc/src/wchar/mbrtowc.h
M libc/test/src/wchar/CMakeLists.txt
A libc/test/src/wchar/mbrtowc_test.cpp
Log Message:
-----------
[libc] mbrtowc implementation (#144760)
implemented the internal and public mbrtowc as well as tests for the
public function.
---------
Co-authored-by: Sriya Pratipati <sriyap at google.com>
Commit: f8ffb4e7cd94b661c3edd323f3dd85dc77892c16
https://github.com/llvm/llvm-project/commit/f8ffb4e7cd94b661c3edd323f3dd85dc77892c16
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-dead-instructions.ll
Log Message:
-----------
[VPlan] Simplify ExtractLastElement(Broadcast(A)) -> A.
Remove trivial ExtractLastElement VPInstructions.
Commit: 3b9795b3d3b249a5a3052a44f2c1ad7268ed34c6
https://github.com/llvm/llvm-project/commit/3b9795b3d3b249a5a3052a44f2c1ad7268ed34c6
Author: Rodolfo Wottrich <rgwott at users.noreply.github.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
A llvm/test/CodeGen/AArch64/cpa-globalisel.ll
A llvm/test/CodeGen/AArch64/cpa-selectiondag.ll
Log Message:
-----------
[AArch64] Add CodeGen support for scalar FEAT_CPA (#105669)
CPA stands for Checked Pointer Arithmetic and is part of the 2023 MTE
architecture extensions for A-profile.
The new CPA instructions perform regular pointer arithmetic (such as
base register + offset) but check for overflow in the most significant
bits of the result, enhancing security by detecting address tampering.
In this patch we intend to capture the semantics of pointer arithmetic
when it is not folded into loads/stores, then generate the appropriate
scalar CPA instructions. In order to preserve pointer arithmetic
semantics through the backend, we use the PTRADD SelectionDAG node type.
Use backend option `-aarch64-use-featcpa-codegen=true` to enable CPA
CodeGen (for a target with CPA enabled).
The story of this PR is that initially it introduced the PTRADD
SelectionDAG node and the respective visitPTRADD() function, adapted
from the CHERI/Morello LLVM tree. The original authors are
@davidchisnall, @jrtc27, @arichardson.
After a while, @ritter-x2a took the part of the code that was
target-independent and merged it separately in #140017. This PR thus
remains as the AArch64-part only.
Mode details about the CPA extension can be found at:
-
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023
- https://developer.arm.com/documentation/ddi0602/2023-09/ (e.g ADDPT
instruction)
This PR follows #79569.
It does not address vector FEAT_CPA instructions.
Commit: 491b82a5ec1add78d2c93370580a2f1897b6a364
https://github.com/llvm/llvm-project/commit/491b82a5ec1add78d2c93370580a2f1897b6a364
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M lld/ELF/Arch/AArch64.cpp
A lld/ELF/Arch/TargetImpl.h
M lld/ELF/Arch/X86_64.cpp
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/Options.td
M lld/ELF/Relocations.cpp
M lld/ELF/Target.h
M lld/docs/ReleaseNotes.rst
M lld/docs/ld.lld.1
A lld/test/ELF/aarch64-branch-to-branch.s
A lld/test/ELF/x86-64-branch-to-branch.s
Log Message:
-----------
ELF: Add branch-to-branch optimization.
When code calls a function which then immediately tail calls another
function there is no need to go via the intermediate function. By
branching directly to the target function we reduce the program's working
set for a slight increase in runtime performance.
Normally it is relatively uncommon to have functions that just tail call
another function, but with LLVM control flow integrity we have jump tables
that replace the function itself as the canonical address. As a result,
when a function address is taken and called directly, for example after
a compiler optimization resolves the indirect call, or if code built
without control flow integrity calls the function, the call will go via
the jump table.
The impact of this optimization was measured using a large internal
Google benchmark. The results were as follows:
CFI enabled: +0.1% ± 0.05% queries per second
CFI disabled: +0.01% queries per second [not statistically significant]
The optimization is enabled by default at -O2 but may also be enabled
or disabled individually with --{,no-}branch-to-branch.
This optimization is implemented for AArch64 and X86_64 only.
lld's runtime performance (real execution time) after adding this
optimization was measured using firefox-x64 from lld-speed-test [1]
with ldflags "-O2 -S" on an Apple M2 Ultra. The results are as follows:
```
N Min Max Median Avg Stddev
x 512 1.2264546 1.3481076 1.2970261 1.2965788 0.018620888
+ 512 1.2561196 1.3839965 1.3214632 1.3209327 0.019443971
Difference at 95.0% confidence
0.0243538 +/- 0.00233202
1.87831% +/- 0.179859%
(Student's t, pooled s = 0.0190369)
```
[1] https://discourse.llvm.org/t/improving-the-reproducibility-of-linker-benchmarking/86057
Pull Request: https://github.com/llvm/llvm-project/pull/138366
Commit: 6110dead894bec37d6373eda4cba2d5dc426f824
https://github.com/llvm/llvm-project/commit/6110dead894bec37d6373eda4cba2d5dc426f824
Author: Michael Spencer <bigcheesegs at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningFilesystem.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningService.h
M clang/lib/Tooling/DependencyScanning/DependencyScanningFilesystem.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningService.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
M clang/tools/clang-scan-deps/Opts.td
M clang/unittests/Tooling/DependencyScanning/DependencyScannerTest.cpp
M clang/unittests/Tooling/DependencyScanning/DependencyScanningFilesystemTest.cpp
Log Message:
-----------
[clang][scan-deps] Add option to disable caching stat failures (#144000)
While the source code isn't supposed to change during a build, in some
environments it does. This adds an option that disables caching of stat
failures, meaning that source files can be added to the build during
scanning.
This adds a `-no-cache-negative-stats` option to clang-scan-deps to
enable this behavior. There are no tests for clang-scan-deps as there's
no reliable way to do so from it. A unit test has been added that
modifies the filesystem between scans to test it.
Commit: 58f48011b3229b568d3a23a6f4853128712d5f8b
https://github.com/llvm/llvm-project/commit/58f48011b3229b568d3a23a6f4853128712d5f8b
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M lldb/examples/python/templates/scripted_process.py
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/Inputs/a.out.ips
Log Message:
-----------
[lldb] Add support for x86_64h to scripted process (#145099)
This patch adds support to the haswell sub-architecture (x86_64h) to
scripted processes.
rdar://147208252
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: b6445ac0c54992993b154875d6afb04eeaa13910
https://github.com/llvm/llvm-project/commit/b6445ac0c54992993b154875d6afb04eeaa13910
Author: David Green <david.green at arm.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/include/llvm/Target/GlobalISel/Combine.td
Log Message:
-----------
[GlobalISel] Create a common register_vector_matchinfo (#144306)
Several combiner use MatchInfo that are just SmallVector<Register>. This
creates a common register_vector_matchinfo that they can all use.
Commit: 9c1ce31f546368d6296bc881e9f576ad25c20c73
https://github.com/llvm/llvm-project/commit/9c1ce31f546368d6296bc881e9f576ad25c20c73
Author: Nishant Patel <nishant.b.patel at intel.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorUnroll.cpp
M mlir/test/Dialect/Vector/vector-unroll-options.mlir
M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
Log Message:
-----------
[mlir][vector] Add unroll patterns for vector.load and vector.store (#143420)
This PR adds unroll patterns for vector.load and vector.store. This PR is follow up of #137558
Commit: 4c97a91dc085fba40e5a86c4da8feeffd15b1f8a
https://github.com/llvm/llvm-project/commit/4c97a91dc085fba40e5a86c4da8feeffd15b1f8a
Author: sribee8 <sriya.pratipati at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M libc/hdr/types/mbstate_t.h
Log Message:
-----------
[libc] Added closing quote (#145101)
Error message was missing a closing quote, added it.
Co-authored-by: Sriya Pratipati <sriyap at google.com>
Commit: 0c2191b3a79d91d1115b1dbc1a9bd39daed1d9c5
https://github.com/llvm/llvm-project/commit/0c2191b3a79d91d1115b1dbc1a9bd39daed1d9c5
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Log Message:
-----------
[AMDGPU] Omit image waits in function prologue on gfx1250 (#145097)
Commit: 5886f0a18342457f142871ef73f40fc27f936d9b
https://github.com/llvm/llvm-project/commit/5886f0a18342457f142871ef73f40fc27f936d9b
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vle_vid-vfcvt.ll
Log Message:
-----------
[RISCV] Allow larger offset when matching build_vector as vid sequence (#144756)
I happened to notice that when legalizing get.active.lane.mask with
large vectors we were materializing via constant pool instead of just
shifting by a constant.
We should probably be doing a full cost comparison for the different
lowering strategies as opposed to our current adhoc heuristics, but the
few cases this regresses seem pretty minor. (Given the reduction in vset
toggles, they might not be regressions at all.)
---------
Co-authored-by: Craig Topper <craig.topper at sifive.com>
Commit: f0d32575a1193741bc9ca90e5beced693cba28b0
https://github.com/llvm/llvm-project/commit/f0d32575a1193741bc9ca90e5beced693cba28b0
Author: Amir Ayupov <aaupov at fb.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
Log Message:
-----------
[BOLT][NFCI] Use FileSymbols for local symbol disambiguation (#89088)
Remove SymbolToFileName mapping from every local symbol to its
containing FILE symbol name, and reuse FileSymbols to disambiguate
local symbols instead.
Also removes the check for `ld-temp.o` file symbol which was added to
prevent LTO build mode from affecting the disambiguated name. This may
cause incompatibility when using the profile collected on a binary built
in a different mode than the input binary.
Addresses #90661.
Speeds up discover file objects by 5-10% for large binaries:
- binary with ~1.2M symbols: 12.6422s -> 12.0297s
- binary with ~4.5M symbols: 48.8851s -> 43.7315s
Commit: a91154343780dae022bb314aa76f0b0affc28b62
https://github.com/llvm/llvm-project/commit/a91154343780dae022bb314aa76f0b0affc28b62
Author: Uzair Nawaz <uzairnawaz at google.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/wchar.yaml
M libc/src/__support/wchar/CMakeLists.txt
A libc/src/__support/wchar/wcrtomb.cpp
A libc/src/__support/wchar/wcrtomb.h
M libc/src/wchar/CMakeLists.txt
A libc/src/wchar/wcrtomb.cpp
A libc/src/wchar/wcrtomb.h
M libc/test/src/wchar/CMakeLists.txt
A libc/test/src/wchar/wcrtomb_test.cpp
Log Message:
-----------
[libc] Implemented wcrtomb internal function and public libc function (#144596)
Implemented internal wcrtomb function using the CharacterConverter class
public libc function calls this internal function to perform the
conversion
Commit: e6ee2c7c7b36825331b39e221725780167457e6d
https://github.com/llvm/llvm-project/commit/e6ee2c7c7b36825331b39e221725780167457e6d
Author: Finn Plummer <finn.c.plum at gmail.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/SemaHLSL/RootSignature-resource-ranges-err.hlsl
A clang/test/SemaHLSL/RootSignature-resource-ranges.hlsl
M llvm/include/llvm/Frontend/HLSL/HLSLRootSignatureUtils.h
M llvm/lib/Frontend/HLSL/HLSLRootSignatureUtils.cpp
Log Message:
-----------
[HLSL][RootSignature] Implement validation of resource ranges for `RootDescriptors` (#140962)
As was established
[previously](https://github.com/llvm/llvm-project/pull/140957), we
created a structure to model a resource range and to detect an overlap
in a given set of these.
However, a resource range only overlaps with another resource range if
they have:
- equivalent ResourceClass (SRV, UAV, CBuffer, Sampler)
- equivalent resource name-space
- overlapping shader visibility
For instance, the following don't overlap even though they have the same
register range:
- `CBV(b0)` and `SRV(t0)` (different resource class)
- `CBV(b0, space = 0)` and `CBV(b0, space = 1)` (different space)
- `CBV(b0, visibility = Pixel)` and `CBV(b0, visibility = Domain)`
(non-overlapping visibility)
The first two clauses are naturally modelled by grouping all the
`RangeInfo`s that have the equivalent `ResourceClass` and `Space` values
together and check if there is any overlap on a `ResourceRange` for all
these `RangeInfo`s. However, `Visibility` is not quite as easily mapped
(`Visibility = All` would overlap with any other visibility). So we will
instead need to track a `ResourceRange` for each of the `Visibility`
types in a group. Then we can determine when inserting a range of the
same group if it would overlap with any overlapping visibilities.
The collection of `RangeInfo` for `RootDescriptor`s, sorting of the
`RangeInfo`s into the groups and finally the insertion of each point
into their respective `ResourceRange`s are implemented. Furthermore, we
integrate this into `SemaHLSL` to provide a diagnostic for each entry
function that uses the invalid root signature.
- Implements collection of `RangeInfo` for `RootDescriptors`
- Implements resource range validation in `SemaHLSL`
- Add diagnostic testing of error production in
`RootSignature-resource-ranges-err.hlsl`
- Add testing to ensure no errors are raised in valid root signatures
`RootSignature-resource-ranges.hlsl`
Part 2 of https://github.com/llvm/llvm-project/issues/129942
A final pr will be produced to integrate the analysis of
`DescriptorTable`, `StaticSampler` and `RootConstants` by defining how
to construct the `RangeInfo` from their elements respectively.
Commit: 94865edfa85a61dd4ad985d2fb86990a1bba357b
https://github.com/llvm/llvm-project/commit/94865edfa85a61dd4ad985d2fb86990a1bba357b
Author: Anshil Gandhi <95053726+gandhi56 at users.noreply.github.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
A llvm/test/Transforms/InstCombine/AMDGPU/ptr-replace-alloca.ll
Log Message:
-----------
[Reland][InstCombine] Iterative replacement in PtrReplacer (#144626)
This patch enhances the PtrReplacer as follows:
1. Users are now collected iteratively to be generous on the stack. In the case of PHIs with incoming values which have not yet been visited, they are pushed back into the stack for reconsideration.
2. Replace users of the pointer root in a reverse-postorder traversal, instead of a simpletraversal over the collected users. This reordering ensures that the uses of an instruction are replaced before replacing the instruction itself.
3. During the replacement of PHI, use the same incoming value if it does not have a replacement.
This patch specifically fixes the case when an incoming value of a PHI
is addrspacecasted.
This is a reland of https://github.com/llvm/llvm-project/pull/137215.
Commit: b7be8786af42d131974ec9cfc3ba79b264511b7b
https://github.com/llvm/llvm-project/commit/b7be8786af42d131974ec9cfc3ba79b264511b7b
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M .ci/compute_projects.py
M .ci/compute_projects_test.py
M .ci/monolithic-linux.sh
M .github/workflows/premerge.yaml
Log Message:
-----------
Reapply "[CI] Migrate to runtimes build" (#143612)
This reverts commit 6f62979a5a5bcf70d65f23e0991a274e6df5955b.
The reapplies commit 80ea5f46df3e365a0a2112889bb91732167b6214.
That commit was reverted because it was causing compiler-rt test
failures due to tysan not having its dependencies set up properly within
CMake. That situation has since been rectified in
3cef099ceddccefca8e11268624397cde9e04af6.
Reviewers: lnihlen, rnk, gburgessiv, cmtice
Reviewed By: rnk, cmtice
Pull Request: https://github.com/llvm/llvm-project/pull/144033
Commit: 5a0a07c4ad77a3d12e69c6006a5b40de5ca5de7e
https://github.com/llvm/llvm-project/commit/5a0a07c4ad77a3d12e69c6006a5b40de5ca5de7e
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M bolt/lib/Profile/BoltAddressTranslation.cpp
M bolt/lib/Profile/DataAggregator.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/test/X86/register-fragments-bolt-symbols.s
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/SemaHLSL.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningFilesystem.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningService.h
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningFilesystem.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningService.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
A clang/test/SemaHLSL/RootSignature-resource-ranges-err.hlsl
A clang/test/SemaHLSL/RootSignature-resource-ranges.hlsl
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
M clang/tools/clang-scan-deps/Opts.td
M clang/unittests/Tooling/DependencyScanning/DependencyScannerTest.cpp
M clang/unittests/Tooling/DependencyScanning/DependencyScanningFilesystemTest.cpp
M flang/lib/Lower/OpenMP/Atomic.h
M libc/config/linux/x86_64/entrypoints.txt
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/mbstate_t.h
M libc/include/llvm-libc-types/mbstate_t.h
M libc/include/wchar.yaml
M libc/src/__support/wchar/CMakeLists.txt
A libc/src/__support/wchar/mbrtowc.cpp
A libc/src/__support/wchar/mbrtowc.h
M libc/src/__support/wchar/mbstate.h
A libc/src/__support/wchar/wcrtomb.cpp
A libc/src/__support/wchar/wcrtomb.h
M libc/src/wchar/CMakeLists.txt
A libc/src/wchar/mbrtowc.cpp
A libc/src/wchar/mbrtowc.h
A libc/src/wchar/wcrtomb.cpp
A libc/src/wchar/wcrtomb.h
M libc/test/src/wchar/CMakeLists.txt
A libc/test/src/wchar/mbrtowc_test.cpp
A libc/test/src/wchar/wcrtomb_test.cpp
M lld/ELF/Arch/AArch64.cpp
A lld/ELF/Arch/TargetImpl.h
M lld/ELF/Arch/X86_64.cpp
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/Options.td
M lld/ELF/Relocations.cpp
M lld/ELF/Target.h
M lld/docs/ReleaseNotes.rst
M lld/docs/ld.lld.1
A lld/test/ELF/aarch64-branch-to-branch.s
A lld/test/ELF/x86-64-branch-to-branch.s
M lldb/examples/python/templates/scripted_process.py
M lldb/source/API/CMakeLists.txt
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/Inputs/a.out.ips
M llvm/cmake/modules/TableGen.cmake
M llvm/include/llvm/BinaryFormat/DXContainer.h
M llvm/include/llvm/BinaryFormat/DXContainerConstants.def
M llvm/include/llvm/Frontend/HLSL/HLSLRootSignatureUtils.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/include/llvm/TargetParser/CMakeLists.txt
M llvm/lib/Frontend/HLSL/HLSLRootSignatureUtils.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/DirectX/DXILDataScalarization.cpp
M llvm/lib/Target/DirectX/DXILRootSignature.cpp
M llvm/lib/Target/DirectX/DXILRootSignature.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
A llvm/test/CodeGen/AArch64/cpa-globalisel.ll
A llvm/test/CodeGen/AArch64/cpa-selectiondag.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-AllValidFlagCombinations.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-AllValidFlagCombinationsV1.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-Invalid-Flag.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-Invalid-RangeType.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-Invalid-RegisterSpace.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Parameters.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor-Invalid-Flags.ll
M llvm/test/CodeGen/DirectX/scalarize-alloca.ll
A llvm/test/CodeGen/DirectX/scalarize-dynamic-vector-index.ll
M llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmaccbf16.ll
M llvm/test/CodeGen/RISCV/rvv/vle_vid-vfcvt.ll
A llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s
M llvm/test/MC/AMDGPU/gfx12_asm_sopp.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sopp.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopp.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt
A llvm/test/Transforms/InstCombine/AMDGPU/ptr-replace-alloca.ll
M llvm/test/Transforms/LoopVectorize/AArch64/tail-folding-styles.ll
M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cond-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-interleave.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-intermediate-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-iv32.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-known-no-overflow.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-masked-loadstore.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-ordered-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-uniform-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-dead-instructions.ll
A llvm/test/Transforms/LoopVectorize/scalable-predication.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_and.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_div_urem.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_lshr.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction2.ll
M llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll
M mlir/include/mlir/Dialect/Ptr/IR/PtrDialect.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrOps.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/Dialect/XeGPU/Transforms/Passes.td
M mlir/include/mlir/Dialect/XeGPU/Utils/XeGPUUtils.h
M mlir/include/mlir/IR/BuiltinTypeInterfaces.td
M mlir/include/mlir/IR/BuiltinTypes.h
M mlir/include/mlir/IR/BuiltinTypes.td
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp
M mlir/lib/Dialect/Ptr/IR/PtrTypes.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorUnroll.cpp
M mlir/lib/Dialect/XeGPU/Transforms/CMakeLists.txt
A mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
M mlir/lib/IR/BuiltinTypes.cpp
M mlir/test/Dialect/Ptr/canonicalize.mlir
A mlir/test/Dialect/Ptr/invalid.mlir
M mlir/test/Dialect/Ptr/ops.mlir
M mlir/test/Dialect/Vector/canonicalize.mlir
M mlir/test/Dialect/Vector/vector-unroll-options.mlir
A mlir/test/Dialect/XeGPU/propagate-layout.mlir
A mlir/test/Dialect/XeGPU/subgroup-distribute.mlir
R mlir/test/Dialect/XeGPU/subgroup-distribution.mlir
R mlir/test/Dialect/XeGPU/subgroup-map-propagation.mlir
M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6
[skip ci]
Commit: bdbd603d31357f5c3953d6a28d78767299fc654c
https://github.com/llvm/llvm-project/commit/bdbd603d31357f5c3953d6a28d78767299fc654c
Author: Aiden Grossman <agrossman154 at yahoo.com>
Date: 2025-06-20 (Fri, 20 Jun 2025)
Changed paths:
M bolt/lib/Profile/BoltAddressTranslation.cpp
M bolt/lib/Profile/DataAggregator.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/test/X86/register-fragments-bolt-symbols.s
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/SemaHLSL.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningFilesystem.h
M clang/include/clang/Tooling/DependencyScanning/DependencyScanningService.h
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningFilesystem.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningService.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
A clang/test/SemaHLSL/RootSignature-resource-ranges-err.hlsl
A clang/test/SemaHLSL/RootSignature-resource-ranges.hlsl
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
M clang/tools/clang-scan-deps/Opts.td
M clang/unittests/Tooling/DependencyScanning/DependencyScannerTest.cpp
M clang/unittests/Tooling/DependencyScanning/DependencyScanningFilesystemTest.cpp
M flang/lib/Lower/OpenMP/Atomic.h
M libc/config/linux/x86_64/entrypoints.txt
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/mbstate_t.h
M libc/include/llvm-libc-types/mbstate_t.h
M libc/include/wchar.yaml
M libc/src/__support/wchar/CMakeLists.txt
A libc/src/__support/wchar/mbrtowc.cpp
A libc/src/__support/wchar/mbrtowc.h
M libc/src/__support/wchar/mbstate.h
A libc/src/__support/wchar/wcrtomb.cpp
A libc/src/__support/wchar/wcrtomb.h
M libc/src/wchar/CMakeLists.txt
A libc/src/wchar/mbrtowc.cpp
A libc/src/wchar/mbrtowc.h
A libc/src/wchar/wcrtomb.cpp
A libc/src/wchar/wcrtomb.h
M libc/test/src/wchar/CMakeLists.txt
A libc/test/src/wchar/mbrtowc_test.cpp
A libc/test/src/wchar/wcrtomb_test.cpp
M lld/ELF/Arch/AArch64.cpp
A lld/ELF/Arch/TargetImpl.h
M lld/ELF/Arch/X86_64.cpp
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/Options.td
M lld/ELF/Relocations.cpp
M lld/ELF/Target.h
M lld/docs/ReleaseNotes.rst
M lld/docs/ld.lld.1
A lld/test/ELF/aarch64-branch-to-branch.s
A lld/test/ELF/x86-64-branch-to-branch.s
M lldb/examples/python/templates/scripted_process.py
M lldb/source/API/CMakeLists.txt
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/Inputs/a.out.ips
M llvm/cmake/modules/TableGen.cmake
M llvm/include/llvm/BinaryFormat/DXContainer.h
M llvm/include/llvm/BinaryFormat/DXContainerConstants.def
M llvm/include/llvm/Frontend/HLSL/HLSLRootSignatureUtils.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/include/llvm/TargetParser/CMakeLists.txt
M llvm/lib/Frontend/HLSL/HLSLRootSignatureUtils.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/DirectX/DXILDataScalarization.cpp
M llvm/lib/Target/DirectX/DXILRootSignature.cpp
M llvm/lib/Target/DirectX/DXILRootSignature.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
A llvm/test/CodeGen/AArch64/cpa-globalisel.ll
A llvm/test/CodeGen/AArch64/cpa-selectiondag.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-AllValidFlagCombinations.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-AllValidFlagCombinationsV1.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-Invalid-Flag.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-Invalid-RangeType.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable-Invalid-RegisterSpace.ll
A llvm/test/CodeGen/DirectX/ContainerData/RootSignature-DescriptorTable.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-Parameters.ll
M llvm/test/CodeGen/DirectX/ContainerData/RootSignature-RootDescriptor-Invalid-Flags.ll
M llvm/test/CodeGen/DirectX/scalarize-alloca.ll
A llvm/test/CodeGen/DirectX/scalarize-dynamic-vector-index.ll
M llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmaccbf16.ll
M llvm/test/CodeGen/RISCV/rvv/vle_vid-vfcvt.ll
A llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s
M llvm/test/MC/AMDGPU/gfx12_asm_sopp.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
A llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sopp.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopp.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt
A llvm/test/Transforms/InstCombine/AMDGPU/ptr-replace-alloca.ll
M llvm/test/Transforms/LoopVectorize/AArch64/tail-folding-styles.ll
M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cond-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-interleave.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-intermediate-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-iv32.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-known-no-overflow.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-masked-loadstore.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-ordered-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-uniform-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-dead-instructions.ll
A llvm/test/Transforms/LoopVectorize/scalable-predication.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_and.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_div_urem.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_lshr.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction2.ll
M llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll
M mlir/include/mlir/Dialect/Ptr/IR/PtrDialect.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrOps.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/Dialect/XeGPU/Transforms/Passes.td
M mlir/include/mlir/Dialect/XeGPU/Utils/XeGPUUtils.h
M mlir/include/mlir/IR/BuiltinTypeInterfaces.td
M mlir/include/mlir/IR/BuiltinTypes.h
M mlir/include/mlir/IR/BuiltinTypes.td
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp
M mlir/lib/Dialect/Ptr/IR/PtrTypes.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorUnroll.cpp
M mlir/lib/Dialect/XeGPU/Transforms/CMakeLists.txt
A mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
M mlir/lib/IR/BuiltinTypes.cpp
M mlir/test/Dialect/Ptr/canonicalize.mlir
A mlir/test/Dialect/Ptr/invalid.mlir
M mlir/test/Dialect/Ptr/ops.mlir
M mlir/test/Dialect/Vector/canonicalize.mlir
M mlir/test/Dialect/Vector/vector-unroll-options.mlir
A mlir/test/Dialect/XeGPU/propagate-layout.mlir
A mlir/test/Dialect/XeGPU/subgroup-distribute.mlir
R mlir/test/Dialect/XeGPU/subgroup-distribution.mlir
R mlir/test/Dialect/XeGPU/subgroup-map-propagation.mlir
M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
rebase
Created using spr 1.3.6
Compare: https://github.com/llvm/llvm-project/compare/0d7cc25ece77...bdbd603d3135
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