[all-commits] [llvm/llvm-project] 225768: [X86] combineConcatVectorOps - add tests showing v...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 225768d1f9f2e2ccff7dc79b4a4aaeab4c6aafc1
      https://github.com/llvm/llvm-project/commit/225768d1f9f2e2ccff7dc79b4a4aaeab4c6aafc1
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2025-06-20 (Fri, 20 Jun 2025)

  Changed paths:
    M llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
    M llvm/test/CodeGen/X86/vector-shift-shl-256.ll

  Log Message:
  -----------
  [X86] combineConcatVectorOps - add tests showing v4i64 shift-by-32 with unnecessary concatenation

On AVX1-only targets, we concat SHL/SRL AVX1 v4i64 by 32-bits as a shuffle. But this is only worth while if the shift source value is free to concatenate.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications