[all-commits] [llvm/llvm-project] d18fe4: [RISCV] Implement Feature Bits for Q

[Iris Shi via All-commits]

  Branch: refs/heads/users/el-ev/riscv-q-feature-bit
  Home:   https://github.com/llvm/llvm-project
  Commit: d18fe40a4c982031e3e501165f7be346567016b6
      https://github.com/llvm/llvm-project/commit/d18fe40a4c982031e3e501165f7be346567016b6
  Author: Iris Shi <0.0 at owo.li>
  Date:   2025-06-20 (Fri, 20 Jun 2025)

  Changed paths:
    M compiler-rt/lib/builtins/cpu_model/riscv.c

  Log Message:
  -----------
  [RISCV] Implement Feature Bits for Q



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