[all-commits] [llvm/llvm-project] 8063bd: [MLIR][XeGPU] Add support for elementwise ops in W...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Thu Jun 19 14:22:26 PDT 2025
Branch: refs/heads/users/alexey-bataev/spr/slpinitial-support-for-copyable-elements-non-schedulable-only
Home: https://github.com/llvm/llvm-project
Commit: 8063bd153c6aca43869d96aee64aeceb9be98ca5
https://github.com/llvm/llvm-project/commit/8063bd153c6aca43869d96aee64aeceb9be98ca5
Author: Nishant Patel <nishant.b.patel at intel.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
A mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-elemwise.mlir
Log Message:
-----------
[MLIR][XeGPU] Add support for elementwise ops in Wg to Sg distribute pass [1/N] (#142797)
This PR adds support for Elementwise operations' (unary & binary)
lowering from Workgroup to Subgroup.
Commit: 01a7a21a4b8070a88e5dcc9753066e38d26faf85
https://github.com/llvm/llvm-project/commit/01a7a21a4b8070a88e5dcc9753066e38d26faf85
Author: Chris B <chris.bieneman at me.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/cmake/modules/AddLLVM.cmake
Log Message:
-----------
[CMake] Add BINARY_DIR argument for add_lit_testsuites (#144431)
We're doing some slightly odd things with LIT in the offload-test-suite.
Specifically we generate multiple binary directories to configure and
run tests with different configurations from the same source root.
In this configuration the subdirectory targets need to instead point to
the correct generated binary directory and use test filtering to get a
subset of tests.
Commit: 526310e916af2073e30b57b678307ce94df803f3
https://github.com/llvm/llvm-project/commit/526310e916af2073e30b57b678307ce94df803f3
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/IR/DiagnosticInfo.cpp
M llvm/test/Transforms/GVN/opt-remarks.ll
Log Message:
-----------
[Remarks] Elaborate on called intrinsics (#143985)
Commit: ec230aa7a7d13c222c0b34b87c3c16937383b4a0
https://github.com/llvm/llvm-project/commit/ec230aa7a7d13c222c0b34b87c3c16937383b4a0
Author: Garvit Gupta <quic_garvgupt at quicinc.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/lib/Driver/ToolChains/BareMetal.cpp
M clang/lib/Driver/ToolChains/BareMetal.h
M clang/test/Driver/aarch64-toolchain-extra.c
M clang/test/Driver/aarch64-toolchain.c
M clang/test/Driver/arm-toolchain-extra.c
M clang/test/Driver/arm-toolchain.c
M clang/test/Driver/baremetal.cpp
M clang/test/Driver/sanitizer-ld.c
Log Message:
-----------
[Driver] Add support for crtbegin.o, crtend.o and libgloss lib to BareMetal toolchain object (#121830)
This patch conditionalise the addition of crt{begin,end}.o object files
along
with addition of -lgloss lib based on whether libc selected is newlib or
llvm
libc. Since there is no way a user can specify which libc it wants to
link
against, currently passing valid GCCInstallation to driver will select
newlib
otherwise it will default to llvm libc.
Moreover, this patch makes gnuld the default linker for baremetal
toolchain
object. User need to pass `-fuse-ld=lld` explicitly to driver to select
lld
This is the 2nd patch in the series of patches of merging RISCVToolchain
into
BareMetal toolchain object.
RFC:
https://discourse.llvm.org/t/merging-riscvtoolchain-and-baremetal-toolchains/75524
Commit: 8513066f2c49457f5d1f63e275403330f854041c
https://github.com/llvm/llvm-project/commit/8513066f2c49457f5d1f63e275403330f854041c
Author: someoneinjd <someoneinjd at outlook.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang-tools-extra/clangd/ClangdLSPServer.cpp
M clang-tools-extra/clangd/Protocol.cpp
M clang-tools-extra/clangd/Protocol.h
A clang-tools-extra/clangd/test/positionencoding.test
Log Message:
-----------
[clangd] Implement LSP 3.17 positionEncoding (#142903)
This PR adds support for the `positionEncoding` client capability
introduced in LSP 3.17. Clangd can now negotiate the position encoding
with the client during initialization.
Fix https://github.com/clangd/clangd/issues/1746
Co-authored-by: kadir çetinkaya <kadircetinkaya.06.tr at gmail.com>
Commit: 9dd1c66e8ffba73fead13aaf359e290f6e1d4899
https://github.com/llvm/llvm-project/commit/9dd1c66e8ffba73fead13aaf359e290f6e1d4899
Author: Luke Lau <luke at igalia.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/test/Transforms/LoopVectorize/AArch64/clamped-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/divs-with-scalable-vfs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/simple_early_exit.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-remove-loop-region.ll
M llvm/test/Transforms/LoopVectorize/ARM/optsize_minsize.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-masked-access.ll
M llvm/test/Transforms/LoopVectorize/RISCV/mask-index-type.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-interleave.ll
M llvm/test/Transforms/LoopVectorize/X86/constant-fold.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/outer_loop_test1_no_explicit_vect_width.ll
M llvm/test/Transforms/LoopVectorize/X86/scatter_crash.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-any-of-reductions.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/load-deref-pred-poison-ub-ops-feeding-pointer.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
M llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/scalable-inductions.ll
M llvm/test/Transforms/LoopVectorize/scalable-iv-outside-user.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit_live_outs.ll
M llvm/test/Transforms/LoopVectorize/uniform-blend.ll
M llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll
Log Message:
-----------
[VPlan] Expand VPWidenIntOrFpInductionRecipe into separate recipes (#118638)
The motivation of this PR is to make #115274 easier to implement, and
should allow us to add EVL support by just passing EVL to the VF
operand.
The current difficulty with widening IVs with EVL is that
VPWidenIntOrFpInductionRecipe generates its own backedge value. Since
it's a VPHeaderPHIRecipe the VF operand must be in the preheader, which
means we can't use the EVL since it's defined in the loop body.
The gist in this PR is to take the approach in #114305 and expand
VPWidenIntOrFpInductionRecipe into several recipes for the initial
value, phi and backedge value just before execution. I.e. this example:
```
vector.ph:
Successor(s): vector loop
<x1> vector loop: {
vector.body:
WIDEN-INDUCTION %i = phi %start, %step, %vf
...
EMIT branch-on-count ...
No successors
}
```
gets expanded to:
```
vector.ph:
...
vp<%induction.start> = ...
vp<%induction.increment> = ...
Successor(s): vector loop
<x1> vector loop: {
vector.body:
ir<%i> = WIDEN-PHI vp<%induction.start>, vp<%vec.ind.next>
...
vp<%vec.ind.next> = add ir<%i>, vp<%induction.increment>
EMIT branch-on-count ...
No successors
}
```
This allows us to a value defined in the loop in the backedge value, and
also means we can just reuse the existing backedge fixups in
VPlan::execute without having to specially handle it ourselves.
After this #115274 should just become a matter of setting the VF operand
to EVL (and building the increment step in the loop body, not the
preheader).
Commit: 9e0186d925f0c375a627866c59394f25c22eb3ff
https://github.com/llvm/llvm-project/commit/9e0186d925f0c375a627866c59394f25c22eb3ff
Author: Finn Plummer <finn.c.plum at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h
M llvm/include/llvm/Frontend/HLSL/HLSLRootSignatureUtils.h
M llvm/lib/Frontend/HLSL/HLSLRootSignatureUtils.cpp
M llvm/unittests/Frontend/CMakeLists.txt
A llvm/unittests/Frontend/HLSLRootSignatureRangesTest.cpp
Log Message:
-----------
[HLSL][RootSignature] Implement `ResourceRange` as an `IntervalMap` (#140957)
A resource range consists of a closed interval, `[a;b]`, denoting which
shader registers it is bound to.
For instance:
- `CBV(b1)` corresponds to the resource range of `[1;1]`
- `CBV(b0, numDescriptors = 3)` likewise to `[0;2]`
We want to provide an error diagnostic when there is an overlap in the
required registers (an overlap in the resource ranges).
The goal of this pr is to implement a structure to model a set of
resource ranges and provide an api to detect any overlap over a set of
resource ranges.
`ResourceRange` models this by implementing an `IntervalMap` to denote a
mapping from an interval of registers back to a resource range. It
allows for a new `ResourceRange` to be added to the mapping and it will
report if and what the first overlap is.
For the context of how this will be used in validation of a
`RootSignatureDecl` please see the proceeding pull request here:
https://github.com/llvm/llvm-project/pull/140962.
- Implements `ResourceRange` as an `IntervalMap`
- Adds unit testing of the various `insert` scenarios
Note: it was also considered to implement this as an `IntervalTree`,
this would allow reporting of a diagnostic for each overlap that is
encountered, as opposed to just the first. However, error generation of
just reporting the first error is already rather verbose, and adding the
additional diagnostics only made this worse.
Part 1 of https://github.com/llvm/llvm-project/issues/129942
Commit: ed07b54b38c675235b4ce1bfd49e1fff372f6520
https://github.com/llvm/llvm-project/commit/ed07b54b38c675235b4ce1bfd49e1fff372f6520
Author: Morris Hafner <mmha at users.noreply.github.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenStmt.cpp
M clang/lib/CIR/CodeGen/CIRGenValue.h
Log Message:
-----------
[CIR][NFCI] Represent Complex RValues As Single Value (#144519)
This patch removes one mlir::Value in the RValue class that has been
used to represent complex values in classic CG. In CIR we plan on
representing complex as a single value. It also removes some now
unnecessary member functions related to complex handling.
Commit: 3a06e9a710b7cfdbf1c002acc46fa76617e8baf8
https://github.com/llvm/llvm-project/commit/3a06e9a710b7cfdbf1c002acc46fa76617e8baf8
Author: Garvit Gupta <quic_garvgupt at quicinc.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M compiler-rt/lib/builtins/CMakeLists.txt
Log Message:
-----------
Conditionalise the addition of Aarch64 function Multi versioning support on aarch64 target (#143749)
Currently, `ENABLE_BAREMETAL_AARCH64_FMV` is added to builtin defines
for all baremetal targets though it is only needed for aarch64. This
patch fixes this by adding it only for aarch64 target.
Commit: 7ea710fafa5782a274ded2ab6933c63c5c71f2ee
https://github.com/llvm/llvm-project/commit/7ea710fafa5782a274ded2ab6933c63c5c71f2ee
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M libc/test/src/stdio/CMakeLists.txt
M libc/test/src/stdio/fdopen_test.cpp
M libc/test/src/stdio/fgetc_test.cpp
M libc/test/src/stdio/fgetc_unlocked_test.cpp
M libc/test/src/stdio/fgets_test.cpp
M libc/test/src/stdio/fileop_test.cpp
M libc/test/src/stdio/fopencookie_test.cpp
M libc/test/src/stdio/remove_test.cpp
M libc/test/src/stdio/rename_test.cpp
M libc/test/src/stdio/setvbuf_test.cpp
M libc/test/src/stdio/unlocked_fileop_test.cpp
M libc/test/src/stdlib/StrtolTest.h
M libc/test/src/stdlib/strtold_test.cpp
Log Message:
-----------
Fix/reapply "[libc] Migrate stdio tests to ErrnoCheckingTest. (#144134)
This reverts commit 92a116c4ef822950f8c57eaa5164c844c73a1f7e with a fix
for fgets test - convert nullptr to fgets return type (char*), since the
matcher is pedantic.
Commit: 4943e746909ddbf8845e7fa397a97b918bf777df
https://github.com/llvm/llvm-project/commit/4943e746909ddbf8845e7fa397a97b918bf777df
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/fallback.ll
Log Message:
-----------
fixup! [Remarks] Elaborate on called intrinsics (#143985)
Commit: 030b5519ec139757c13a6d6f337e69750ec24d6e
https://github.com/llvm/llvm-project/commit/030b5519ec139757c13a6d6f337e69750ec24d6e
Author: Yijia Gu <yijiagu at google.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] add missing deps for XeGPUTransforms
Commit: b876b3fa98cffd5b8755398f9a8218f667464d76
https://github.com/llvm/llvm-project/commit/b876b3fa98cffd5b8755398f9a8218f667464d76
Author: vitor1001 <56533861+vitor1001 at users.noreply.github.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/lib/Headers/__clang_cuda_intrinsics.h
Log Message:
-----------
Add missing intrinsics to cuda headers (#143664)
LLVM prevents the sm_32_intrinsics.hpp header from being included with a
#define __SM_32_INTRINSICS_HPP__. It also provides drop-in replacements
of the functions defined in the CUDA header.
One issue is that some intrinsics were added after the replacement was
written, and thus have no replacement, breaking code that calls them
(Raft is one example).
This patch adds the missing intrinsics.
Commit: 0cfc59ff51720ee60a71dd34077fc161886a3701
https://github.com/llvm/llvm-project/commit/0cfc59ff51720ee60a71dd34077fc161886a3701
Author: Yijia Gu <yijiagu at google.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] remove extra empty space for XeGPUTransforms
Commit: e29bb9a038245320164c5890d1a75843e4a664ef
https://github.com/llvm/llvm-project/commit/e29bb9a038245320164c5890d1a75843e4a664ef
Author: S. VenkataKeerthy <31350914+svkeerthy at users.noreply.github.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Analysis/IR2Vec.cpp
Log Message:
-----------
[IR2Vec] Consider only reachable BBs and non-debug instructions (#143476)
Changes to consider BBs that are reachable from the entry block. Similarly we skip debug instruction while computing the embeddings.
(Tracking issue - #141817)
Commit: 31523de4b000ca254259ae3167d28922e1302648
https://github.com/llvm/llvm-project/commit/31523de4b000ca254259ae3167d28922e1302648
Author: Garvit Gupta <quic_garvgupt at quicinc.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/lib/Driver/ToolChains/BareMetal.cpp
M clang/test/Driver/aarch64-toolchain-extra.c
M clang/test/Driver/aarch64-toolchain.c
M clang/test/Driver/arm-toolchain-extra.c
M clang/test/Driver/arm-toolchain.c
M clang/test/Driver/baremetal-multilib.yaml
M clang/test/Driver/baremetal-sysroot.cpp
M clang/test/Driver/baremetal.cpp
Log Message:
-----------
[Driver] Fix link order of BareMetal toolchain object (#132806)
The linker job in BareMetal toolchain object will be used by GNU ld and
lld both.
However, gnuld process the arguments in the order in which they appear
on command
line, whereas there is no such restriction with lld.
The previous order was:
LibraryPaths -> Libraries -> LTOOptions -> LinkerInputs
The new order is:
LibraryPaths -> LTOOptions -> LinkerInputs -> Libraries
LTO options need to be added before adding any linker inputs because
file format
after compile stage during LTO is bitcode which gnuld natively cannot
process.
Hence will need to pass appropriate plugins before adding any bitcode
file on the
command line.
Object files that are getting linked need to be passed before processing
any
libraries so that gnuld can appropriately do symbol resolution for the
symbols
for which no definition is provided through user code.
Similar link order is also followed by other linker jobs for gnuld such
as in
gnutools::Linker in Gnu.cpp
This is the 3rd patch in the series of patches of merging RISCVToolchain
into
BareMetal toolchain object.
RFC:
https://discourse.llvm.org/t/merging-riscvtoolchain-and-baremetal-toolchains/75524
Commit: 2ab9c35ea93f8557827d4cadcceb05e4eed2d30a
https://github.com/llvm/llvm-project/commit/2ab9c35ea93f8557827d4cadcceb05e4eed2d30a
Author: joaosaffran <126493771+joaosaffran at users.noreply.github.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/include/llvm/BinaryFormat/DXContainer.h
M llvm/include/llvm/BinaryFormat/DXContainerConstants.def
Log Message:
-----------
[DXContainer] Update DXContainer to match D3D12 spec (#143201)
Update the descriptor range flag values in DXContainerConstants.def to
match
the Direct3D12 specification. This changes two aspects:
1. Modify the DESCRIPTOR_RANGE_FLAG macro to use direct values instead
of
bit shifts
2. Update the flag values to use hex notation and match D3D12's
D3D12_DESCRIPTOR_RANGE_FLAGS enumeration:
- DESCRIPTORS_VOLATILE: 0x1
- DATA_VOLATILE: 0x2
- DATA_STATIC_WHILE_SET_AT_EXECUTE: 0x4
- DATA_STATIC: 0x8
- DESCRIPTORS_STATIC_KEEPING_BUFFER_BOUNDS_CHECKS: 0x10000
3. Removed NONE value from ROOT_DESCRIPTOR_FLAG
This ensures better compatibility with the D3D12 API and makes the
values
more explicit in the code.
Requested here:
https://github.com/llvm/llvm-project/pull/138315#discussion_r2132818269
---------
Co-authored-by: joaosaffran <joao.saffran at microsoft.com>
Commit: bb288de4e0e74f235402ff41be60dabcd57e379f
https://github.com/llvm/llvm-project/commit/bb288de4e0e74f235402ff41be60dabcd57e379f
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Utils/LoopPeel.cpp
M llvm/test/Transforms/LoopUnroll/peel-last-iteration-minmax.ll
Log Message:
-----------
[LoopPeel] Support last iteration peeling of min/max intrinsics (#143598)
This isn't terribly useful at the moment because of the step=1
restriction but it should be functionally sound. This is mostly just
making sure the codepaths don't diverge as we make other changes.
Commit: 8cd05b88ec623018ca2c68cf2418d2beed026d27
https://github.com/llvm/llvm-project/commit/8cd05b88ec623018ca2c68cf2418d2beed026d27
Author: Finn Plummer <finn.c.plum at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/include/clang/Parse/Parser.h
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaHLSL.cpp
Log Message:
-----------
[NFC][HLSL] Move Sema work from `ParseMicrosoftRootSignatureAttributeArgs` (#143184)
This separates semantic analysis from parsing by moving `RootSignatureDecl` creation, scope storage, and lookup logic into
`SemaHLSL`.
For more context see:
https://github.com/llvm/llvm-project/issues/142834.
- Define `ActOnStartRootSignatureDecl` and `ActOnFinishRootSignatureDecl` on `SemaHLSL`
- NFC so no test changes.
Resolves: https://github.com/llvm/llvm-project/issues/142834
---------
Co-authored-by: Aaron Ballman <aaron at aaronballman.com>
Commit: 80f3a28bbe7c2e17fb4b60e974c4157ec7e1eefc
https://github.com/llvm/llvm-project/commit/80f3a28bbe7c2e17fb4b60e974c4157ec7e1eefc
Author: Justin King <jcking at wulver.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M compiler-rt/lib/lsan/lsan_allocator.cpp
M compiler-rt/lib/lsan/lsan_allocator.h
M compiler-rt/lib/lsan/lsan_interceptors.cpp
M compiler-rt/lib/lsan/lsan_malloc_mac.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_malloc_mac.inc
Log Message:
-----------
Revert "lsan: Support free_sized and free_aligned_sized from C23" (#144575)
Reverts llvm/llvm-project#144415
Need to update approach to handle Apple platforms gracefully.
Commit: 391dafd8af9c0309f2ca75621dae1dbae307b428
https://github.com/llvm/llvm-project/commit/391dafd8af9c0309f2ca75621dae1dbae307b428
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
Log Message:
-----------
[RISCV] Consolidate both copies of getLMUL1VT [nfc] (#144568)
Put one copy on RISCVTargetLowering as a static function so that both
locations can use it, and rename the method to getM1VT for slightly
improved readability.
Commit: 1f10c6a277fbc1b1c6ceb7546b001af39feb92ce
https://github.com/llvm/llvm-project/commit/1f10c6a277fbc1b1c6ceb7546b001af39feb92ce
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
Log Message:
-----------
[Matrix] Hoist more IRBuilder<>'s. NFC
Commit: b59d4cf05447fdaf3d3c859e10db0b3c892f6ec6
https://github.com/llvm/llvm-project/commit/b59d4cf05447fdaf3d3c859e10db0b3c892f6ec6
Author: Joshua Batista <jbatista at microsoft.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Target/DirectX/DXILPrepare.cpp
M llvm/test/CodeGen/DirectX/llc-vector-load-scalarize.ll
A llvm/test/CodeGen/DirectX/noop_bitcast_global_array_type.ll
Log Message:
-----------
[Reland] Adjust bit cast instruction filter for DXIL Prepare pass (#143783)
Relands https://github.com/llvm/llvm-project/pull/142678, with a new
change to remove an unnecessary gep argument, after a revert was needed
due to unforeseen bugs.
Fixes https://github.com/llvm/llvm-project/issues/139013
Commit: dd65e6e0608c3390752750a0f19bca4409603db9
https://github.com/llvm/llvm-project/commit/dd65e6e0608c3390752750a0f19bca4409603db9
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
A offload/cmake/caches/AMDGPULibcBot.cmake
Log Message:
-----------
[Offload][libc] Add cmake cache AMDGPU buildbot (#144500)
An upcoming libc4GPU buildbot will be using this CMake cache file for
its build configuration.
Commit: 9cb754509608b9d9143fa17f775631bbfcce0848
https://github.com/llvm/llvm-project/commit/9cb754509608b9d9143fa17f775631bbfcce0848
Author: Garvit Gupta <quic_garvgupt at quicinc.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/lib/Driver/ToolChains/BareMetal.cpp
A clang/test/Driver/baremetal-undefined-symbols.c
R clang/test/Driver/riscv-args.c
Log Message:
-----------
[Driver] Add option to force undefined symbols during linking in BareMetal toolchain object. (#132807)
Add support for `-u` option to force defined symbols. This option is
supported by both lld and gnuld.
This is done as a part of the effort to merge RISCVToolchain object into
BareMetal toolchain object.
This is the 4th patch in the series of patches for merging
RISCVToolchain object into BareMetal toolchain object.
RFC:
https://discourse.llvm.org/t/merging-riscvtoolchain-and-baremetal-toolchains/75524
Commit: 57828fec760f086b334ce0cb1c465fc559dcaea4
https://github.com/llvm/llvm-project/commit/57828fec760f086b334ce0cb1c465fc559dcaea4
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Descriptor.cpp
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/Floating.h
M clang/lib/AST/ByteCode/Integral.h
M clang/lib/AST/ByteCode/IntegralAP.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
M clang/lib/AST/ByteCode/InterpState.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ByteCode/PrimType.h
M clang/lib/AST/ByteCode/Program.h
M clang/test/AST/ByteCode/builtin-bit-cast-long-double.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
Log Message:
-----------
Revert "[clang][bytecode] Allocate IntegralAP and Floating types using an allocator (#144246)"
This reverts commit c66be289901b3f035187d391e80e3610d7d6232e.
This breaks the armv8-quick builder:
https://lab.llvm.org/buildbot/#/builders/154/builds/17549
Commit: 667c7860ef5cc67a94c5233ff1be9c0e113ac514
https://github.com/llvm/llvm-project/commit/667c7860ef5cc67a94c5233ff1be9c0e113ac514
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
M clang/test/CIR/CodeGen/string-literals.c
A clang/test/CIR/CodeGen/string-literals.cpp
Log Message:
-----------
[CIR] Handle global string literals as char array initializer (#144384)
This change adds the line of code needed to handle a string literal as
an initializer for a character array.
Commit: b1aa845595c4dc204dfbe0e48481572e936620fc
https://github.com/llvm/llvm-project/commit/b1aa845595c4dc204dfbe0e48481572e936620fc
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M libcxx/include/fstream
Log Message:
-----------
[libc++][NFC] Consistently qualify calls to C functions in <fstream> (#144539)
Commit: 19658d14749876cf0b6633f210c923be3709323b
https://github.com/llvm/llvm-project/commit/19658d14749876cf0b6633f210c923be3709323b
Author: Andrew Rogers <andrurogerz at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/include/llvm/Target/CGPassBuilderOption.h
M llvm/include/llvm/Target/TargetLoweringObjectFile.h
M llvm/include/llvm/Target/TargetMachine.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
M llvm/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
M llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
M llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
M llvm/lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp
M llvm/lib/Target/AVR/AVRAsmPrinter.cpp
M llvm/lib/Target/AVR/AVRTargetMachine.cpp
M llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
M llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.cpp
M llvm/lib/Target/AVR/TargetInfo/AVRTargetInfo.cpp
M llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
M llvm/lib/Target/BPF/BPFAsmPrinter.cpp
M llvm/lib/Target/BPF/BPFTargetMachine.cpp
M llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
M llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp
M llvm/lib/Target/BPF/TargetInfo/BPFTargetInfo.cpp
M llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
M llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
M llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp
M llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
M llvm/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp
M llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
M llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp
M llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp
M llvm/lib/Target/Lanai/LanaiTargetMachine.cpp
M llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp
M llvm/lib/Target/Lanai/TargetInfo/LanaiTargetInfo.cpp
M llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
M llvm/lib/Target/LoongArch/Disassembler/LoongArchDisassembler.cpp
M llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
M llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp
M llvm/lib/Target/LoongArch/TargetInfo/LoongArchTargetInfo.cpp
M llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
M llvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp
M llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp
M llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp
M llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
M llvm/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp
M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
M llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.cpp
M llvm/lib/Target/Mips/MipsTargetMachine.cpp
M llvm/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
M llvm/lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.cpp
M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
M llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
M llvm/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCTargetDesc.cpp
M llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/SPIRV/TargetInfo/SPIRVTargetInfo.cpp
M llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
M llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
M llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
M llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
M llvm/lib/Target/Sparc/SparcTargetMachine.cpp
M llvm/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp
M llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
M llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
M llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
M llvm/lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp
M llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
M llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp
M llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.cpp
M llvm/lib/Target/VE/TargetInfo/VETargetInfo.cpp
M llvm/lib/Target/VE/VEAsmPrinter.cpp
M llvm/lib/Target/VE/VETargetMachine.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
M llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp
M llvm/lib/Target/WebAssembly/TargetInfo/WebAssemblyTargetInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
M llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
M llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
M llvm/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp
M llvm/lib/Target/XCore/XCoreAsmPrinter.cpp
M llvm/lib/Target/XCore/XCoreTargetMachine.cpp
M llvm/unittests/Target/AArch64/CMakeLists.txt
M llvm/unittests/Target/LoongArch/CMakeLists.txt
M llvm/unittests/Target/RISCV/CMakeLists.txt
M llvm/unittests/Target/SPIRV/CMakeLists.txt
M llvm/unittests/Target/VE/CMakeLists.txt
M llvm/unittests/Target/WebAssembly/CMakeLists.txt
Log Message:
-----------
[llvm] annotate interfaces in llvm/Target for DLL export (#143615)
## Purpose
This patch is one in a series of code-mods that annotate LLVM’s public
interface for export. This patch annotates the `llvm/Target` library.
These annotations currently have no meaningful impact on the LLVM build;
however, they are a prerequisite to support an LLVM Windows DLL (shared
library) build.
## Background
This effort is tracked in #109483. Additional context is provided in
[this
discourse](https://discourse.llvm.org/t/psa-annotating-llvm-public-interface/85307),
and documentation for `LLVM_ABI` and related annotations is found in the
LLVM repo
[here](https://github.com/llvm/llvm-project/blob/main/llvm/docs/InterfaceExportAnnotations.rst).
A sub-set of these changes were generated automatically using the
[Interface Definition Scanner (IDS)](https://github.com/compnerd/ids)
tool, followed formatting with `git clang-format`.
The bulk of this change is manual additions of `LLVM_ABI` to
`LLVMInitializeX` functions defined in .cpp files under llvm/lib/Target.
Adding `LLVM_ABI` to the function implementation is required here
because they do not `#include "llvm/Support/TargetSelect.h"`, which
contains the declarations for this functions and was already updated
with `LLVM_ABI` in a previous patch. I considered patching these files
with `#include "llvm/Support/TargetSelect.h"` instead, but since
TargetSelect.h is a large file with a bunch of preprocessor x-macro
stuff in it I was concerned it would unnecessarily impact compile times.
In addition, a number of unit tests under llvm/unittests/Target required
additional dependencies to make them build correctly against the LLVM
DLL on Windows using MSVC.
## Validation
Local builds and tests to validate cross-platform compatibility. This
included llvm, clang, and lldb on the following configurations:
- Windows with MSVC
- Windows with Clang
- Linux with GCC
- Linux with Clang
- Darwin with Clang
Commit: 7b7b5a397da1ecb9f767df5a3a3b6076cec109f9
https://github.com/llvm/llvm-project/commit/7b7b5a397da1ecb9f767df5a3a3b6076cec109f9
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
Log Message:
-----------
[AMDGPU] Remove AsmVOP3OpSel field completely. NFCI. (#144574)
Commit: 8dcf4ba6359578c4d944b75b3f96a1fbd4fb9528
https://github.com/llvm/llvm-project/commit/8dcf4ba6359578c4d944b75b3f96a1fbd4fb9528
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
Log Message:
-----------
[AMDGPU] Fix getAsmVOP3Base call agruments. (#144572)
https://github.com/llvm/llvm-project/pull/143465 has removed
getAsmVOP3OpSel and uses getAsmVOP3Base instead, but original
call to getAsmVOP3OpSel was using HasSrc*FloatMods and the
call to getAsmVOP3Base uses HasSrc*Mods. This does not play
well with opsel. An opsel instruction has modifiers in dag but
shall not have them in the asm string.
Commit: 73f307a5ca308d356c557734765742c26bf7ed03
https://github.com/llvm/llvm-project/commit/73f307a5ca308d356c557734765742c26bf7ed03
Author: Ashley Coleman <ascoleman at microsoft.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/CodeGenHLSL/builtins/firstbithigh.hlsl
M clang/test/CodeGenHLSL/builtins/firstbitlow.hlsl
Log Message:
-----------
[HLSL] Use ExtVector for firstbit intrinsics (#142679)
Fixes https://github.com/llvm/llvm-project/issues/142430
firstbit intrinsics were using the wrong vector type which causes some
conversions to fail. This PR switches them to ExtVector which resolves
the issue
Commit: a79186c1ea62bbe0579e0b1eed4ad507966cca41
https://github.com/llvm/llvm-project/commit/a79186c1ea62bbe0579e0b1eed4ad507966cca41
Author: Sam Elliott <quic_aelliott at quicinc.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/test/Driver/aarch64-toolchain.c
M clang/test/Driver/arm-toolchain.c
Log Message:
-----------
[Driver] Fix Arm/AArch64 Link Argument tests (#144582)
The openmp-offload-amdgpu-runtime-2 bot specifies default rtlib of
compiler-rt, but default unwindlib of libgcc. Change the tests to accept
that there may be `"--as-needed" "-lgcc_s" "--no-as-needed"` between
`libclang_rt.builtins.a` and `-lc`.
Relates to #121830
Commit: 7c4b2be983e900663a8d766ea9dc6f03b713e5b0
https://github.com/llvm/llvm-project/commit/7c4b2be983e900663a8d766ea9dc6f03b713e5b0
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M libcxx/include/streambuf
Log Message:
-----------
[libc++][NFC] Refactor basic_streambuf to use public API functions when possible (#144547)
The implementation of std::basic_streambuf used private member variables
to manipulate the get and the put areas. Using public API functions is
equivalent but leads to code that is easier to understand, since the
public API functions are known more widely than our internal member
variables. Using the public API functions removes the need to map the
internal member variables back to get/put area manipulation functions in
one's head.
Finally, it also makes it easier to find subtle issues by instrumenting
accessor functions, which is impossible if the class uses the member
variables directly.
Commit: 9ae4d2e01331ddeb2543f1940a09ef9c76ff5268
https://github.com/llvm/llvm-project/commit/9ae4d2e01331ddeb2543f1940a09ef9c76ff5268
Author: Sirraide <aeternalmail at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Support/Unix/Process.inc
Log Message:
-----------
[LLVM] [Support] Disable `ioctl()` terminal size check on Solaris (#144600)
#143514 broke the `clang-solaris11-sparcv9` bot; from what I can tell
that’s Solaris and according to `SolarisTargetInfo::getOSDefines`, the
macro `__sun__` should be defined on Solaris, so check for that and
don’t try to query the terminal size if it is defined.
Not sure this is the best solution but hopefully it fixes the bot.
Commit: c677a11c8d3223480cfe772e63fa0e7c09c76e2e
https://github.com/llvm/llvm-project/commit/c677a11c8d3223480cfe772e63fa0e7c09c76e2e
Author: David Peixotto <peix at meta.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M lldb/include/lldb/Core/PluginManager.h
M lldb/source/Core/PluginManager.cpp
A lldb/test/API/commands/plugin/TestPlugin.py
M lldb/test/Shell/Commands/command-plugin-list.test
Log Message:
-----------
[lldb] Add support to list/enable/disable remaining plugin types. (#143970)
In #134418 we added support to list/enable/disable `SystemRuntime` and
`InstrumentationRuntime` plugins. We limited it to those two plugin
types to flesh out the idea with a smaller change.
This PR adds support for the remaining plugin types. We now support all
the plugins that can be registered directly with the plugin manager.
Plugins that are added by loading shared objects are still not
supported.
Commit: 908f74a25e01cc88d1dee1af5521d8fb1c21bc51
https://github.com/llvm/llvm-project/commit/908f74a25e01cc88d1dee1af5521d8fb1c21bc51
Author: Andrew Rogers <andrurogerz at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/include/llvm/Target/TargetMachine.h
Log Message:
-----------
[llvm] re-order LLVM_ABI and extern on NoKernelInfoEndLTO decl (#144601)
## Overview
Fix compilation error introduced by #143615. Build failure logs
available
[here](https://lab.llvm.org/buildbot/#/builders/195/builds/10573)
## Background
On `extern` variable declarations, `LLVM_ABI` must appear before
`extern` because `LLVM_ABI` currently resolves to
`[[gnu::visibility("default")]]` when building with gcc.
Commit: 49bf8d38d80ce43bd700f27833a7b8c8e7082af8
https://github.com/llvm/llvm-project/commit/49bf8d38d80ce43bd700f27833a7b8c8e7082af8
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/include/llvm/Config/BUILD.gn
Log Message:
-----------
[gn build] Manually port b4e39e4f
Commit: 8d1610afd0db877460d1b3cd43cc4066478846a0
https://github.com/llvm/llvm-project/commit/8d1610afd0db877460d1b3cd43cc4066478846a0
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M libcxx/test/std/input.output/stream.buffers/streambuf/streambuf.protected/streambuf.get.area/setg.assert.pass.cpp
M libcxx/test/std/input.output/stream.buffers/streambuf/streambuf.protected/streambuf.put.area/setp.assert.pass.cpp
Log Message:
-----------
[libc++] Mark two assertion tests as unsupported in C++03 mode
Our assertion checking facility requires at least C++11, so these
tests were failing when run in C++03 mode.
Commit: 3c7df98c7b2a203e49a74b229bbf535c2ef6274b
https://github.com/llvm/llvm-project/commit/3c7df98c7b2a203e49a74b229bbf535c2ef6274b
Author: Piotr Idzik <65706193+vil02 at users.noreply.github.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang-tools-extra/docs/clang-tidy/checks/performance/enum-size.rst
Log Message:
-----------
[clang-tidy] Add missing colon in the docs of performance-enum-size (#144525)
There is a syntax error in the provided code example - this PR fixes it.
I did a quick search - I could not find similar _typos_.
Commit: ecfb8fe5c1870091b095ae6ca1ad4cfc7158e619
https://github.com/llvm/llvm-project/commit/ecfb8fe5c1870091b095ae6ca1ad4cfc7158e619
Author: Daniel Thornburgh <dthorn at google.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/docs/Toolchain.rst
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/lib/Driver/ToolChains/BareMetal.cpp
M clang/lib/Driver/ToolChains/BareMetal.h
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/include/c++/8.2.1/.keep
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/lib/.keep
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/lib/crt0.o
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/bin/aarch64-none-elf-ld
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/crtbegin.o
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/crtend.o
R clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crt0.o
R clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crtbegin.o
R clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crtend.o
R clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/bin/aarch64-none-elf-ld
R clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/include/c++/8.2.1/.keep
R clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/lib/.keep
R clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/lib/crt0.o
R clang/test/Driver/Inputs/basic_arm_gcc_tree/bin/armv6m-none-eabi-ld
R clang/test/Driver/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/crtbegin.o
R clang/test/Driver/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/crtend.o
R clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crt0.o
R clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crtbegin.o
R clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crtend.o
R clang/test/Driver/Inputs/basic_arm_nogcc_tree/bin/armv6m-none-eabi-ld
R clang/test/Driver/aarch64-gnutools.c
R clang/test/Driver/aarch64-toolchain-extra.c
R clang/test/Driver/aarch64-toolchain.c
R clang/test/Driver/arm-gnutools.c
R clang/test/Driver/arm-toolchain-extra.c
R clang/test/Driver/arm-toolchain.c
M clang/test/Driver/baremetal-multilib.yaml
M clang/test/Driver/baremetal-sysroot.cpp
R clang/test/Driver/baremetal-undefined-symbols.c
M clang/test/Driver/baremetal.cpp
R clang/test/Driver/check-no-multlib-warning.c
A clang/test/Driver/riscv-args.c
M clang/test/Driver/sanitizer-ld.c
Log Message:
-----------
Revert stack "[Driver] Add support for GCC installation detection in … (#144603)
…Baremetal toolchain (#121829)"
This reverts the following stack of commits, due to them breaking the
Fuchsia toolchain and corresponding LLVM buildbot.
Revert "[Driver] Fix Arm/AArch64 Link Argument tests (#144582)" This
reverts commit a79186c1ea62bbe0579e0b1eed4ad507966cca41.
Revert "[Driver] Add option to force undefined symbols during linking in
BareMetal toolchain object. (#132807)" This reverts commit
9cb754509608b9d9143fa17f775631bbfcce0848.
Revert "[Driver] Fix link order of BareMetal toolchain object (#132806)"
This reverts commit 31523de4b000ca254259ae3167d28922e1302648.
Revert "[Driver] Add support for crtbegin.o, crtend.o and libgloss lib
to BareMetal toolchain object (#121830)" This reverts commit
ec230aa7a7d13c222c0b34b87c3c16937383b4a0.
Revert "[Driver] Add support for GCC installation detection in Baremetal
toolchain (#121829)" This reverts commit
eb31c422d0dc816bf285a81bf92690d4d16273ed.
Commit: a5a0d880736f5dc6a566374bc3b3ca0d86901510
https://github.com/llvm/llvm-project/commit/a5a0d880736f5dc6a566374bc3b3ca0d86901510
Author: Sam Clegg <sbc at chromium.org>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M libcxx/include/__assert
M libcxx/src/verbose_abort.cpp
M libcxx/test/support/check_assertion.h
Log Message:
-----------
[libc++] Remove trailing newline from _LIBCPP_ASSERTION_HANDLER calls (#143573)
This newline was originally added in https://reviews.llvm.org/D142184
but I think updating `__libcpp_verbose_abort` to add newline instead is
more consistent, and works for other callers of `_LIBCPP_VERBOSE_ABORT`.
The `_LIBCPP_ASSERTION_HANDLER` calls through to either
`_LIBCPP_VERBOSE_ABORT` macro or the `__builtin_verbose_trap`. From what
I can tell neither of these function expect a trailing newline (at least
none of the usage of `_LIBCPP_VERBOSE_ABORT` or `__builtin_verbose_trap`
that I can find include a trailing newline except `_LIBCPP_ASSERTION_HANDLER`).
I noticed this discrepancy when working on
https://github.com/emscripten-core/emscripten/pull/24543
Commit: 844e41c2acedd5219d9363e38838abd5146f63c0
https://github.com/llvm/llvm-project/commit/844e41c2acedd5219d9363e38838abd5146f63c0
Author: sribee8 <sriya.pratipati at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M libc/src/__support/wchar/character_converter.cpp
Log Message:
-----------
[libc] Moved shared constexpr to the top (#144569)
Some conversions shared constexpr so moved to the top.
---------
Co-authored-by: Sriya Pratipati <sriyap at google.com>
Commit: 6fb36db4818abde56e5da47899dcdaacd8293903
https://github.com/llvm/llvm-project/commit/6fb36db4818abde56e5da47899dcdaacd8293903
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
Log Message:
-----------
[LinkerWrapper] Fix 'save-temps' when targeting SPIR-V (#144605)
Summary:
The logic here is flawed, it was only intended to apply to the CPU case
where we use the linker passed in on the command line. This was falsely
applying to SPIR-V which caused issues.
Commit: 362b9d78b4ee9107da2b5e90b3764b0f0fa610fe
https://github.com/llvm/llvm-project/commit/362b9d78b4ee9107da2b5e90b3764b0f0fa610fe
Author: John Harrison <harjohn at google.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/lldbdap_testcase.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_setBreakpoints.py
M lldb/test/API/tools/lldb-dap/cancel/TestDAP_cancel.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch.py
M lldb/test/API/tools/lldb-dap/module/TestDAP_module.py
M lldb/test/API/tools/lldb-dap/output/TestDAP_output.py
Log Message:
-----------
[lldb-dap] Refactoring DebugCommunication to improve test consistency. (#143818)
In DebugCommunication, we currently are using 2 thread to drive
lldb-dap. At the moment, they make an attempt at only synchronizing the
`recv_packets` between the reader thread and the main test thread. Other
stateful properties of the debug session are not guarded by a
locks/mutex.
To mitigate this, I am moving any state updates to the main thread
inside the `_recv_packet` method to ensure that between calls to
`_recv_packet` the state does not change out from under us in a test.
This does mean the precise timing of events has changed slightly as a
result and I've updated the existing tests that fail for me locally with
this new behavior.
I think this should result in overall more predictable behavior, even if
the test is slow due to the host workload or architecture differences.
---------
Co-authored-by: Ebuka Ezike <yerimyah1 at gmail.com>
Commit: 3f33c8482fc0b8dd0d2596262ebd0ed73d41665d
https://github.com/llvm/llvm-project/commit/3f33c8482fc0b8dd0d2596262ebd0ed73d41665d
Author: Eli Friedman <efriedma at quicinc.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
Log Message:
-----------
[clang] Add release note for int->enum conversion change. (#144407)
This seems to be having some practical impact, so we should let people
know.
Commit: f25f2f7de4f8264d89ba3c4dc9daddb10a90c13f
https://github.com/llvm/llvm-project/commit/f25f2f7de4f8264d89ba3c4dc9daddb10a90c13f
Author: Jianhui Li <jian.hui.li at intel.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp
M mlir/test/Dialect/XeGPU/xegpu-unroll-patterns.mlir
M mlir/test/lib/Dialect/XeGPU/TestXeGPUTransforms.cpp
Log Message:
-----------
[MLIR][XeGPU] Extend unrolling support for scatter ops with chunk_size (#144447)
Add support for load/store with chunk_size, which requires special
consideration for the operand blocking since offests and masks are
n-D and tensor are n+1-D. Support operations including create_tdesc,
update_tdesc, load, store, and prefetch.
---------
Co-authored-by: Adam Siemieniuk <adam.siemieniuk at intel.com>
Commit: fd7e46b864229a270726bd1026387740b9113094
https://github.com/llvm/llvm-project/commit/fd7e46b864229a270726bd1026387740b9113094
Author: Daniel Thornburgh <dthorn at google.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M libcxx/include/__assert
M libcxx/src/verbose_abort.cpp
M libcxx/test/support/check_assertion.h
Log Message:
-----------
Revert "[libc++] Remove trailing newline from _LIBCPP_ASSERTION_HANDLER calls" (#144615)
Reverts llvm/llvm-project#143573
Commit: 1cd18bc894b97b282677c1d140688a27ebbec924
https://github.com/llvm/llvm-project/commit/1cd18bc894b97b282677c1d140688a27ebbec924
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
A llvm/test/Analysis/CostModel/AMDGPU/maximumnum.ll
A llvm/test/Analysis/CostModel/AMDGPU/minimumnum.ll
Log Message:
-----------
AMDGPU: Add cost model tests for minimumnum/maximumnum (#141904)
The f16 cases in particular look broken since every vector size
has the same reported cost.
Commit: 87b13ada109643bbf5495727b0bf59a46bd533aa
https://github.com/llvm/llvm-project/commit/87b13ada109643bbf5495727b0bf59a46bd533aa
Author: Finn Plummer <finn.c.plum at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/include/llvm/Frontend/HLSL/HLSLRootSignatureUtils.h
M llvm/lib/Frontend/HLSL/HLSLRootSignatureUtils.cpp
M llvm/unittests/Frontend/HLSLRootSignatureDumpTest.cpp
Log Message:
-----------
[HLSL][RootSignature] Implement serialization of remaining Root Elements (#143198)
Implements serialization of the remaining `RootElement`s, namely
`RootDescriptor`s and `StaticSampler`s.
- Adds unit testing for the serialization methods
Resolves https://github.com/llvm/llvm-project/issues/138191
Resolves https://github.com/llvm/llvm-project/issues/138193
Commit: cb63b75e32a415c9bfc298ed7fdcd67e8d9de54c
https://github.com/llvm/llvm-project/commit/cb63b75e32a415c9bfc298ed7fdcd67e8d9de54c
Author: John Harrison <harjohn at google.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/lldbdap_testcase.py
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_setBreakpoints.py
M lldb/test/API/tools/lldb-dap/cancel/TestDAP_cancel.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch.py
M lldb/test/API/tools/lldb-dap/module/TestDAP_module.py
M lldb/test/API/tools/lldb-dap/output/TestDAP_output.py
Log Message:
-----------
Revert "[lldb-dap] Refactoring DebugCommunication to improve test consistency. (#143818)
This reverts commit 362b9d78b4ee9107da2b5e90b3764b0f0fa610fe.
Buildbots using python3.10 are running into errors from this change.
Commit: c9b28163888574bcfba0171372ae0dcfb40abbfa
https://github.com/llvm/llvm-project/commit/c9b28163888574bcfba0171372ae0dcfb40abbfa
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AMDGPU/canonicalize.ll
M llvm/test/Analysis/CostModel/AMDGPU/copysign.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f16.ll
Log Message:
-----------
AMDGPU: Fix cost model for 16-bit operations on gfx8 (#141943)
We should only divide the number of pieces to fit the packed instructions
if we actually have pk instructions. This increases the cost of copysign,
but is closer to the current codegen output. It could be much cheaper
than it is now.
Commit: 3800a83160a42f32947b82700e454cc07c600734
https://github.com/llvm/llvm-project/commit/3800a83160a42f32947b82700e454cc07c600734
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AMDGPU/copysign.ll
Log Message:
-----------
AMDGPU: Reduce cost of f64 copysign (#141944)
The real implementation is 1 real instruction plus a constant
materialize. Call that a 1, it's not a real f64 operation.
Commit: bec9ac2dafe1c9fca975721e9951c5f7f6b1b559
https://github.com/llvm/llvm-project/commit/bec9ac2dafe1c9fca975721e9951c5f7f6b1b559
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Transforms/IPO/FunctionSpecialization.cpp
Log Message:
-----------
[llvm] Lower latency bonus threshold in function specialization. (#143954)
Related to #143219.
Function specialization does not kick in if flang sets `noalias`
attributes on the function arguments of `digits_2`, because PRE
optimizes several `srem` instructions and other memory accesses
from the inner loops causing the latency bonus to be lower than
the current 40% threshold.
While looking at this, I did not really get why we compute the latency
bonus as a ratio of the latency of the "eliminated" instructions
and the code-size of the whole function. It did not make much sense
to me.
I tried computing the total latency as a sum of latencies
of the instructions that belong to non-dead code (including
the instructions that would be executed had they not been
"eliminated" due to the constant propagation). This total
latency should identify the total cost of executing the function
with the given argument being dynamically equal to the tried
constant value. Then the latency bonus would be computed
as the ratio between the latency of the "eliminated" instructions
and the total latency. Unfortunately, this did not given me a good
heuristics either. The bonus was close to 0% on some targets,
and as big as 3-5% on other targets. This does match very well
with the performance gain achieved by function specialization
for exchange2, so it seemd like another artificial heuristic
not better than the current one.
It seems that GCC uses a set of different heuristics for function
specialization, but I am not an expert here and I cannot say
if we can match them in LLVM.
With all that said, I decided to try to lower the threshold
to avoid the regression and be able to re-enable the generally
good change for `noalias` attribute.
With this patch, I was able to reduce the effect of `noalias`,
so that `-force-no-alias=true` is only ~10% slower than
`-force-no-alias=false` code on neoverse-v1 and neoverse-v2.
On neoverse-n1, `-force-no-alias=true` is >2x faster than
`-force-no-alias=false` regardless of this patch.
This threshold has been changed before also due to improved
alias information:
https://github.com/llvm/llvm-project/commit/2fb51fba8ca904a6d3ddf30ae94228ecf9e6a231#diff-066363256b7b4164e66b28a3028b2cb9e405c9136241baa33db76ebd2edb87cd
Please let me know what testing I should run to make sure this change
is safe. As I understand, it may affect the compilation time
performance,
and I will appreciate it if someone points out which benchmarks
need to be checked before merging this.
Commit: af65cb68f553759eac307edda87ff7d8b5fdffa9
https://github.com/llvm/llvm-project/commit/af65cb68f553759eac307edda87ff7d8b5fdffa9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
Log Message:
-----------
AMDGPU: Move fpenvIEEEMode into TTI (#141945)
Commit: 70343c8d44273c187e3f7fa5e2037fbc41307077
https://github.com/llvm/llvm-project/commit/70343c8d44273c187e3f7fa5e2037fbc41307077
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/Transforms/ControlFlowConverter.cpp
A flang/test/Fir/cfg-conversion-if.fir
M flang/test/Fir/fir-ops.fir
M flang/test/Fir/invalid.fir
M mlir/include/mlir/Dialect/ControlFlow/IR/ControlFlowOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Interfaces/ControlFlowInterfaces.h
M mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
M mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
M mlir/lib/Conversion/ControlFlowToLLVM/ControlFlowToLLVM.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Interfaces/ControlFlowInterfaces.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMIRToLLVMTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Conversion/ControlFlowToLLVM/branch.mlir
M mlir/test/Dialect/ControlFlow/invalid.mlir
M mlir/test/Dialect/ControlFlow/ops.mlir
M mlir/test/Target/LLVMIR/Import/metadata-profiling.ll
M mlir/test/Target/LLVMIR/llvmir-invalid.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[mlir][flang] Added Weighted[Region]BranchOpInterface's. (#142079)
The new interfaces provide getters and setters for the weight
information about the branches of BranchOpInterface and
RegionBranchOpInterface operations.
These interfaces are done the same way as LLVM dialect's
BranchWeightOpInterface.
The plan is to produce this information in Flang, e.g. mark
most probably "cold" code as such and allow LLVM to order
basic blocks accordingly. An example of such a code is
copy loops generated for arrays repacking - we can mark it
as "cold" assuming that the copy will not happen dynamically.
If the copy actually happens the overhead of the copy is probably high
enough so that we may not care about the little overhead
of jumping to the "cold" code and fetching it.
Commit: 54015f36c682aab9024a21a93957312a69c5bc9b
https://github.com/llvm/llvm-project/commit/54015f36c682aab9024a21a93957312a69c5bc9b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AMDGPU/maximumnum.ll
M llvm/test/Analysis/CostModel/AMDGPU/minimumnum.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f16.ll
Log Message:
-----------
AMDGPU: Cost model for minimumnum/maximumnum (#141946)
Commit: f08474ab1fa984560565e917453a42bc8562a6f9
https://github.com/llvm/llvm-project/commit/f08474ab1fa984560565e917453a42bc8562a6f9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
A llvm/test/Analysis/CostModel/AMDGPU/special-argument-intrinsics.ll
Log Message:
-----------
AMDGPU: Add baseline cost model tests for special argument intrinsics (#141947)
Commit: f3af1cd08cd456214961af915c17f858c9eef1a5
https://github.com/llvm/llvm-project/commit/f3af1cd08cd456214961af915c17f858c9eef1a5
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/get_vector_length.ll
M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/legalize-store-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
Log Message:
-----------
[RISCV] Set the exact flag on the SRL created for converting vscale to a read of vlenb. (#144571)
We know that vlenb is a multiple of RVVBytesPerBlock so we aren't
shifting out any non-zero bits.
Commit: a9811340b75baae8e06fb9ab83015a90d61510ee
https://github.com/llvm/llvm-project/commit/a9811340b75baae8e06fb9ab83015a90d61510ee
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AMDGPU/special-argument-intrinsics.ll
Log Message:
-----------
AMDGPU: Report special input intrinsics as free (#141948)
Commit: 628274dadf92995f4544d6134cba45d327d9eaaa
https://github.com/llvm/llvm-project/commit/628274dadf92995f4544d6134cba45d327d9eaaa
Author: Sterling-Augustine <56981066+Sterling-Augustine at users.noreply.github.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
A llvm/include/llvm/DebugInfo/DWARF/DWARFCFIPrinter.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFCFIProgram.h
M llvm/lib/DebugInfo/DWARF/CMakeLists.txt
A llvm/lib/DebugInfo/DWARF/DWARFCFIPrinter.cpp
M llvm/lib/DebugInfo/DWARF/DWARFCFIProgram.cpp
M llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp
M llvm/tools/llvm-readobj/DwarfCFIEHPrinter.h
Log Message:
-----------
[NFC] Extract Printing portions of DWARFCFIProgram to new files (#143762)
CFIPrograms' most common uses are within debug frames, but it is not
their only use. For example, some assembly writers encode them by hand
into .cfi_escape directives. This PR extracts printing code for them
into its own files, which avoids the need for the main class to depend
on DWARFUnit, sections, and similar.
One in a series of NFC DebugInfo/DWARF refactoring changes to layer it
more cleanly, so that binary CFI parsing can be used from low-level
code, (such as byte strings created via .cfi_escape) without circular
dependencies. The final goal is to make a more limited dwarf library
usable from lower-level code.
More information can be found at
https://discourse.llvm.org/t/rfc-debuginfo-dwarf-refactor-into-to-lower-and-higher-level-libraries/86665
Commit: a871b919ed135b3b50db58ed816d6ddb488d9c5e
https://github.com/llvm/llvm-project/commit/a871b919ed135b3b50db58ed816d6ddb488d9c5e
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Frontend/BUILD.gn
Log Message:
-----------
[gn build] Port 9e0186d925f0
Commit: 535291409cc7e4ae571318a38bd3617d7f608002
https://github.com/llvm/llvm-project/commit/535291409cc7e4ae571318a38bd3617d7f608002
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/Mips/MCTargetDesc/BUILD.gn
Log Message:
-----------
[gn build] Port 9ec75a50bc48
Commit: 6652961ae5fee4d81871e4310a9e842c61136c10
https://github.com/llvm/llvm-project/commit/6652961ae5fee4d81871e4310a9e842c61136c10
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/utils/gn/secondary/lldb/test/BUILD.gn
Log Message:
-----------
[gn build] Manually port 556e69b7
Commit: b164d3613ad9b86a8b951cfc43fadc0edfc7644e
https://github.com/llvm/llvm-project/commit/b164d3613ad9b86a8b951cfc43fadc0edfc7644e
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/DebugInfo/DWARF/BUILD.gn
Log Message:
-----------
[gn build] Port 628274dadf92
Commit: f2d2c99866dfd133e7b9c98b1d4983c6bce33d67
https://github.com/llvm/llvm-project/commit/f2d2c99866dfd133e7b9c98b1d4983c6bce33d67
Author: Eli Friedman <efriedma at quicinc.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/lib/Sema/SemaDecl.cpp
M clang/test/SemaCXX/builtin-is-constant-evaluated.cpp
M clang/test/SemaCXX/class.cpp
M clang/test/SemaCXX/cxx0x-class.cpp
M clang/test/SemaCXX/cxx2a-consteval.cpp
M clang/test/SemaTemplate/instantiate-static-var.cpp
Log Message:
-----------
[clang] Remove separate evaluation step for static class member init. (#142713)
We already evaluate the initializers for all global variables, as
required by the standard. Leverage that evaluation instead of trying to
separately validate static class members.
This has a few benefits:
- Improved diagnostics; we now get notes explaining what failed to
evaluate.
- Improved correctness: is_constant_evaluated is handled correctly.
The behavior follows the proposed resolution for CWG1721.
Fixes #88462. Fixes #99680.
Commit: c21a4c6c43bb6d68dfe52e07a5a391a6167eedf9
https://github.com/llvm/llvm-project/commit/c21a4c6c43bb6d68dfe52e07a5a391a6167eedf9
Author: Andrei Safronov <andrei.safronov at espressif.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
M llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.h
M llvm/lib/Target/Xtensa/XtensaFeatures.td
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
M llvm/lib/Target/Xtensa/XtensaSubtarget.h
A llvm/test/MC/Disassembler/Xtensa/coprocessor.txt
A llvm/test/MC/Disassembler/Xtensa/debug.txt
A llvm/test/MC/Disassembler/Xtensa/exception.txt
A llvm/test/MC/Disassembler/Xtensa/highinterrupts.txt
A llvm/test/MC/Disassembler/Xtensa/interrupt.txt
A llvm/test/MC/Disassembler/Xtensa/prid.txt
A llvm/test/MC/Disassembler/Xtensa/timer.txt
M llvm/test/MC/Xtensa/Core/processor-control.s
A llvm/test/MC/Xtensa/coprocessor.s
A llvm/test/MC/Xtensa/debug-invalid.s
A llvm/test/MC/Xtensa/debug.s
A llvm/test/MC/Xtensa/exception.s
A llvm/test/MC/Xtensa/highinterrupts.s
A llvm/test/MC/Xtensa/interrupt.s
A llvm/test/MC/Xtensa/prid.s
A llvm/test/MC/Xtensa/timer.s
Log Message:
-----------
[Xtensa] Implement Xtensa Interrupt/Exception/Debug Options. (#143820)
Implement Xtensa Interrupt. HighInterrupts, Exception, Debug Options.
Also implement small Xtensa Options like PRID, Coprocessor and Timers.
Commit: 15482c83aa2b05779d7ad947c34835656ab9da1c
https://github.com/llvm/llvm-project/commit/15482c83aa2b05779d7ad947c34835656ab9da1c
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Transforms/IPO/ElimAvailExtern.cpp
A llvm/test/Transforms/EliminateAvailableExternally/convert-global-variables-to-local.ll
Log Message:
-----------
[ElimAvailExtern] Add an option to allow to convert global variables in a specified address space to local (#144287)
Currently, the `EliminateAvailableExternallyPass` only converts certain
available externally functions to local if `avail-extern-to-local` is
set or in
contextual profiling mode. For global variables, it only drops their
initializers.
This PR adds an option to allow the pass to convert global variables in
a
specified address space to local. The motivation for this change is to
correctly
support lowering of LDS variables (`__shared__` variables, in more
generic
terminology) when ThinLTO is enabled for AMDGPU.
A `__shared__` variable is lowered to a hidden global variable in a
particular
address space by the frontend, which is roughly same as a `static` local
variable. To properly lower it in the backend, the compiler needs to
check all
its uses. Enabling ThinLTO currently breaks this when a function
containing a
`__shared__` variable is imported from another module. Even though the
global
variable is imported along with its associated function, and the
function is
privatized by the `EliminateAvailableExternallyPass`, the global
variable itself
is not.
It's safe to privatize such global variables, because they're _local_ to
their
associated functions. If the function itself is privatized, its
associated
global variables should also be privatized accordingly.
Commit: 64155a32297f4884875783664ff13bec9ab376f5
https://github.com/llvm/llvm-project/commit/64155a32297f4884875783664ff13bec9ab376f5
Author: Minding <77574923+Minding000 at users.noreply.github.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm-c/ExecutionEngine.h
Log Message:
-----------
Added clarifying comment to 'LLVMLinkInMCJIT' and 'LLVMLinkInInterpreter' (#92467)
Clarify that these functions are no-ops when linking to LLVM as a shared object.
Commit: abbdd1670d8b12dd72ec353b14e256619ff4694b
https://github.com/llvm/llvm-project/commit/abbdd1670d8b12dd72ec353b14e256619ff4694b
Author: Andrew Rogers <andrurogerz at gmail.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Core/Z3CrosscheckVisitor.cpp
M llvm/include/llvm/BinaryFormat/Dwarf.h
M llvm/include/llvm/Object/ELF.h
M llvm/lib/BinaryFormat/Dwarf.cpp
Log Message:
-----------
[llvm] minor fixes for clang-cl Windows DLL build (#144386)
## Purpose
This patch makes a minor changes to LLVM and Clang so that LLVM can be
built as a Windows DLL with `clang-cl`. These changes were not required
for building a Windows DLL with MSVC.
## Background
The Windows DLL effort is tracked in #109483. Additional context is
provided in [this
discourse](https://discourse.llvm.org/t/psa-annotating-llvm-public-interface/85307),
and documentation for `LLVM_ABI` and related annotations is found in the
LLVM repo
[here](https://github.com/llvm/llvm-project/blob/main/llvm/docs/InterfaceExportAnnotations.rst).
## Overview
Specific changes made in this patch:
- Remove `constexpr` fields that reference DLL exported symbols. These
symbols cannot be resolved at compile time when building a Windows DLL
using `clang-cl`, so they cannot be `constexpr`. Instead, they are made
`const` and initialized in the implementation file rather than at
declaration in the header.
- Annotate symbols now defined out-of-line with `LLVM_ABI` so they are
exported when building as a shared library.
- Explicitly add default copy assignment operator for `ELFFile` to
resolve a compiler warning.
## Validation
Local builds and tests to validate cross-platform compatibility. This
included llvm, clang, and lldb on the following configurations:
- Windows with MSVC
- Windows with Clang
- Linux with GCC
- Linux with Clang
- Darwin with Clang
Commit: 99e263228f4513c166f20469968b2b646edaaa33
https://github.com/llvm/llvm-project/commit/99e263228f4513c166f20469968b2b646edaaa33
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M .github/new-prs-labeler.yml
Log Message:
-----------
github: Add mips backend to PR autolabeler (#140909)
Commit: 4e090b6e84e33e2a442e3951253ca570f8f842f8
https://github.com/llvm/llvm-project/commit/4e090b6e84e33e2a442e3951253ca570f8f842f8
Author: Jason Molenda <jmolenda at apple.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M lldb/source/Core/DynamicLoader.cpp
Log Message:
-----------
[lldb] Re-insert code to search for a binary by filepath if provided
July 14 2024 I landed a change to update progress reporting when
loading kernel/firmware binaries
https://github.com/llvm/llvm-project/pull/98845
In DynamicLoader::LoadBinaryWithUUIDAndAddress I removed code that
was setting the ModuleSpec to the provided name, if the name provided
is that of a file on disk. With this code missing, if a filepath
name is passed in, this code will fail to find that binary on the local
disk. There's nothing in the PR / intention that would lead to this
change, it was unintentional.
Commit: 86a09f36154fbd264f61ea6462c8cf48b1ff2eb0
https://github.com/llvm/llvm-project/commit/86a09f36154fbd264f61ea6462c8cf48b1ff2eb0
Author: Jianhui Li <jian.hui.li at intel.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M mlir/test/Dialect/XeGPU/invalid.mlir
A mlir/test/Dialect/XeGPU/layout.mlir
M mlir/test/Dialect/XeGPU/ops.mlir
M mlir/test/Dialect/XeGPU/subgroup-map-propagation.mlir
M mlir/test/Dialect/XeGPU/xegpu-blocking.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-rr.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir
Log Message:
-----------
[MLIR][XeGPU] Clean up xegpu op tests (#144592)
Test cleanup:
1) separate layout.mlir from ops.mlir for layout related test
2) remove lane layout for ops working at work item scope.
3) remove redundant test in create_tdesc/update_tdesc/prefetch.
4) remove "test_" from all test function name.
Commit: 0defde8e06338cbe968d55d1d9e8581d55f3ae2b
https://github.com/llvm/llvm-project/commit/0defde8e06338cbe968d55d1d9e8581d55f3ae2b
Author: Harrison Hao <57025411+harrisonGPU at users.noreply.github.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/test/Transforms/InstCombine/AMDGPU/image-d16.ll
Log Message:
-----------
[AMDGPU] Support D16 folding for image.sample with multiple extractelement and fptrunc users (#141758)
Now we only support D16 folding for `image sample` instructions with a
single user: a `fptrunc` to half.
However, we can actually support D16 folding for image.sample
instructions with multiple users,
as long as each user follows the pattern of extractelement followed by
fptrunc to half.
For example:
```
%sample = call <4 x float> @llvm.amdgcn.image.sample
%e0 = extractelement <4 x float> %sample, i32 0
%h0 = fptrunc float %e0 to half
%e1 = extractelement <4 x float> %sample, i32 1
%h1 = fptrunc float %e1 to half
%e2 = extractelement <4 x float> %sample, i32 2
%h2 = fptrunc float %e2 to half
```
This change enables D16 folding for such cases and avoids generating
`v_cvt_f16_f32_e32` instructions.
Commit: 9265b1f0cff74c929214efb64f41183299f31772
https://github.com/llvm/llvm-project/commit/9265b1f0cff74c929214efb64f41183299f31772
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
M llvm/test/Transforms/LowerTypeTests/blockaddress-2.ll
M llvm/test/Transforms/LowerTypeTests/cfi-icall-alias.ll
M llvm/test/Transforms/LowerTypeTests/export-alias.ll
M llvm/test/Transforms/LowerTypeTests/export-icall.ll
M llvm/test/Transforms/LowerTypeTests/function-disjoint.ll
M llvm/test/Transforms/LowerTypeTests/function.ll
M llvm/test/Transforms/LowerTypeTests/icall-branch-funnel.ll
M llvm/test/Transforms/LowerTypeTests/pr37625.ll
M llvm/test/Transforms/LowerTypeTests/section.ll
Log Message:
-----------
LowerTypeTests: Use jump table entry type as value type of jump table alias.
The motivation for this is that it causes the jump table entry's symbol
to have an st_size equal to the jump table entry size, instead of being
equal to the size of the entire jump table, which is incorrect and can
lead to unexpected behavior in binary analysis tools that rely on the
size field such as Bloaty.
Reviewers: fmayer
Reviewed By: fmayer
Pull Request: https://github.com/llvm/llvm-project/pull/144462
Commit: 8ddada41df0488358373cff1d31a47e5ef4961e0
https://github.com/llvm/llvm-project/commit/8ddada41df0488358373cff1d31a47e5ef4961e0
Author: Jim Lin <jim at andestech.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Preprocessor/riscv-target-features-andes.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/features-info.ll
A llvm/test/MC/RISCV/xandesvbfhcvt-valid.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add Andes XAndesVBFHCvt (Andes Vector BFLOAT16 Conversion) extension (#144320)
The spec can be found at:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release.
This patch only supports assembler. The instructions are similar to
`Zvfbfmin` and the only difference with `Zvfbfmin` is that
`XAndesVBFHCvt` doesn't have mask variant.
Commit: a96a3f1b26baa8e5ee0abbac629f02566b7e9d1c
https://github.com/llvm/llvm-project/commit/a96a3f1b26baa8e5ee0abbac629f02566b7e9d1c
Author: Jacob Lalonde <jalalonde at fb.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M lldb/source/Plugins/Process/minidump/MinidumpParser.cpp
M lldb/source/Plugins/Process/minidump/MinidumpParser.h
Log Message:
-----------
[lldb][Minidump Parser] Implement a range data vector for minidump memory ranges (#136040)
Recently I was debugging a Minidump with a few thousand ranges, and came
across the (now deleted) comment:
```
// I don't have a sense of how frequently this is called or how many memory
// ranges a Minidump typically has, so I'm not sure if searching for the
// appropriate range linearly each time is stupid. Perhaps we should build
// an index for faster lookups.
```
blaming this comment, it's 9 years old! Much overdue for this simple fix
with a range data vector.
I had to add a default constructor to Range in order to implement the
RangeDataVector, but otherwise this just a replacement of look up logic.
Commit: a2ad65661ad560b04952d4d992248d2db3be36c8
https://github.com/llvm/llvm-project/commit/a2ad65661ad560b04952d4d992248d2db3be36c8
Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
A llvm/test/CodeGen/RISCV/xqcibm-cto-clo.ll
Log Message:
-----------
[RISCV] Add patterns for generating QC_CTO and QC_CLO (#144532)
These instructions count leading/trailing ones in the register.
Currently these are only generated when we have `Zbb` enabled (along
with `Xqcibm`) since it contains the `CTTZ/CTLZ` instructions.
Commit: e14f327d8094e02134efa98625acaf6fd43fee08
https://github.com/llvm/llvm-project/commit/e14f327d8094e02134efa98625acaf6fd43fee08
Author: Liao Chunyu <chunyu at iscas.ac.cn>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
Log Message:
-----------
[RISCV] Pre-test for #144461
Commit: af49a650e172d56d684581b66afa9ab0368ec8f9
https://github.com/llvm/llvm-project/commit/af49a650e172d56d684581b66afa9ab0368ec8f9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/test/CodeGen/PowerPC/f128-arith.ll
Log Message:
-----------
PowerPC: Add baseline tests for more f128 libcall handling (#144381)
Some of these incorrectly call the l suffixed version of libm
functions and others assert.
Commit: 7b9d10d2e6410029fd0750b2e0566432dbf03dc7
https://github.com/llvm/llvm-project/commit/7b9d10d2e6410029fd0750b2e0566432dbf03dc7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/test/CodeGen/PowerPC/f128-arith.ll
Log Message:
-----------
PowerPC: Fix using long double libm functions for f128 intrinsics (#144382)
This wasn't setting the correct libcall names, which default to the
l suffixed libm names.
Commit: ad9e591fd53f2cf91a2744973b59669d873658af
https://github.com/llvm/llvm-project/commit/ad9e591fd53f2cf91a2744973b59669d873658af
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
Log Message:
-----------
[SelectionDAG][RISCV] Fold (add (vscale * C0), (vscale * C1)) to (vscale * (C0 + C1)) in getNode. (#144565)
We already have shl/mul vscale related folds in getNode.
This is an alternative to the DAGCombine proposed in #144507.
Commit: 74687180dde07312521db09c6f6454fe9d1e5662
https://github.com/llvm/llvm-project/commit/74687180dde07312521db09c6f6454fe9d1e5662
Author: Kirill Chibisov <contact at kchibisov.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/EmitC/IR/CMakeLists.txt
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.h
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
A mlir/include/mlir/Dialect/EmitC/IR/EmitCInterfaces.h
A mlir/include/mlir/Dialect/EmitC/IR/EmitCInterfaces.td
R mlir/include/mlir/Dialect/EmitC/IR/EmitCTraits.h
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
M mlir/lib/Dialect/EmitC/Transforms/FormExpressions.cpp
M mlir/lib/Dialect/EmitC/Transforms/Transforms.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
Log Message:
-----------
[mlir][emitc] Make CExpression trait into interface (#142771)
By defining `CExpressionInterface`, we move the side effect detection
logic from `emitc.expression` into the individual operations
implementing the interface allowing operations to gradually tune the
side effect.
It also allows checking for side effects each operation individually.
Commit: 10f29a607205c0c17ee9249a66feb63f0fdae182
https://github.com/llvm/llvm-project/commit/10f29a607205c0c17ee9249a66feb63f0fdae182
Author: Kunqiu Chen <camsyn at foxmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M compiler-rt/lib/msan/msan_interceptors.cpp
Log Message:
-----------
[MSan] Fix wrong unpoison size in SignalAction (#144071)
MSan should unpoison the parameters of extended signal handlers.
However, MSan unpoisoned the second parameter with the wrong size
`sizeof(__sanitizer_sigaction)`, inconsistent with its real type
`siginfo_t`.
This commit fixes this issue by correcting the size to
`sizeof(__sanitizer_siginfo)`.
Commit: 4d71f20b287e398f10bbff55d52bec9683ef89d2
https://github.com/llvm/llvm-project/commit/4d71f20b287e398f10bbff55d52bec9683ef89d2
Author: Robert Imschweiler <robert.imschweiler at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
Log Message:
-----------
[GlobalISel] prevent G_UNMERGE_VALUES for vectors with different elements (#133335)
This commit prevents building a G_UNMERGE_VALUES instruction with
different source and destination vector elements in
`LegalizationArtifactCombiner::ArtifactValueFinder::tryCombineMergeLike()`,
e.g.:
`%1:_(<2 x s8>), %2:_(<2 x s8>) = G_UNMERGE_VALUES %0:_(<2 x s16>)`
This LLVM defect was identified via the AMD Fuzzing project.
Commit: 896e187a6e923b8441428f9db63c412d989fc51d
https://github.com/llvm/llvm-project/commit/896e187a6e923b8441428f9db63c412d989fc51d
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineAndMaskToShift - pull out repeated SDLoc(). NFC.
Commit: dac94f28e696e8234ec69bbed549533ea6b00227
https://github.com/llvm/llvm-project/commit/dac94f28e696e8234ec69bbed549533ea6b00227
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineAndNotOrIntoAndNotAnd - pull out repeated SDLoc(). NFC.
Commit: 0875bee2b10185eca40aea3b3f49eb8462522eda
https://github.com/llvm/llvm-project/commit/0875bee2b10185eca40aea3b3f49eb8462522eda
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineAndNotIntoANDNP - pull out repeated SDLoc(). NFC.
Commit: 44b715293fcad79ef4a54474627ac574a759fa5a
https://github.com/llvm/llvm-project/commit/44b715293fcad79ef4a54474627ac574a759fa5a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
A llvm/test/Transforms/PhaseOrdering/X86/fmaddsub.ll
Log Message:
-----------
[PhaseOrdering][X86] Copy FMUL+ADDSUB/FMADDSUB build vector patterns from codegen tests
As detailed on #144489 - confirm the vectorisation of scalar FMUL+ADDSUB/FMADDSUB on various targets
Commit: 45ea46c44636094e9fcdbbeabfd11f9d0fad5e38
https://github.com/llvm/llvm-project/commit/45ea46c44636094e9fcdbbeabfd11f9d0fad5e38
Author: Garvit Gupta <quic_garvgupt at quicinc.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/docs/Toolchain.rst
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/lib/Driver/ToolChains/BareMetal.cpp
M clang/lib/Driver/ToolChains/BareMetal.h
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/include/c++/8.2.1/.keep
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/lib/.keep
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/lib/crt0.o
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/bin/aarch64-none-elf-ld
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/crtbegin.o
A clang/test/Driver/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/crtend.o
A clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crt0.o
A clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crtbegin.o
A clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crtend.o
A clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/bin/aarch64-none-elf-ld
A clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/include/c++/8.2.1/.keep
A clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/lib/.keep
A clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/lib/crt0.o
A clang/test/Driver/Inputs/basic_arm_gcc_tree/bin/armv6m-none-eabi-ld
A clang/test/Driver/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/crtbegin.o
A clang/test/Driver/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/crtend.o
A clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crt0.o
A clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crtbegin.o
A clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crtend.o
A clang/test/Driver/Inputs/basic_arm_nogcc_tree/bin/armv6m-none-eabi-ld
A clang/test/Driver/aarch64-gnutools.c
A clang/test/Driver/aarch64-toolchain-extra.c
A clang/test/Driver/aarch64-toolchain.c
A clang/test/Driver/arm-gnutools.c
A clang/test/Driver/arm-toolchain-extra.c
A clang/test/Driver/arm-toolchain.c
M clang/test/Driver/baremetal.cpp
A clang/test/Driver/check-no-multlib-warning.c
Log Message:
-----------
Reland [Driver] Add support for GCC installation detection in Baremetal toolchain (#144640)
This patch introduces enhancements to the Baremetal toolchain to support
GCC toolchain detection.
- If the --gcc-install-dir or --gcc-toolchain options are provided and
point to valid paths, the sysroot is derived from those locations.
- If not, the logic falls back to the existing sysroot inference
mechanism already present in the Baremetal toolchain.
- Support for adding include paths for the libstdc++ library has also
been added.
Additionally, the restriction to always use the integrated assembler has
been removed. With a valid GCC installation, the GNU assembler can now
be used as well.
This patch currently updates and adds tests for the ARM target only.
RISC-V-specific tests will be introduced in a later patch, once the
RISCVToolChain is fully merged into the Baremetal toolchain. At this
stage, there is no way to test the RISC-V target within this PR.
RFC:
https://discourse.llvm.org/t/merging-riscvtoolchain-and-baremetal-toolchains/75524
Commit: e07b1b26c38ba48af247b370a29eeb9879cefc97
https://github.com/llvm/llvm-project/commit/e07b1b26c38ba48af247b370a29eeb9879cefc97
Author: Rajveer Singh Bharadwaj <rajveer.developer at icloud.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
Log Message:
-----------
[DAG] Implement SDPatternMatch `m_Abs()` matcher (#144512)
Commit: a38932ac3c0a16226e3dde7f1532f117959c58df
https://github.com/llvm/llvm-project/commit/a38932ac3c0a16226e3dde7f1532f117959c58df
Author: Robert Imschweiler <robert.imschweiler at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
Log Message:
-----------
Revert "[GlobalISel] prevent G_UNMERGE_VALUES for vectors with different elements" (#144650)
Reverts llvm/llvm-project#133335
Commit: 49df87e71b73b230ecb21335dcb5f5390eebdab3
https://github.com/llvm/llvm-project/commit/49df87e71b73b230ecb21335dcb5f5390eebdab3
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M libc/src/__support/FPUtil/dyadic_float.h
Log Message:
-----------
[libc][printf] Fix out-of-range shift in float320 printf (#144542)
If you enable `LIBC_CONF_PRINTF_FLOAT_TO_STR_USE_FLOAT320` and use a
`%f` style printf format directive to print a nonzero number too small
to show up in the output digits, e.g. `printf("%.2f", 0.001)`, then the
output would be intermittently incorrect, because
`DyadicFloat::as_mantissa_type_rounded` would try to shift the 320-bit
mantissa right by more than 320 bits, invoking the 'undefined behavior'
clause commented in the `shift()` function in `big_int.h`.
There were already tests in the libc test suite exercising this case,
e.g. the subnormal tests in `LlvmLibcSPrintfTest.FloatDecimalConv` use
`%f` at the default precision of 6 decimal places on tiny numbers such
as 2^-1027. But because the behavior is undefined, they don't visibly
fail all the time, and in all previous test runs we'd tried with
USE_FLOAT320, they had got lucky.
The fix is simply to detect an out-of-range right shift before doing it,
and instead just set the output value to zero.
Commit: ba40a7bc2e65be86ac23c9cf6038ac085dda77eb
https://github.com/llvm/llvm-project/commit/ba40a7bc2e65be86ac23c9cf6038ac085dda77eb
Author: Mel Chen <mel.chen at sifive.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/first-order-recurrence-scalable-vf1.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-scalable-vf1.ll
Log Message:
-----------
[LoopVectorize] Vectorize fixed-order recurrence with vscale x 1. (#142772)
When the fixed-order recurrence phi is live-out from the loop, the
vectorizer uses VPInstruction::ExtractPenultimateElement to extract the
penultimate element from the recurrence vector. However, this is not
feasible when the VF is vscale x 1, since vscale could be 1, making the
vector contain only one element.
This patch changes the behavior for vscale x 1 by extracting the last
element from the vector produced by splicing the recurrence phi and the
previous value. This ensures we can still determine the correct live-out
value of the recurrence phi.
Commit: ca29c632f06fc0e02ebbbb9fbdc73e3abd6b096b
https://github.com/llvm/llvm-project/commit/ca29c632f06fc0e02ebbbb9fbdc73e3abd6b096b
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
A llvm/test/CodeGen/RISCV/icmp-non-byte-sized.ll
M llvm/test/CodeGen/RISCV/memcmp-optsize.ll
M llvm/test/CodeGen/RISCV/memcmp.ll
Log Message:
-----------
[RISCV] Support non-power-of-2 types when expanding memcmp
We can convert non-power-of-2 types into extended value types
and then they will be widen.
Reviewers: lukel97
Reviewed By: lukel97
Pull Request: https://github.com/llvm/llvm-project/pull/114971
Commit: 59d6fbb8ffe03ceecfcc07ebe22e256c97ef70dd
https://github.com/llvm/llvm-project/commit/59d6fbb8ffe03ceecfcc07ebe22e256c97ef70dd
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M flang/lib/Optimizer/Builder/FIRBuilder.cpp
A flang/test/HLFIR/fir-local-alloca-block.fir
Log Message:
-----------
[flang][fir] Provide allocation block for `fir.local` when required (#144521)
Extends `fir::FirOpBuilder::getAllocaBlock()` to support `fir.local`.
This allows us to retrieve an allocation block when needed for
`fir.local`.
Commit: 255b55c602f73964262893859a543a115b278e21
https://github.com/llvm/llvm-project/commit/255b55c602f73964262893859a543a115b278e21
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
Log Message:
-----------
[GlobalOpt] Use cast instead of dyn_cast. NFC (#144634)
The dyn_cast was not checked for null, and the cast is guaranteed to
succeed by an earlier check.
Commit: 7ea7ccd24d603ceec6eb5194d98911e6ab7c0717
https://github.com/llvm/llvm-project/commit/7ea7ccd24d603ceec6eb5194d98911e6ab7c0717
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
M llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
M llvm/test/CodeGen/PowerPC/aix-cc-byval-mir.ll
M llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-mir.ll
M llvm/test/CodeGen/PowerPC/aix-vec-arg-spills.ll
M llvm/test/CodeGen/PowerPC/aix-vector-vararg-caller.ll
M llvm/test/CodeGen/PowerPC/aix-vector-vararg-fixed-caller.ll
Log Message:
-----------
[PowerPC][AIX] Specify pointer info and alignment for stack store (#144526)
When lowering call arguments to stack, specify a stack MPI, as well as
the stack alignment, instead of using the defaults (which would be an
unknown location with ABI alignment).
I believe the asm diffs are just changes in scheduling.
Commit: c16dc63b44ae039f2ac123a8ffbc90031767d00b
https://github.com/llvm/llvm-project/commit/c16dc63b44ae039f2ac123a8ffbc90031767d00b
Author: Mikael Holmen <mikael.holmen at ericsson.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
Log Message:
-----------
[OMPIRBuilder] Fix gcc -Wparentheses warning [NFC]
Without this gcc warned like
/repo/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp:7559:68: warning: suggest parentheses around '&&' within '||' [-Wparentheses]
7559 | NumStaleCIArgs == (OffloadingArraysToPrivatize.size() + 2) &&
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~
7560 | "Wrong number of arguments for StaleCI when shareds are present");
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Commit: 669627d0c77ed8408358bc8c5973255fe28a36ea
https://github.com/llvm/llvm-project/commit/669627d0c77ed8408358bc8c5973255fe28a36ea
Author: Philipp Jung <philippjung2010 at live.de>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang-tools-extra/clang-tidy/cppcoreguidelines/CMakeLists.txt
M clang-tools-extra/clang-tidy/cppcoreguidelines/CppCoreGuidelinesTidyModule.cpp
A clang-tools-extra/clang-tidy/cppcoreguidelines/UseEnumClassCheck.cpp
A clang-tools-extra/clang-tidy/cppcoreguidelines/UseEnumClassCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines/use-enum-class.rst
M clang-tools-extra/docs/clang-tidy/checks/list.rst
A clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/use-enum-class.cpp
Log Message:
-----------
Add check 'cppcoreguidelines-use-enum-class' (#138282)
Warn on non-class enum definitions as suggested by the Core Guidelines:
https://isocpp.github.io/CppCoreGuidelines/CppCoreGuidelines#Renum-class
Commit: 43e1a5a411d972fe06a1afb86ffd5ba21fd2a376
https://github.com/llvm/llvm-project/commit/43e1a5a411d972fe06a1afb86ffd5ba21fd2a376
Author: Frank Schlimbach <frank.schlimbach at intel.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.h
M mlir/include/mlir/Dialect/Mesh/Transforms/Passes.h
M mlir/include/mlir/Dialect/Mesh/Transforms/Passes.td
M mlir/lib/Dialect/Mesh/IR/MeshOps.cpp
M mlir/lib/Dialect/Mesh/Transforms/ShardingPropagation.cpp
A mlir/test/Dialect/Mesh/backward-sharding-propagation.mlir
A mlir/test/Dialect/Mesh/forward-backward-sharding-propagation.mlir
A mlir/test/Dialect/Mesh/forward-sharding-propagation.mlir
Log Message:
-----------
[mlir][mesh] adding option for traversal order in sharding propagation (#144079)
The traversal order in sharding propagation was hard-coded. This PR
provides options to the pass to select a suitable order
- forward-only
- backward-only
- forward-backward
- backward-forward
Default is the previous behavior (backward-forward).
Commit: 355725a25e6be38d7a97cab9e206d2a16a1bd849
https://github.com/llvm/llvm-project/commit/355725a25e6be38d7a97cab9e206d2a16a1bd849
Author: Kunqiu Chen <camsyn at foxmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp
M llvm/test/Instrumentation/ThreadSanitizer/atomic-non-integer.ll
Log Message:
-----------
[TSan] Fix missing inst cleanup (#144067)
Commit 44e875ad5b2ce26826dd53f9e7d1a71436c86212 introduced a change that
replaces `ReplaceInstWithInst` with `Instruction::replaceAllUsesWith`,
without subsequent instruction cleanup.
This results in TSan leaving behind useless `load atomic` instructions
after 'replacing' them.
This commit adds cleanup back, consistent with the context.
Commit: 8e157fdbb7b4af9f67b139a9f05feaa9b338d3f5
https://github.com/llvm/llvm-project/commit/8e157fdbb7b4af9f67b139a9f05feaa9b338d3f5
Author: Sirui Mu <msrlancern at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
M clang/test/CIR/CodeGen/builtin_call.cpp
Log Message:
-----------
[CIR] Add support for __builtin_assume (#144376)
This patch adds support for the `__builtin_assume` builtin function.
Commit: fe42d34274cac79794637bf2f69f85537dde8b74
https://github.com/llvm/llvm-project/commit/fe42d34274cac79794637bf2f69f85537dde8b74
Author: Ying Yi <ying.yi at sony.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/lib/Headers/bmiintrin.h
M clang/lib/Headers/immintrin.h
M clang/lib/Headers/keylockerintrin.h
M clang/lib/Headers/x86gprintrin.h
M clang/lib/Headers/x86intrin.h
Log Message:
-----------
[clang][headers]Remove unnecessary guard of !defined(__SCE__). (#144522)
Sony PlayStation now supports C++20, and we wish to change the default
C++ mode to C++20 sometime in the future. As such, the !defined(__SCE__)
guards are redundant and we want to remove them. This in turn makes the
entire guard lines redundant (always true), so this patch removes them
entirely.
Commit: 58c4fa96cb111ea8d399296838f4cb6a294115ca
https://github.com/llvm/llvm-project/commit/58c4fa96cb111ea8d399296838f4cb6a294115ca
Author: Karlo Basioli <k.basioli at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Fix bazel build for #142771 (#144659)
Commit: 6fcdde2a4eb9eaf34511ac3a35075be329fe1fae
https://github.com/llvm/llvm-project/commit/6fcdde2a4eb9eaf34511ac3a35075be329fe1fae
Author: Lucas Duarte Prates <lucas.prates at arm.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M runtimes/CMakeLists.txt
Log Message:
-----------
[runtimes] Allow use of external llvm-lit on standalone builds (#144347)
When creating a standalone build of the runtimes sub-project, the
current CMake implementation looks for a lit executable that might
potentially exist in the build tree and unconditionally overrides the
value of `LLVM_EXTERNAL_LIT`. Due to this, any value passed via
`-DLLVM_EXTERNAL_LIT` when configuring the CMake project is ignored.
This change adds the `ALLOW_EXTERNAL` argument to the
`get_llvm_lit_path` call in the runtimes' CMakeLists.txt, allowing any
value previously set to be considered.
Commit: 757a0e6d3b6130a984960ee413a3c8a6f99c7cb5
https://github.com/llvm/llvm-project/commit/757a0e6d3b6130a984960ee413a3c8a6f99c7cb5
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
A llvm/test/CodeGen/SystemZ/fake-use-size.ll
Log Message:
-----------
[SystemZ] Treat FAKE_USE instructions as instructions without a size (#144390)
This patch fixes an error in which `FAKE_USE` instructions would trigger
an assertion in SystemZLongBranch due to them having a size of 0 without
being excepted in the assertion that each instruction, other than a set
of known 0-size instruction types, should have a non-0 size.
`FAKE_USE` instructions are no-op instructions that are emitted into
LLVM by the `-fextend-variable-liveness` clang flag to help preserve the
liveness of source variables in optimized code, and therefore they
should be understood as being valid size 0 instructions.
Commit: bb00fd087a3c3e02fb812e41218ad0a85d9f0fe1
https://github.com/llvm/llvm-project/commit/bb00fd087a3c3e02fb812e41218ad0a85d9f0fe1
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/cppcoreguidelines/BUILD.gn
Log Message:
-----------
[gn build] Port 669627d0c77e
Commit: cd8248f3e856a37cc1addcb74475b4d37dc8aa42
https://github.com/llvm/llvm-project/commit/cd8248f3e856a37cc1addcb74475b4d37dc8aa42
Author: Scott Constable <scott.d.constable at intel.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/X86/X86AsmPrinter.cpp
M llvm/test/CodeGen/X86/kcfi-arity.ll
Log Message:
-----------
Fixed a bug in `-fsanitize-kcfi-arity` (#142867)
Compiling with `fsanitize-kcfi-arity` can crash the compiler if a
function has more than 6 arguments, including floating-point arguments
passed in XMM registers. This patch fixes the feature by only counter
integer and stack arguments toward kCFI arity. For example, the compiler
crashed when it attempted to generate kCFI arity information for this
function:
https://github.com/torvalds/linux/blob/16b70698aa3ae7888826d0c84567c72241cf6713/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h#L680
As noted in a comment, floating-point registers are not relevant to
enforcing kCFI at this time.
Commit: dac0820b277835b7506a9c0d1dc5e077597f6742
https://github.com/llvm/llvm-project/commit/dac0820b277835b7506a9c0d1dc5e077597f6742
Author: Bjorn Pettersson <bjorn.a.pettersson at ericsson.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/test/CodeGen/Thumb2/mve-shuffle.ll
M llvm/test/CodeGen/Thumb2/mve-vld3.ll
M llvm/test/CodeGen/Thumb2/schedm7-hazard.ll
Log Message:
-----------
[Thumb2] Regenerate some test checks. NFC
Commit: 5a9cc93a2058e2c26d766f7be6aee63e928bf825
https://github.com/llvm/llvm-project/commit/5a9cc93a2058e2c26d766f7be6aee63e928bf825
Author: Karlo Basioli <k.basioli at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Fix for bazel build #142079 (#144665)
Commit: a13b7cc00c5f4b9d2636ed7a22c1390cf8033baf
https://github.com/llvm/llvm-project/commit/a13b7cc00c5f4b9d2636ed7a22c1390cf8033baf
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/test/Transforms/LICM/call-hoisting.ll
M llvm/test/Transforms/LICM/funclet.ll
Log Message:
-----------
[LICM] Support hoisting of non-argmemonly readonly calls (#144497)
The code checking whether a readonly call is safe to hoist is
currently limited to only argmemonly calls. However, the actual
implementation does not depend on this in any way. It either
does an MSSA clobber walk on the memory access (which will take
all locations accessed by the call into account), or it will
look at all MemoryDefs in an entirely location-independent manner.
The current restriction dates back to the time when LICM still
supported AST, in which case this code *did* reason about the
individual pointer arguments.
Commit: ee4c2bb68752a6c4b463f3873cde278b8d348628
https://github.com/llvm/llvm-project/commit/ee4c2bb68752a6c4b463f3873cde278b8d348628
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M lldb/test/Shell/SymbolFile/DWARF/x86/explicit-member-function-quals.cpp
Log Message:
-----------
[lldb][test] explicit-member-function-quals.cpp: add -glldb
This will get un-XFAILed but requires `-glldb` in an upcoming patch.
Commit: 561eca44e7639ee8805d0bf65a59b9898d782538
https://github.com/llvm/llvm-project/commit/561eca44e7639ee8805d0bf65a59b9898d782538
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
A llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg-mir.ll
M llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
A llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg-mir.ll
M llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll
Log Message:
-----------
[PowerPC] Split tests into asm and mir parts (NFC)
To allow both to be generated.
Commit: acde20b5605f3a3a8da2217e4526fc045e6603ed
https://github.com/llvm/llvm-project/commit/acde20b5605f3a3a8da2217e4526fc045e6603ed
Author: Steven Perron <stevenperron at google.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/AST/HLSL/vk.spec-constant.usage.hlsl
R clang/test/CodeGenHLSL/inline-spirv/SpirvType.alignment.hlsl
R clang/test/CodeGenHLSL/inline-spirv/SpirvType.hlsl
A clang/test/CodeGenHLSL/vk-features/SpirvType.alignment.hlsl
A clang/test/CodeGenHLSL/vk-features/SpirvType.hlsl
A clang/test/CodeGenHLSL/vk-features/vk.spec-constant.hlsl
A clang/test/SemaHLSL/vk.spec-constant.error.hlsl
Log Message:
-----------
[HLSL][SPIRV] Add vk::constant_id attribute. (#143544)
The vk::constant_id attribute is used to indicate that a global const
variable
represents a specialization constant in SPIR-V. This PR adds this
attribute to clang.
The documentation for the attribute is
[here](https://github.com/microsoft/DirectXShaderCompiler/blob/main/docs/SPIR-V.rst#specialization-constants).
The strategy is to to modify the initializer to get the value of a
specialize constant for a builtin defined in the SPIR-V backend.
Implements https://github.com/llvm/wg-hlsl/pull/287
Fixes https://github.com/llvm/llvm-project/issues/142448
---------
Co-authored-by: Nathan Gauër <github at keenuts.net>
Commit: d3441f7348203cc2a1d9c44fd24c1113954aa2b2
https://github.com/llvm/llvm-project/commit/d3441f7348203cc2a1d9c44fd24c1113954aa2b2
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV] Change getSmallBestKnownTC to return an ElementCount (NFC) (#141793)
This is prep work for enabling better UF calculations when using vscale
based VFs to vectorise loops with vscale based tripcounts.
NOTE: NFC because All uses remain fixed-length until a following PR
changes LoopVectorize's version of getSmallConstantTripCount().
Commit: b7ef5dbac91f9ccaf335ae4dd998e5783523f24e
https://github.com/llvm/llvm-project/commit/b7ef5dbac91f9ccaf335ae4dd998e5783523f24e
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
M llvm/test/CodeGen/AArch64/complex-deinterleaving-splat-scalable.ll
Log Message:
-----------
[LLVM][ComplexDeinterleaving] Update splat identification to include vector ConstantInt/FP. (#144516)
Commit: b5967264b0fbfd502b3a7edec27409e966fb68be
https://github.com/llvm/llvm-project/commit/b5967264b0fbfd502b3a7edec27409e966fb68be
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/Support/CodeGen.h
M llvm/include/llvm/Target/TargetOptions.h
Log Message:
-----------
CodeGen: Move ABI option enums to support (#142912)
Move these out of TargetOptions and into Support to avoid
the dependency on Target. There are similar ABI options
already in Support/CodeGen.h.
Commit: 4aca3dc48b0919b81bd86302b141f29869266c45
https://github.com/llvm/llvm-project/commit/4aca3dc48b0919b81bd86302b141f29869266c45
Author: Robert Imschweiler <robert.imschweiler at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
Log Message:
-----------
Reland: [GlobalISel] prevent G_UNMERGE_VALUES for vectors with different elements (#144661)
This commit prevents building a G_UNMERGE_VALUES instruction with
different source and destination vector elements in
`LegalizationArtifactCombiner::ArtifactValueFinder::tryCombineMergeLike()`,
e.g.:
`%1:_(<2 x s8>), %2:_(<2 x s8>) = G_UNMERGE_VALUES %0:_(<2 x s16>)`
This LLVM defect was identified via the AMD Fuzzing project.
Commit: c3efe7d64cebcd8679bec3ba7ff8154f8b0a1fa4
https://github.com/llvm/llvm-project/commit/c3efe7d64cebcd8679bec3ba7ff8154f8b0a1fa4
Author: Martin Storsjö <martin at martin.st>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M libcxx/test/libcxx/odr_signature.exceptions.sh.cpp
M libcxx/test/libcxx/odr_signature.hardening.sh.cpp
Log Message:
-----------
[libcxx] [test] Fix odr_signature tests with optimizations enabled (#144317)
If optimization is enabled, the inline `f()` function actually gets
inlined, meaning that the functions `tu1()` and `tu2()` trivially return
1 and 2, instead of actually referencing the potentially linker
deduplicated function `f()`, which is what the test tries to test.
Therefore, this test previously actually failed to test what it was
supposed to test, if optimization was enabled.
Mark the inline functions with `TEST_NOINLINE` to make sure that they
don't get inlined even with optimizations enabled.
Also update the TODO comments to explain why we have an XFAIL for msvc
mode here.
This avoids these tests unexpectedly passing if building in msvc mode,
with optimizations enabled
(`-DLIBCXX_TEST_PARAMS="optimization=speed"`).
Commit: 66d6964a55014e7fabb7c80fbba19d2145262b6b
https://github.com/llvm/llvm-project/commit/66d6964a55014e7fabb7c80fbba19d2145262b6b
Author: Garvit Gupta <quic_garvgupt at quicinc.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/test/Driver/aarch64-toolchain-extra.c
M clang/test/Driver/aarch64-toolchain.c
M clang/test/Driver/arm-toolchain-extra.c
M clang/test/Driver/arm-toolchain.c
Log Message:
-----------
Fix tests failing on fuchsia clang x86_64 builders (#144655)
Fuchsia sets CLANG_DEFAULT_UNWINDLIB to libunwind. As a result, when
rtlib is set to libgcc and unwindlib is not explicitly specified, tests
using Fuchsia as the default platform will fail. To address this, the
affected tests are now xfailed
This change fixes the following tests introduced in
https://github.com/llvm/llvm-project/commit/45ea46c44636094e9fcdbbeabfd11f9d0fad5e38:
clang/test/Driver/aarch64-toolchain-extra.c
clang/test/Driver/arm-toolchain-extra.c
clang/test/Driver/aarch64-toolchain.c
clang/test/Driver/arm-toolchain.c
Commit: 8a469da8b2342dd9104faf25deeddd8ad66ca6a6
https://github.com/llvm/llvm-project/commit/8a469da8b2342dd9104faf25deeddd8ad66ca6a6
Author: Oleksandr "Alex" Zinenko <git at ozinenko.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/lib/Dialect/MemRef/Transforms/ExpandOps.cpp
M mlir/test/Dialect/MemRef/expand-ops.mlir
Log Message:
-----------
[mlir] remove unnecessary atomic_rmw expansions (#144515)
The expansion of `memref.atomic_rmw` into a `memref.generic_atomic_rmw`
for floating-point min/max operations is no longer necessary as those
are now supported by the LLVM dialect and LLVM IR.
Furthermore, combining this expansion with direct lowering of
`generic_atomic_rmw` could leads to invalid LLVM dialect IR with
`cmpxchg` operating on floating-point values that it does not support.
Commit: d8e8ab79773f739c602c5869f80c6c5b5962c558
https://github.com/llvm/llvm-project/commit/d8e8ab79773f739c602c5869f80c6c5b5962c558
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/test/CodeGen/AArch64/stack-hazard.ll
Log Message:
-----------
[AArch64][SME] Fix restoring callee-saves from FP with hazard padding (#143371)
Currently, when hazard-padding is enabled a (fixed-size) hazard slot is
placed in the CS area, just after the frame record. The size of this
slot is part of the "CalleeSaveBaseToFrameRecordOffset". The SVE
epilogue emission code assumed this offset was always zero, and
incorrectly setting the stack pointer, resulting in all SVE registers
being reloaded from incorrect offsets.
```
| prev_lr |
| prev_fp |
| (a.k.a. "frame record") |
|-----------------------------------| <- fp(=x29)
| <hazard padding> |
|-----------------------------------| <- callee-saved base
| |
| callee-saved fp/simd/SVE regs |
| |
|-----------------------------------| <- SVE callee-save base
```
i.e. in the above diagram, the code assumed `fp == callee-saved base`.
Commit: 34a48941498d95ec2682f7adaeb6115b7b4d70ba
https://github.com/llvm/llvm-project/commit/34a48941498d95ec2682f7adaeb6115b7b4d70ba
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] detectZextAbsDiff - use SDPatternMatch::m_Abs() matcher. NFC.
Commit: 7c15edb306932e41c159f3d69c161ed0d89d47b7
https://github.com/llvm/llvm-project/commit/7c15edb306932e41c159f3d69c161ed0d89d47b7
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Descriptor.cpp
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/Floating.h
M clang/lib/AST/ByteCode/Integral.h
M clang/lib/AST/ByteCode/IntegralAP.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
M clang/lib/AST/ByteCode/InterpState.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ByteCode/PrimType.h
M clang/lib/AST/ByteCode/Program.h
M clang/test/AST/ByteCode/builtin-bit-cast-long-double.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
Log Message:
-----------
Reapply "[clang][bytecode] Allocate IntegralAP and Floating types usi… (#144676)
…ng an allocator (#144246)"
This reverts commit 57828fec760f086b334ce0cb1c465fc559dcaea4.
Commit: 6265ca686dfe18e6032e59637f144bad7ea6cf2b
https://github.com/llvm/llvm-project/commit/6265ca686dfe18e6032e59637f144bad7ea6cf2b
Author: Ties Stuij <ties.stuij at arm.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64.td
M llvm/lib/Target/AArch64/AArch64Processors.td
A llvm/lib/Target/AArch64/AArch64SchedA320.td
A llvm/test/tools/llvm-mca/AArch64/Cortex/A320-basic-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Cortex/A320-neon-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Cortex/A320-sve-instructions.s
Log Message:
-----------
[AArch64] Add Cortex-A320 scheduling model (#144385)
Instead of using the Cortex-A510 scheduling model, Cortex-A320 now uses
its own scheduling model, based off of the Cortex-A320 Software
Optimization Guide:
https://developer.arm.com/documentation/110285/r0p1
---------
Co-authored-by: Nashe Mncube <Nashe.Mncube at arm.com>
Commit: a1c2a712939897251729b6fc436a2db7db6f03fc
https://github.com/llvm/llvm-project/commit/a1c2a712939897251729b6fc436a2db7db6f03fc
Author: Andrei Golubev <andrey.golubev at intel.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparsificationAndBufferizationPass.cpp
Log Message:
-----------
[mlir][bufferization] Use Type instead of Value in unknown conversion (#144658)
Generally, bufferization should be able to create a memref from a tensor
without needing to know more than just a mlir::Type. Thus, change
BufferizationOptions::UnknownTypeConverterFn to accept just a type
(mlir::TensorType for now) instead of mlir::Value. Additionally, apply
the same rationale to getMemRefType() helper function.
Both changes are prerequisites to enable custom types support in
one-shot bufferization.
Commit: 66580f77b826e71a9727f1d6287bec6a6101f620
https://github.com/llvm/llvm-project/commit/66580f77b826e71a9727f1d6287bec6a6101f620
Author: Matthias Springer <me at m-sp.org>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/lib/Transforms/Utils/DialectConversion.cpp
Log Message:
-----------
[mlir][Transforms][NFC] Dialect Conversion: Keep `unresolvedMaterializations` up to date (#144254)
`unresolvedMaterializations` is a mapping from
`UnrealizedConversionCastOp` to `UnresolvedMaterializationRewrite`. This
mapping is needed to find the correct type converter for an unresolved
materialization.
With this commit, `unresolvedMaterializations` is updated immediately
when an op is being erased. This also cleans up the code base a bit:
`SingleEraseRewriter` is now used only during the "cleanup" phase and no
longer needed as a field of `ConversionRewriterImpl`.
This commit is in preparation of the One-Shot Dialect Conversion
refactoring: `allowPatternRollback = false` will in the future trigger
immediate materialization of all IR changes.
Commit: 4b2ab1494bc07493087252dff4e5e19808703048
https://github.com/llvm/llvm-project/commit/4b2ab1494bc07493087252dff4e5e19808703048
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Lower/OpenMP/Todo/declare-mapper-iterator.f90
Log Message:
-----------
[flang][OpenMP] Don't crash on iterator modifier in declare mapper (#144359)
Both the declare mapper directive argument, and the iterator modifier
can contain declaration-type-spec, so make sure that the processing of
one ends before processing of the other begins in semantic analysis.
Commit: a83d3362f686725bac76bfb9562663908de25f15
https://github.com/llvm/llvm-project/commit/a83d3362f686725bac76bfb9562663908de25f15
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M flang/lib/Semantics/resolve-directives.cpp
R flang/test/Lower/OpenMP/Todo/omp-doconcurrent.f90
A flang/test/Semantics/OpenMP/do-concurrent-collapse.f90
Log Message:
-----------
[flang][OpenMP] Don't allow DO CONCURRENT inside of a loop nest (#144506)
I don't think DO CONCURRENT fits the definition of a Canonical Loop Nest
(OpenMP 6.0 section 6.4.1).
It is however explicitly allowed for the LOOP construct (6.0 section
13.8).
There's some obscure language in OpenMP 6.0 for the LOOP construct:
> If the collapsed loop is a DO CONCURRENT loop, neither the
> data-sharing attribute clauses nor the collapse clause may be
specified.
>From the surrounding context, I think "collapsed loop" just means the
loop that the LOOP construct applies to. So I will interpret this to
mean that DO CONCURRENT can only be used with the LOOP construct if it
does not contain the COLLAPSE clause.
This also fixes a bug where the associated clause was never cleared
after it was set.
Fixes #144178
Commit: 8584abb05a84d3bf4e84cdfe4154d7ade8bdfd04
https://github.com/llvm/llvm-project/commit/8584abb05a84d3bf4e84cdfe4154d7ade8bdfd04
Author: Frank Schlimbach <frank.schlimbach at intel.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
A mlir/test/Target/SPIRV/lit.local.cfg
R mlir/test/lit.local.cfg
Log Message:
-----------
[mlir] mlir/test/lit.local.cfg -> mlir/test/Target/SPIRV/lit.local.cfg (#144685)
renamed: mlir/test/lit.local.cfg -> mlir/test/Target/SPIRV/lit.local.cfg
Commit: 68471d29eed2c49f9b439e505b3f24d387d54f97
https://github.com/llvm/llvm-project/commit/68471d29eed2c49f9b439e505b3f24d387d54f97
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Descriptor.cpp
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/Floating.h
M clang/lib/AST/ByteCode/Integral.h
M clang/lib/AST/ByteCode/IntegralAP.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
M clang/lib/AST/ByteCode/InterpState.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ByteCode/PrimType.h
M clang/lib/AST/ByteCode/Program.h
M clang/test/AST/ByteCode/builtin-bit-cast-long-double.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
Log Message:
-----------
Revert "Reapply "[clang][bytecode] Allocate IntegralAP and Floating types usi… (#144676)"
This reverts commit 7c15edb306932e41c159f3d69c161ed0d89d47b7.
This still breaks clang-armv8-quick:
https://lab.llvm.org/buildbot/#/builders/154/builds/17587
Commit: 6729da647afa2b0ee040ccd4f06153e45d6ca738
https://github.com/llvm/llvm-project/commit/6729da647afa2b0ee040ccd4f06153e45d6ca738
Author: Kunwar Grover <groverkss at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.h
M mlir/lib/Dialect/AMDGPU/Transforms/EmulateAtomics.cpp
M mlir/lib/Dialect/AMDGPU/Transforms/ResolveStridedMetadata.cpp
M mlir/lib/Dialect/AMDGPU/Transforms/TransferReadToLoad.cpp
Log Message:
-----------
[mlir][amdgpu][nfc] Add PatternBenefit to populate methods (#144663)
Commit: c4d99704e22097703c57ee67baea96fdabfd68ab
https://github.com/llvm/llvm-project/commit/c4d99704e22097703c57ee67baea96fdabfd68ab
Author: Garvit Gupta <quic_garvgupt at quicinc.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/docs/Toolchain.rst
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/lib/Driver/ToolChains/BareMetal.cpp
M clang/lib/Driver/ToolChains/BareMetal.h
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/include/c++/8.2.1/.keep
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/lib/.keep
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/lib/crt0.o
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/bin/aarch64-none-elf-ld
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/crtbegin.o
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/crtend.o
R clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crt0.o
R clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crtbegin.o
R clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crtend.o
R clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/bin/aarch64-none-elf-ld
R clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/include/c++/8.2.1/.keep
R clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/lib/.keep
R clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/lib/crt0.o
R clang/test/Driver/Inputs/basic_arm_gcc_tree/bin/armv6m-none-eabi-ld
R clang/test/Driver/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/crtbegin.o
R clang/test/Driver/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/crtend.o
R clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crt0.o
R clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crtbegin.o
R clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crtend.o
R clang/test/Driver/Inputs/basic_arm_nogcc_tree/bin/armv6m-none-eabi-ld
R clang/test/Driver/aarch64-gnutools.c
R clang/test/Driver/aarch64-toolchain-extra.c
R clang/test/Driver/aarch64-toolchain.c
R clang/test/Driver/arm-gnutools.c
R clang/test/Driver/arm-toolchain-extra.c
R clang/test/Driver/arm-toolchain.c
M clang/test/Driver/baremetal.cpp
R clang/test/Driver/check-no-multlib-warning.c
Log Message:
-----------
Revert "Reland [Driver] Add support for GCC installation detection in… (#144684)
… Baremetal toolchain (#144640)"
This reverts commit 45ea46c44636094e9fcdbbeabfd11f9d0fad5e38.
Commit: 1f34d68c4f086e7ea6ef9a529f9606476b38bbbb
https://github.com/llvm/llvm-project/commit/1f34d68c4f086e7ea6ef9a529f9606476b38bbbb
Author: Tobias Stadler <mail at stadler-tobias.de>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/docs/CommandGuide/llvm-opt-report.rst
M llvm/docs/Remarks.rst
M llvm/include/llvm/Remarks/RemarkFormat.h
M llvm/include/llvm/Remarks/RemarkParser.h
M llvm/include/llvm/Remarks/YAMLRemarkSerializer.h
M llvm/lib/Remarks/BitstreamRemarkParser.cpp
M llvm/lib/Remarks/BitstreamRemarkParser.h
M llvm/lib/Remarks/RemarkFormat.cpp
M llvm/lib/Remarks/RemarkLinker.cpp
M llvm/lib/Remarks/RemarkParser.cpp
M llvm/lib/Remarks/RemarkSerializer.cpp
M llvm/lib/Remarks/RemarkStreamer.cpp
M llvm/lib/Remarks/YAMLRemarkParser.cpp
M llvm/lib/Remarks/YAMLRemarkParser.h
M llvm/lib/Remarks/YAMLRemarkSerializer.cpp
M llvm/test/CodeGen/X86/remarks-section.ll
M llvm/unittests/Remarks/RemarksLinkingTest.cpp
M llvm/unittests/Remarks/YAMLRemarksParsingTest.cpp
M llvm/unittests/Remarks/YAMLRemarksSerializerTest.cpp
Log Message:
-----------
[Remarks] Remove yaml-strtab format (#144527)
Background: The yaml-strtab format looks just like the yaml format,
except that the values in the key/value pairs of the remarks are
deduplicated and replaced by indices into a string table (see removed
test cases for examples). The motivation behind this format was to
reduce size of the remarks files. However, it was quickly superseded by
the bitstream format.
Therefore, remove the yaml-strtab format, as it doesn't have a good
usecase anymore:
- It isn't particularly efficient
- It isn't human-readable
- It isn't straightforward to parse in external tools that can't use the
remarks library. We don't even support it in opt-viewer.
llvm-remarkutil is also missing options to parse/convert yaml-strtab, so
the chance that anyone is actually using this format is low.
Commit: 671caef379c603d2bcc428a00e3535b230162941
https://github.com/llvm/llvm-project/commit/671caef379c603d2bcc428a00e3535b230162941
Author: Jack Styles <jack.styles at arm.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M flang/lib/Semantics/resolve-directives.cpp
M flang/test/Semantics/OpenMP/allocate-align01.f90
M flang/test/Semantics/OpenMP/allocate01.f90
M flang/test/Semantics/OpenMP/allocate02.f90
M flang/test/Semantics/OpenMP/allocate03.f90
M flang/test/Semantics/OpenMP/allocate05.f90
M flang/test/Semantics/OpenMP/allocate06.f90
M flang/test/Semantics/OpenMP/allocate09.f90
M flang/test/Semantics/OpenMP/clause-validity01.f90
M flang/test/Semantics/OpenMP/deprecation.f90
M flang/test/Semantics/OpenMP/flush02.f90
M flang/test/Semantics/OpenMP/nested-barrier.f90
M flang/test/Semantics/OpenMP/nested-master.f90
M flang/test/Semantics/OpenMP/nested-teams.f90
M flang/test/Semantics/OpenMP/ordered-simd.f90
M flang/test/Semantics/OpenMP/parallel-master-goto.f90
Log Message:
-----------
[Flang][OpenMP] Update relevant warnings to emit when OMP >= v5.2 (#144492)
There has been a number of deprecation warnings that have been added to
Flang, however these features are only deprecated when the OpenMP
Version being used is 5.2 or later. Previously, flang did not consider
the version with the warnings so would always be emitted.
Flang now ensures warnings are emitted for the appropriate version of
OpenMP, and tests are updated to reflect this change.
Commit: fda6b751f1b1356e65816f85fbc5b98e78337940
https://github.com/llvm/llvm-project/commit/fda6b751f1b1356e65816f85fbc5b98e78337940
Author: Eric Fiselier <eric at efcs.ca>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M .github/workflows/libcxx-restart-preempted-jobs.yaml
Log Message:
-----------
Fix libc++ restarter job.
A while ago, the test workflow was updated with a new preemption regex,
however it was only applied to the test job, and not the job
that's actually restarting the failed libc++ test runs.
This fix should correct the issue and get the restarter working
again.
Commit: bdac9580f3bc341ccbeeb743ecca656756f5aaec
https://github.com/llvm/llvm-project/commit/bdac9580f3bc341ccbeeb743ecca656756f5aaec
Author: Mircea Trofin <mtrofin at google.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/Transforms/Scalar/JumpThreading.h
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
Log Message:
-----------
[nfc][jt] Drop `std::optional` pointers (#144548)
The `std::optional` didn't add any semantics that couldn't be modeled with the pointers being `nullptr`.
Commit: c5613dc8635000bc0e8396b8156d5639195776ab
https://github.com/llvm/llvm-project/commit/c5613dc8635000bc0e8396b8156d5639195776ab
Author: lorenzo chelini <l.chelini at icloud.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
M mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
M mlir/test/Integration/GPU/CUDA/dump-ptx.mlir
Log Message:
-----------
[MLIR] Mark LLVM::FMAOp as legal (#144671)
Mark LLVM::FMAOp as legal in configureGpuToNVVMConversionLegality, since
we can handle intrinsic lowering in the NVPTX backend and emit
fma.rn.f32.
Commit: 1d6f1029f7e8cf5468309078da3e85201844b625
https://github.com/llvm/llvm-project/commit/1d6f1029f7e8cf5468309078da3e85201844b625
Author: Sergei Lebedev <185856+superbobry at users.noreply.github.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
Log Message:
-----------
[mlir] [python] Fixed the return type of `MemRefType.get_strides_and_offset` (#144523)
Previously, the return type for `offset` was `list[int]`, which clearly
is not right.
Commit: 9db7502d229b48817521429c2a5d3fb84543fdf9
https://github.com/llvm/llvm-project/commit/9db7502d229b48817521429c2a5d3fb84543fdf9
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M libcxx/include/__iterator/iterator_traits.h
Log Message:
-----------
[libc++] Move __has_iterator_typedefs to the up-to-C++17 implementation of iterator_traits (#144265)
`__has_iterator_typedefs` is only used in the up-to-C++17 implementation
of `type_traits`. To make that clearer the struct is moved into that
code block.
Commit: 40d2f392106f43a60eea79f433b47a5ce44fc4a4
https://github.com/llvm/llvm-project/commit/40d2f392106f43a60eea79f433b47a5ce44fc4a4
Author: Akira Hatanaka <ahatanak at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Sema/SemaObjC.h
M clang/lib/Sema/SemaCast.cpp
M clang/lib/Sema/SemaExprObjC.cpp
M clang/test/SemaObjCXX/arc-type-conversion.mm
Log Message:
-----------
[Sema][ObjC] Loosen restrictions on reinterpret_cast involving indirect ARC-managed pointers (#144458)
Allow using reinterpret_cast for conversions between indirect ARC
pointers and other pointer types.
rdar://152905399
Commit: ee070d08163ac09842d9bf0c1315f311df39faf1
https://github.com/llvm/llvm-project/commit/ee070d08163ac09842d9bf0c1315f311df39faf1
Author: Andrei Golubev <andrey.golubev at intel.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationOps.td
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationTypeInterfaces.h
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationTypeInterfaces.td
M mlir/include/mlir/Dialect/Bufferization/IR/UnstructuredControlFlow.h
M mlir/lib/Dialect/Arith/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationDialect.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
A mlir/lib/Dialect/Bufferization/IR/BufferizationTypeInterfaces.cpp
M mlir/lib/Dialect/Bufferization/IR/CMakeLists.txt
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
M mlir/lib/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Linalg/Transforms/ConvertToDestinationStyle.cpp
M mlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Shape/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseGPUCodegen.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorCodegen.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenUtils.cpp
M mlir/lib/Dialect/Tensor/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/test/Dialect/Bufferization/Transforms/one-shot-bufferize.mlir
M mlir/test/lib/Dialect/Test/TestOpDefs.cpp
M mlir/test/lib/Dialect/Test/TestOps.h
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/test/lib/Dialect/Test/TestTypeDefs.td
M mlir/test/lib/Dialect/Test/TestTypes.cpp
Log Message:
-----------
[mlir][bufferization] Support custom types (1/N) (#142986)
Following the addition of TensorLike and BufferLike type interfaces (see
00eaff3e9c897c263a879416d0f151d7ca7eeaff), introduce minimal changes
required to bufferize a custom tensor operation into a custom buffer
operation.
To achieve this, new interface methods are added to TensorLike type
interface that abstract away the differences between existing (tensor ->
memref) and custom conversions.
The scope of the changes is intentionally limited (for example,
BufferizableOpInterface is untouched) in order to first understand the
basics and reach consensus design-wise.
---
Notable changes:
* mlir::bufferization::getBufferType() returns BufferLikeType (instead
of BaseMemRefType)
* ToTensorOp / ToBufferOp operate on TensorLikeType / BufferLikeType.
Operation argument "memref" renamed to "buffer"
* ToTensorOp's tensor type inferring builder is dropped (users now need
to provide the tensor type explicitly)
Commit: 6f4add34801e6ce02a5ebc96df4d1ca479125649
https://github.com/llvm/llvm-project/commit/6f4add34801e6ce02a5ebc96df4d1ca479125649
Author: Omair Javaid <omair.javaid at linaro.org>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M compiler-rt/lib/fuzzer/tests/CMakeLists.txt
Log Message:
-----------
[compiler-rt] [Fuzzer] Fix ARMv7 test link failure by linking unwinder (#144495)
compiler-rt/lib/fuzzer/tests build was failing on armv7, with undefined
references to unwinder symbols, such as __aeabi_unwind_cpp_pr0.
This occurs because the test is built with `-nostdlib++` but `libunwind`
is not explicitly linked to the final test executable.
This patch resolves the issue by adding CMake logic to explicitly link
the required unwinder to the fuzzer tests, inspired by the same solution
used to fix Scudo build failures by https://reviews.llvm.org/D142888.
Commit: 36038a1048b2aab87ed18f982e960c044ad97670
https://github.com/llvm/llvm-project/commit/36038a1048b2aab87ed18f982e960c044ad97670
Author: Orlando Cazalet-Hyams <orlando.hyams at sony.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/CodeGen/FunctionLoweringInfo.h
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Log Message:
-----------
[RemoveDIs][NFC] Remove dbg intrinsic handling code from SelectionDAG ISel (#144702)
Commit: 8fc20bffabe7fe6cdc4a9ec1bc79202eba5f1f23
https://github.com/llvm/llvm-project/commit/8fc20bffabe7fe6cdc4a9ec1bc79202eba5f1f23
Author: Karlo Basioli <k.basioli at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
Fix bazel build issue caused by 142986 (#144721)
Commit: e4c3b037bc7f5d9a8089de4c509d3e6034735891
https://github.com/llvm/llvm-project/commit/e4c3b037bc7f5d9a8089de4c509d3e6034735891
Author: amordo <iammorjj at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
A llvm/test/Transforms/InstCombine/fmul-tan-cos.ll
Log Message:
-----------
[InstCombine] Fold `tan(x) * cos(x) => sin(x)` (#136319)
This patch enables folding `tan(x) * cos(x) -> sin(x)` under the `contract` flag.
Fixes https://github.com/llvm/llvm-project/issues/34950.
Commit: b53c1e4ee810ac21dab5d27413af1f31a6a4cbfa
https://github.com/llvm/llvm-project/commit/b53c1e4ee810ac21dab5d27413af1f31a6a4cbfa
Author: John Brawn <john.brawn at arm.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
A llvm/test/CodeGen/AArch64/vector-ldst-offset.ll
M llvm/test/CodeGen/AArch64/zext-to-tbl.ll
Log Message:
-----------
[AArch64] Add ISel for postindex ld1/st1 in big-endian (#144387)
When big-endian we need to use ld1/st1 for vector loads and stores so
that we get the elements in the correct order, but this prevents
postindex addressing from being used. Fix this by adding the appropriate
ISel patterns, plus the relevant changes in ISelLowering and
ISelDAGToDAG to cause postindex addressing to be used.
Commit: 3af4d4e8100fda2a7e1bd0dbbe0914b584ad08d6
https://github.com/llvm/llvm-project/commit/3af4d4e8100fda2a7e1bd0dbbe0914b584ad08d6
Author: Nathan Gauër <brioche at google.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/test/CodeGenHLSL/semantics/SV_Position.ps.hlsl
A llvm/test/CodeGen/SPIRV/linkage/link-attribute-vk.ll
Log Message:
-----------
[HLSL][SPIR-V] Fix LinkageAttribute emission for BuiltIn (#144701)
BuiltIn variables were missing the visibility attribute, which caused
the Linkage capability to be emitted by the backend.
Commit: 8b8a3699dbdbb5d7865b0fe330d972c3fa380f1e
https://github.com/llvm/llvm-project/commit/8b8a3699dbdbb5d7865b0fe330d972c3fa380f1e
Author: Graham Hunter <graham.hunter at arm.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/sve2p1-vector-shuffles.ll
Log Message:
-----------
[AArch64] Use dupq (SVE2.1) for segmented lane splats (#144482)
Use the dupq instructions (when available) to represent a splat of the
same lane within each 128b segment of a wider fixed vector.
Commit: 9da9d32670ddbf610f0788236e78b2382037f00b
https://github.com/llvm/llvm-project/commit/9da9d32670ddbf610f0788236e78b2382037f00b
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
A llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
Log Message:
-----------
[AMDGPU][True16][CodeGen] sext i16 inreg in true16 mode (#144024)
update sext pattern in true16, setting up proper vgpr16 reg use
Commit: 5d502aeddf2a5d93c3fd93103054261acf4d92f3
https://github.com/llvm/llvm-project/commit/5d502aeddf2a5d93c3fd93103054261acf4d92f3
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
M flang/test/Semantics/OpenMP/atomic-update-only.f90
M flang/test/Semantics/OpenMP/atomic03.f90
M flang/test/Semantics/OpenMP/atomic04.f90
Log Message:
-----------
[flang][OpenMP] Clarify confusing error message (#144707)
The message "The atomic variable x should occur exactly once among the
arguments of the top-level [...] operator" was intended to convey that
(1) an atomic variable should be an argument, and (2) it should be
exactly one of the arguments. However, the wording turned out to be
sowing confusion instead.
Rework the corresponding check, and emit an individual error message for
each problematic situation:
- "atomic variable cannot be a proper subexpression of an argument",
- "atomic variable should appear as an argument",
- "atomic variable should be exactly one of the arguments".
Fixes https://github.com/llvm/llvm-project/issues/144599
Commit: b5aaf9d988ff2dc652c86271b181bf0497eb97cb
https://github.com/llvm/llvm-project/commit/b5aaf9d988ff2dc652c86271b181bf0497eb97cb
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/test/Transforms/InstCombine/vp-reverse.ll
Log Message:
-----------
[InstCombine] Implement vp.reverse reordering/elimination through binop/unop (#143963)
This simply copies the structure of the vector.reverse patterns from
just above, and reimplements them for the vp.reverse intrinsics when the
mask is all ones and the EVLs exactly match.
Its unfortunate that we have three different ways to represent a reverse
(shuffle, vector.reverse, and vp.reverse) but I don't see an obvious way
to remove any them because the semantics are slightly different.
This significantly improves vectorization in TSVC_2's s112 and s1112
loops when using EVL tail folding.
Commit: 0fa373c77ded203eddb973c79244c75ee5957eaf
https://github.com/llvm/llvm-project/commit/0fa373c77ded203eddb973c79244c75ee5957eaf
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
A llvm/test/Transforms/LowerMatrixIntrinsics/phi.ll
M llvm/test/Transforms/LowerMatrixIntrinsics/propagate-backwards-unsupported.ll
Log Message:
-----------
[Matrix] Propagate shape information through PHI insts (#141681)
... and split them as we lower them, avoiding several shuffles in the
process.
Commit: a2cee05449636c8e0d630b2ccdc71f2d422227a9
https://github.com/llvm/llvm-project/commit/a2cee05449636c8e0d630b2ccdc71f2d422227a9
Author: Christopher Ferris <cferris1000 at users.noreply.github.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M compiler-rt/lib/scudo/standalone/chunk.h
M compiler-rt/lib/scudo/standalone/combined.h
M compiler-rt/lib/scudo/standalone/report.cpp
M compiler-rt/lib/scudo/standalone/report.h
Log Message:
-----------
[scudo] Make report pointers const. (#144624)
Mark as many of the reportXX functions that take pointers const. This
avoid the need to use const_cast when calling these functions on an
already const pointer.
Fix reportHeaderCorruption calls where an argument was passed into an
append call that didn't use them.
Commit: 13510c07364dc3ac30f34e73c98ac8dc75e7efc7
https://github.com/llvm/llvm-project/commit/13510c07364dc3ac30f34e73c98ac8dc75e7efc7
Author: Peng Liu <winner245 at hotmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M libcxx/docs/FeatureTestMacroTable.rst
M libcxx/include/list
M libcxx/include/version
M libcxx/test/std/containers/sequences/list/compare.pass.cpp
M libcxx/test/std/containers/sequences/list/compare.three_way.pass.cpp
M libcxx/test/std/containers/sequences/list/get_allocator.pass.cpp
M libcxx/test/std/containers/sequences/list/incomplete_type.pass.cpp
M libcxx/test/std/containers/sequences/list/iterators.pass.cpp
M libcxx/test/std/containers/sequences/list/list.capacity/empty.pass.cpp
M libcxx/test/std/containers/sequences/list/list.capacity/max_size.pass.cpp
M libcxx/test/std/containers/sequences/list/list.capacity/resize_size.pass.cpp
M libcxx/test/std/containers/sequences/list/list.capacity/resize_size_value.pass.cpp
M libcxx/test/std/containers/sequences/list/list.capacity/size.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/assign_copy.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/assign_initializer_list.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/assign_move.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/copy.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/copy_alloc.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/default.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/default_stack_alloc.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/from_range.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/initializer_list.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/initializer_list_alloc.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/input_iterator.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/move.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/move_alloc.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/op_equal_initializer_list.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/size_type.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/size_value_alloc.pass.cpp
M libcxx/test/std/containers/sequences/list/list.erasure/erase.pass.cpp
M libcxx/test/std/containers/sequences/list/list.erasure/erase_if.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/append_range.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/assign_range.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/clear.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/emplace.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/emplace_back.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/emplace_front.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/erase_iter.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/erase_iter_iter.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/insert_iter_initializer_list.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/insert_iter_iter_iter.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/insert_iter_rvalue.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/insert_iter_size_value.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/insert_iter_value.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/insert_range.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/pop_back.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/pop_front.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/prepend_range.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/push_back.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/push_back_rvalue.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/push_front.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/push_front_rvalue.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/merge.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/merge_comp.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/remove.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/remove_if.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/reverse.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/sort.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/sort_comp.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/splice_pos_list.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/splice_pos_list_iter.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/splice_pos_list_iter_iter.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/unique.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/unique_pred.pass.cpp
M libcxx/test/std/containers/sequences/list/list.special/swap.pass.cpp
M libcxx/test/std/containers/sequences/list/list.special/swap_noexcept.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/list.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
M libcxx/test/support/min_allocator.h
M libcxx/utils/generate_feature_test_macro_components.py
Log Message:
-----------
[libc++] Make list constexpr as part of P3372R3 (#129799)
This patch makes `std::list` constexpr as part of P3372R3.
Fixes #128659.
Commit: 6d785ca4218b18e77e39320bea7f8973c3ea2764
https://github.com/llvm/llvm-project/commit/6d785ca4218b18e77e39320bea7f8973c3ea2764
Author: Ying Yi <ying.yi at sony.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/test/PCH/ignored-pch.c
Log Message:
-----------
[Clang] Fix the clang/test/PCH/ignored-pch.c test. (#144737)
Change the test to check the exit status of the 'ls' command line
(instead of error message) since the error message is different when
running 'ls' command on the different Host machine.
Commit: 2a41350aabd8b7d3e406141a55ce0bb6f5e70a76
https://github.com/llvm/llvm-project/commit/2a41350aabd8b7d3e406141a55ce0bb6f5e70a76
Author: Karlo Basioli <k.basioli at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
Fix bazel build issue caused by #142986 second attempt (#144721 didnt… (#144743)
… cover everything)
Commit: dd40c460c42d075c47f0d1a6d83f129655eafe10
https://github.com/llvm/llvm-project/commit/dd40c460c42d075c47f0d1a6d83f129655eafe10
Author: Peng Liu <winner245 at hotmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M libcxx/include/forward_list
Log Message:
-----------
[libc++] Clean up casts in std::forward_list (#130310)
The patch removes unnecessary casts to `void*` pointers, inline some
casts, and eliminates an identity cast.
Commit: 9827440f1e723423baf4c235e844eb8ac48a8f97
https://github.com/llvm/llvm-project/commit/9827440f1e723423baf4c235e844eb8ac48a8f97
Author: Peng Liu <winner245 at hotmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M libcxx/docs/ReleaseNotes/21.rst
M libcxx/include/__algorithm/for_each.h
M libcxx/include/__algorithm/for_each_n.h
M libcxx/include/__algorithm/ranges_for_each.h
M libcxx/include/__algorithm/ranges_for_each_n.h
M libcxx/include/experimental/iterator
M libcxx/include/mutex
M libcxx/include/shared_mutex
M libcxx/test/benchmarks/algorithms/nonmodifying/for_each.bench.cpp
M libcxx/test/benchmarks/algorithms/nonmodifying/for_each_n.bench.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.foreach/ranges.for_each.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.foreach/ranges.for_each_n.pass.cpp
Log Message:
-----------
[libc++] Optimize ranges::{for_each, for_each_n} for segmented iterators (#132896)
Previously, the segmented iterator optimization was limited to `std::{for_each, for_each_n}`. This patch
extends the optimization to `std::ranges::for_each` and `std::ranges::for_each_n`, ensuring consistent
optimizations across these algorithms. This patch first generalizes the `std` algorithms by introducing
a `Projection` parameter, which is set to `__identity` for the `std` algorithms. Then we let the `ranges`
algorithms to directly call their `std` counterparts with a general `__proj` argument. Benchmarks
demonstrate performance improvements of up to 21.4x for ``std::deque::iterator`` and 22.3x for
``join_view`` of ``vector<vector<char>>``.
Addresses a subtask of #102817.
Commit: 00189211486d052b25429f11790ef5486cf9d3ce
https://github.com/llvm/llvm-project/commit/00189211486d052b25429f11790ef5486cf9d3ce
Author: woruyu <99597449+woruyu at users.noreply.github.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
A llvm/test/CodeGen/X86/fold-masked-merge-demorgan.ll
Log Message:
-----------
[DAG] add (~a | x) & (a | y) -> (a & (x ^ y)) ^y for foldMaskedMerge (#144342)
### Summary
This PR resolves https://github.com/llvm/llvm-project/issues/143864
Add (~a | x) & (a | y) -> (a & (x ^ y)) ^y for foldMaskedMerge func
using SDPatternMatch
aftering adding this pattern, run ```ninja check-llvm-codegen```, all
other cases remain unchanged, so I add a
testcase(fold-masked-merge-demorgan.ll) for it
---------
Co-authored-by: Simon Pilgrim <llvm-dev at redking.me.uk>
Commit: fe3933da15b5bc635bce156f1f8d11a784316a07
https://github.com/llvm/llvm-project/commit/fe3933da15b5bc635bce156f1f8d11a784316a07
Author: Yang Bai <baiyang0132 at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Affine/constant-fold.mlir
M mlir/test/Dialect/Linalg/mesh-spmdization.mlir
M mlir/test/Dialect/Mesh/spmdization.mlir
M mlir/test/Dialect/Tensor/mesh-spmdization.mlir
M mlir/test/Dialect/Tosa/constant_folding.mlir
M mlir/test/Dialect/Vector/constant-fold.mlir
A mlir/test/Dialect/Vector/single-fold.mlir
M mlir/test/Transforms/constant-fold-debuginfo.mlir
M mlir/test/Transforms/constant-fold.mlir
M mlir/test/lib/Transforms/CMakeLists.txt
R mlir/test/lib/Transforms/TestConstantFold.cpp
A mlir/test/lib/Transforms/TestSingleFold.cpp
M mlir/tools/mlir-opt/mlir-opt.cpp
Log Message:
-----------
[mlir][vector] Support complete folding in single pass for vector.insert/vector.extract (#142124)
### Description
This patch improves the folding efficiency of `vector.insert` and
`vector.extract` operations by not returning early after successfully
converting dynamic indices to static indices.
This PR also renames the test pass `TestConstantFold` to
`TestSingleFold` and adds comprehensive documentation explaining the
single-pass folding behavior.
### Motivation
Since the `OpBuilder::createOrFold` function only calls `fold` **once**,
the current `fold` methods of `vector.insert` and `vector.extract` may
leave the op in a state that can be folded further. For example,
consider the following un-folded IR:
```
%v1 = vector.insert %e1, %v0 [0] : f32 into vector<128xf32>
%c0 = arith.constant 0 : index
%e2 = vector.extract %v1[%c0] : f32 from vector<128xf32>
```
If we use `createOrFold` to create the `vector.extract` op, then the
result will be:
```
%v1 = vector.insert %e1, %v0 [127] : f32 into vector<128xf32>
%e2 = vector.extract %v1[0] : f32 from vector<128xf32>
```
But this is not the optimal result. `createOrFold` should have returned
`%e1`.
The reason is that the execution of fold returns immediately after
`extractInsertFoldConstantOp`, causing subsequent folding logics to be
skipped.
---------
Co-authored-by: Yang Bai <yangb at nvidia.com>
Commit: 4084ffcf1e69b962e864aa138bb54dabbcec912f
https://github.com/llvm/llvm-project/commit/4084ffcf1e69b962e864aa138bb54dabbcec912f
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M flang/include/flang/Semantics/dump-expr.h
M flang/lib/Semantics/dump-expr.cpp
Log Message:
-----------
[flang] Show types in DumpEvExpr (#143743)
When dumping evaluate::Expr, show type names which contain a lot of
useful information.
For example show
```
expr <Fortran::evaluate::SomeType> {
expr <Fortran::evaluate::SomeKind<Fortran::common::TypeCategory::Integer>> {
expr <Fortran::evaluate::Type<Fortran::common::TypeCategory::Integer, 4>> {
...
```
instead of
```
expr T {
expr T {
expr T {
...
```
Commit: 2a8c65e983b3f4e1c83d8028d354f7bacc149015
https://github.com/llvm/llvm-project/commit/2a8c65e983b3f4e1c83d8028d354f7bacc149015
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/CodeGen/MachineFunction.cpp
Log Message:
-----------
[CodeGen][NFC] Fix quadratic c-t for large jump tables
Deleting a basic block removes all references from jump tables, which
is O(n). When freeing a MachineFunction, all basic blocks are deleted
before the jump tables, causing O(n^2) runtime. Fix this by deallocating
the jump table first.
Test case generator:
import sys
n = int(sys.argv[1])
print("define void @f(i64 %c, ptr %p) {")
print(" switch i64 %c, label %d [")
for i in range(n):
print(f" i64 {i}, label %h{i}")
print(f" ]")
for i in range(n):
print(f'h{i}:')
print(f' store i64 {i*i}, ptr %p')
print(f' ret void')
print('d:')
print(' ret void')
print('}')
Improvement at 5000 entries:
Benchmark 1: ./llc.pre -filetype=obj -O0 <switch5k.bc
Time (mean ± σ): 49.7 ms ± 1.0 ms
Range (min … max): 48.0 ms … 52.1 ms 57 runs
Benchmark 2: ./llc.post -filetype=obj -O0 <switch5k.bc
Time (mean ± σ): 39.4 ms ± 0.8 ms
Range (min … max): 37.1 ms … 41.1 ms 72 runs
Summary
./llc.post -filetype=obj -O0 <switch5k.bc ran
1.26 ± 0.04 times faster than ./llc.pre -filetype=obj -O0 <switch5k.bc
Improvement at 20000 entries:
Benchmark 1: ./llc.pre -filetype=obj -O0 <switch20k.bc
Time (mean ± σ): 281.7 ms ± 1.0 ms
Range (min … max): 280.2 ms … 283.0 ms 10 runs
Benchmark 2: ./llc.post -filetype=obj -O0 <switch20k.bc
Time (mean ± σ): 123.9 ms ± 1.5 ms
Range (min … max): 121.4 ms … 129.2 ms 23 runs
Summary
./llc.post -filetype=obj -O0 <switch20k.bc ran
2.27 ± 0.03 times faster than ./llc.pre -filetype=obj -O0 <switch20k.bc
Pull Request: https://github.com/llvm/llvm-project/pull/144108
Commit: 77bc25485135b8a8cb2427910a8850fbc4e4be09
https://github.com/llvm/llvm-project/commit/77bc25485135b8a8cb2427910a8850fbc4e4be09
Author: John Brawn <john.brawn at arm.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
[AArch64] Fix build failure with -Werror (#144749)
PR#144387 caused buildbot failures with -Werror due to a comparison
between signed and unsigned types. Fix this with an explicit cast.
Commit: 298f1c276f4f9c18b25a79ffe6e619e89c5fbf7e
https://github.com/llvm/llvm-project/commit/298f1c276f4f9c18b25a79ffe6e619e89c5fbf7e
Author: Artem Belevich <tra at google.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/lib/Headers/__clang_cuda_intrinsics.h
Log Message:
-----------
Revert "Add missing intrinsics to cuda headers" (#144755)
Reverts llvm/llvm-project#143664
as it breaks CUDA compilation.
Commit: d9f7979a63ceac88727632ecfd522c073288b6c1
https://github.com/llvm/llvm-project/commit/d9f7979a63ceac88727632ecfd522c073288b6c1
Author: Justin King <jcking at google.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
A compiler-rt/test/sanitizer_common/TestCases/Linux/free_aligned_sized.c
A compiler-rt/test/sanitizer_common/TestCases/Linux/free_sized.c
Log Message:
-----------
sanitizer_common: add unsupported test for free_sized and free_aligned_sized from C23 (#144727)
Signed-off-by: Justin King <jcking at google.com>
Commit: 82acd8c377e9ed267195afdbde16eedebabc648c
https://github.com/llvm/llvm-project/commit/82acd8c377e9ed267195afdbde16eedebabc648c
Author: Lei Huang <lei at ca.ibm.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.h
M llvm/lib/Target/PowerPC/PPCInstrMMA.td
M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
M llvm/test/CodeGen/PowerPC/dmr-spill.ll
A llvm/test/CodeGen/PowerPC/dmrp-spill.ll
Log Message:
-----------
[PowerPC] Add code to spill and restore DMRp registers (#142443)
Commit: 835d3034fe96931cf907537b51b9cdd87b59d3ad
https://github.com/llvm/llvm-project/commit/835d3034fe96931cf907537b51b9cdd87b59d3ad
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
A llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmov-gpr32.ll
R llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmov.ll
Log Message:
-----------
[AArch64] improve zero-cycle regmov test (#143680)
- Add a `gpr32` suffix to test name to denote the specific register
class being checked
- Expand `-mtriple=arm64-apple-ios` to `-march=arm64` to broaden the
test context to the generic architecture, as the specific triple is not
required
- Port `bl` match to Linux too via the regex: `{{_?foo}}`
- Advance `-mcpu=cyclone` to the newer M series major `-mcpu=apple-m1`
- Use `-mcpu` so that `-mattr=-zcm` has a real effect
- Add a test that generic arm64 doesn't optimize for ZCM
- Distinguish 4 different assembly layouts: NOTCPU, CPU, NOTATTR, ATTR
- Fix broken test logic, for example: `; NOT: mov [[REG2:w[0-9]+]], w3`
matched `mov w1, w3` then `REG2` captured `w1` but then `; NOT: mov w1,
[[REG2]]` matched by prefix `mov, w1, w19` even though it should have
matched `mov w1, w1`. This change adds explicit matches for all of the
generated copies.
Commit: 6f4e4ea17745d1414519651eb4067ce14031ea93
https://github.com/llvm/llvm-project/commit/6f4e4ea17745d1414519651eb4067ce14031ea93
Author: sribee8 <sriya.pratipati at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M libc/src/__support/HashTable/CMakeLists.txt
M libc/src/__support/HashTable/randomness.h
M libc/src/__support/OSUtil/linux/CMakeLists.txt
A libc/src/__support/OSUtil/linux/getrandom.h
M libc/src/sys/random/linux/getrandom.cpp
Log Message:
-----------
[libc] Internal getrandom implementation (#144427)
Implemented an internal getrandom to avoid calls to the public one in
table.h
---------
Co-authored-by: Sriya Pratipati <sriyap at google.com>
Commit: dfe4d44d8de645d151d3483272c1c1f80c27ab31
https://github.com/llvm/llvm-project/commit/dfe4d44d8de645d151d3483272c1c1f80c27ab31
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
Log Message:
-----------
Revert "[VPlan] Remove unnecessary DomTreeUpdater flush (NFC)." (#144758)
This reverts commit 2e337349f436d75af112c081df5ec683871cbcc8.
Causes breakages internally, will post reproducer later.
Commit: 071a6feabd7aeec2c1239719f50f6912cf94d00a
https://github.com/llvm/llvm-project/commit/071a6feabd7aeec2c1239719f50f6912cf94d00a
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[TTI] Remove PPC hasActiveVectorLength impl, simplify interface (NFC). (#142310)
PPCTTIImpl defines hasActiveVectorLength and also getVPMemoryOpCost, but
they appear unused (i.e. no changes to tests).
Remove them, as they complicate the interface for hasActiveVectorLength.
This simplifies the only use in LV as now no placeholder values need to
be passed.
PR: https://github.com/llvm/llvm-project/pull/142310
Commit: 3f3526f36d23eac8d099e8e887a924c94000bbfa
https://github.com/llvm/llvm-project/commit/3f3526f36d23eac8d099e8e887a924c94000bbfa
Author: zhijian lin <zhijian at ca.ibm.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll
M llvm/test/CodeGen/PowerPC/all-atomics.ll
M llvm/test/CodeGen/PowerPC/loop-comment.ll
Log Message:
-----------
[NFC][PowerPC] pre-commit running the update_llc_test_checks.py for all-atomics.ll,loop-comment.ll etc (#144411)
Run the update_llc_test_checks.py for all-atomics.ll,loop-comment.ll
,PR35812-neg-cmpxchg.ll (Pre-commit patch for the
https://github.com/llvm/llvm-project/pull/144089)
Commit: 17f5b8b52a3552de1143efb42af6a94d47d8c7fd
https://github.com/llvm/llvm-project/commit/17f5b8b52a3552de1143efb42af6a94d47d8c7fd
Author: Andre Kuhlenschmidt <andre.kuhlenschmidt at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M flang/include/flang/Support/Fortran-features.h
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Support/Fortran-features.cpp
Log Message:
-----------
[flang][driver] add ability to look up feature flags without setting them (#144559)
This just adds some convenience methods to feature control and rewrites
old code in terms of those methods. Also cleans up some names that I
just realize were overloads of another method.
Commit: 8c3fbaf0ee7322e948403d2234a7230bd6137c98
https://github.com/llvm/llvm-project/commit/8c3fbaf0ee7322e948403d2234a7230bd6137c98
Author: Walter J.T.V <81811777+eZWALT at users.noreply.github.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/include/clang/AST/StmtOpenMP.h
M clang/lib/AST/StmtOpenMP.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
Log Message:
-----------
[Clang][OpenMP][LoopTransformations] Fix incorrect number of generated loops for Tile and Reverse directives (#140532)
This patch is closely related to #139293 and addresses an existing issue
in the loop transformation codebase. Specifically, it corrects the
handling of the `NumGeneratedLoops` variable in
`OMPLoopTransformationDirective` AST nodes and its inheritors (such as
OMPUnrollDirective, OMPTileDirective, etc.).
Previously, this variable was inaccurately set for certain
transformations like reverse or tile. While this did not lead to
functional bugs, since the value was only checked to determine whether
it was greater than zero or equal to zero, the inconsistency could
introduce problems when supporting more complex directives in the
future.
Commit: ab6beeca9ccc1968661eea27c1a55e8734f7437b
https://github.com/llvm/llvm-project/commit/ab6beeca9ccc1968661eea27c1a55e8734f7437b
Author: uthmanna <114300283+uthmanna at users.noreply.github.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
M llvm/tools/llvm-cov/CoverageExporterJson.cpp
Log Message:
-----------
[llvm-cov] Export decision coverage to output json (#144335)
This commit adds decision coverage counts derived from MC/DC test vector execution to the JSON output of llvm-cov, as
discussed here: [Missing Decision Coverage (DC) in output
json](https://discourse.llvm.org/t/missing-decision-coverage-dc-in-output-json/86783)
with @evodius96
---------
Co-authored-by: uthmanna <andre.uthmann at vector.com>
Commit: ca9a09dbe679dbdd4d47cb7894977e04c3bb914e
https://github.com/llvm/llvm-project/commit/ca9a09dbe679dbdd4d47cb7894977e04c3bb914e
Author: Kazu Hirata <kazu at google.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M libcxx/docs/ABIGuarantees.rst
Log Message:
-----------
[libc++] Fix a typo in documentation (#144763)
Commit: a94eb27a29ef3aee5ccafc1d7bebee1c8efbaf38
https://github.com/llvm/llvm-project/commit/a94eb27a29ef3aee5ccafc1d7bebee1c8efbaf38
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Analysis/HashRecognize.cpp
M llvm/test/Analysis/HashRecognize/cyclic-redundancy-check.ll
Log Message:
-----------
[HashRecognize] Fix big-endian CRC tables (#144754)
Big-endian CRC tables are incorrect due to the initial value of CRC in
genSarwateTable being hard-coded for CRC-8. 128 is the signed-min value
for CRC-8, but it should be generalized to APInt::getSignedMinValue. The
issue was found when writing CRC verification tests for llvm-test-suite.
Commit: f13b9e3643661ea2cda252c7e2c59ace036407c7
https://github.com/llvm/llvm-project/commit/f13b9e3643661ea2cda252c7e2c59ace036407c7
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/Analysis/HashRecognize.h
M llvm/lib/Analysis/HashRecognize.cpp
Log Message:
-----------
[HashRecognize] Don't const-qualify Values in result (#144752)
Const-qualifying Values in the analysis result makes them unusable with
IRBuilder. The issue was discovered when attempting to use the result of
the analysis for a transform.
Commit: 156a64c585faf0870936b62ec85fae19ceb9ad3f
https://github.com/llvm/llvm-project/commit/156a64c585faf0870936b62ec85fae19ceb9ad3f
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Analysis/HashRecognize.cpp
M llvm/test/Analysis/HashRecognize/cyclic-redundancy-check.ll
Log Message:
-----------
[HashRecognize] Tighten pre-conditions for analysis (#144757)
Exit early if the TC is not a byte-multiple, as optimization works by
dividing TC by 8. Also delay the SCEV TC query.
Commit: 88d250729eb00842a41c946632bcacf1af106f64
https://github.com/llvm/llvm-project/commit/88d250729eb00842a41c946632bcacf1af106f64
Author: Alan Phipps <a-phipps at ti.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
M llvm/tools/llvm-cov/CoverageExporterJson.cpp
Log Message:
-----------
Revert "[llvm-cov] Export decision coverage to output json" (#144783)
Reverts llvm/llvm-project#144335
Need to resolve test failures
Commit: fb0651959b1b6ae64f84cf5840adc95923af991f
https://github.com/llvm/llvm-project/commit/fb0651959b1b6ae64f84cf5840adc95923af991f
Author: Jameson Nash <vtjnash at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/trampoline.ll
Log Message:
-----------
[AArch64] fix trampoline implementation: actually use X15 (#143892)
A incorrect switch statement caused it to try to use X4 instead of X15
in #126743, which would have not worked.
Commit: c04fc5596ec8c197c75b92a086c31438bfb08faf
https://github.com/llvm/llvm-project/commit/c04fc5596ec8c197c75b92a086c31438bfb08faf
Author: Jameson Nash <vtjnash at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
M llvm/test/Transforms/MemCpyOpt/memcpy-memcpy-offset.ll
M llvm/test/Transforms/MemCpyOpt/variable-sized-memcpy-memcpy.ll
Log Message:
-----------
[MemCpyOpt] allow some undef contents overread in processMemCpyMemCpyDependence (#143745)
Allows memcpy to memcpy forwarding in cases where the second memcpy is
larger, but the overread is known to be undef, by shrinking the memcpy
size.
Refs https://github.com/llvm/llvm-project/pull/140954 which laid some of
the groundwork for this.
Commit: 67c52aacae2aa698eb1d31d81d2376bd77723d3a
https://github.com/llvm/llvm-project/commit/67c52aacae2aa698eb1d31d81d2376bd77723d3a
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/test/CIR/CodeGen/struct.c
Log Message:
-----------
[CIR] Upstream support for IncompleteArrayType (#144138)
This change adds the basic support for IncompleteArray
Issue https://github.com/llvm/llvm-project/issues/130197
Commit: d4b7c0d8b437f50ea254d814a1aeecf87a17be91
https://github.com/llvm/llvm-project/commit/d4b7c0d8b437f50ea254d814a1aeecf87a17be91
Author: Tobias Stadler <mail at stadler-tobias.de>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/Remarks/RemarkFormat.h
M llvm/include/llvm/Remarks/RemarkLinker.h
M llvm/lib/Remarks/RemarkFormat.cpp
M llvm/lib/Remarks/RemarkLinker.cpp
M llvm/lib/Remarks/RemarkParser.cpp
M llvm/lib/Remarks/RemarkSerializer.cpp
A llvm/test/tools/llvm-remarkutil/Inputs/broken-remark-magic.bitstream
M llvm/test/tools/llvm-remarkutil/annotation-count.test
A llvm/test/tools/llvm-remarkutil/broken-bitstream-remark-magic.test
M llvm/test/tools/llvm-remarkutil/empty-file.test
M llvm/test/tools/llvm-remarkutil/instruction-count.test
M llvm/test/tools/llvm-remarkutil/instruction-mix.test
M llvm/test/tools/llvm-remarkutil/size-diff/no-difference.test
M llvm/tools/llvm-remarkutil/RemarkUtilHelpers.h
M llvm/unittests/Remarks/RemarksLinkingTest.cpp
Log Message:
-----------
[Remarks] Auto-detect remark parser format (#144554)
Add remark format 'Auto', which performs automatic detection of the
remark format using the magic numbers at the beginning of the remarks
files.
The RemarkLinker already did something similar, so we streamlined this
and exposed this to llvm-remarkutil.
Commit: 22a69a266d8206b1585dd82d466cd96d01725a65
https://github.com/llvm/llvm-project/commit/22a69a266d8206b1585dd82d466cd96d01725a65
Author: Justin King <jcking at google.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M compiler-rt/lib/lsan/lsan_allocator.cpp
M compiler-rt/lib/lsan/lsan_allocator.h
M compiler-rt/lib/lsan/lsan_interceptors.cpp
M compiler-rt/lib/lsan/lsan_malloc_mac.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_malloc_mac.inc
M compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
M compiler-rt/test/sanitizer_common/TestCases/Linux/free_aligned_sized.c
M compiler-rt/test/sanitizer_common/TestCases/Linux/free_sized.c
Log Message:
-----------
lsan: Support free_sized and free_aligned_sized from C23 (#144604)
Adds support to LSan for `free_sized` and `free_aligned_sized` from C23.
Other sanitizers will be handled with their own separate PRs.
For https://github.com/llvm/llvm-project/issues/144435
This is attempt number 2.
Signed-off-by: Justin King <jcking at google.com>
Commit: 23b8f11b27f1345cfdd9d03c9ebaccaf81897764
https://github.com/llvm/llvm-project/commit/23b8f11b27f1345cfdd9d03c9ebaccaf81897764
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Remove redundant VPWidenRecipe constructors (NFC)
Since the removal of VPWidenEVLRecipe, the constructors taking a
VPDefOpcode are not needed any more. Remove them.
Commit: a630ca6f6c4727d852d60076d1179c3e9830ca2f
https://github.com/llvm/llvm-project/commit/a630ca6f6c4727d852d60076d1179c3e9830ca2f
Author: Chelsea Cassanova <chelsea_cassanova at apple.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M lldb/include/lldb/Core/Debugger.h
M lldb/source/Breakpoint/Breakpoint.cpp
M lldb/source/Core/CoreProperties.td
M lldb/source/Core/Debugger.cpp
A lldb/test/API/terminal/TestDisabledBreakpoints.py
Log Message:
-----------
[lldb][breakpoint] Grey out disabled breakpoints (#91404)
This commit adds colour settings to the list of breakpoints in order to
grey out breakpoints that have been disabled.
Commit: a88e655809655eec8fa85366318fb3c4a0baa113
https://github.com/llvm/llvm-project/commit/a88e655809655eec8fa85366318fb3c4a0baa113
Author: Andrew Rogers <andrurogerz at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Support/BLAKE3/CMakeLists.txt
Log Message:
-----------
[llvm] build Blake3 source with LLVM_EXPORTS defined (#144753)
## Purpose
This patch ensures that the BLAKE3 implementation in the LLVM Support
library exports its public interface with `__declspec(dllexport)` when
building LLVM as a Windows DLL.
## Background
The effort to support building LLVM as a Windows DLL is tracked in
#109483. Additional context is provided in [this
discourse](https://discourse.llvm.org/t/psa-annotating-llvm-public-interface/85307).
## Overview
Replicate [this
logic](https://github.com/llvm/llvm-project/blob/main/llvm/cmake/modules/AddLLVM.cmake#L662-L664)
from `llvm_add_library()` for the `LLVMSupportBlake3` target. Without
this change, the `llvm_blake_` functions will only be annotated with
`__declspec(dllimport)` when building LLVM as a Windows DLL which leads
to inconsistent DLL linkage warnings from MSVC and `clang-cl`.
Commit: 96bbe472ef01e5f34bfeabedceea397889ff1119
https://github.com/llvm/llvm-project/commit/96bbe472ef01e5f34bfeabedceea397889ff1119
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
M mlir/test/CMakeLists.txt
M mlir/test/Target/SPIRV/constant.mlir
R mlir/test/Target/SPIRV/lit.local.cfg
M mlir/test/lit.cfg.py
M mlir/test/lit.site.cfg.py.in
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
Revert "[mlir][spirv] Fix int type declaration duplication when serializing" and follow up commits (#144773)
This reverts the following PRs:
* https://github.com/llvm/llvm-project/pull/143108
* https://github.com/llvm/llvm-project/pull/144538
* https://github.com/llvm/llvm-project/pull/144685
Reverting because this disabled tests when building without the llvm
spirv backend enabled.
Commit: b85e92990fdec32ec7512dec7bd36d945f8e0144
https://github.com/llvm/llvm-project/commit/b85e92990fdec32ec7512dec7bd36d945f8e0144
Author: Alexey Karyakin <akaryaki at quicinc.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/BinaryFormat/ELF.h
Log Message:
-----------
Hexagon v87 v89 elf flags (#144584)
Commit: 7aecd7ecacb4b305b94149f3cfcef306a9da6beb
https://github.com/llvm/llvm-project/commit/7aecd7ecacb4b305b94149f3cfcef306a9da6beb
Author: Diego Caballero <dieg0ca6aller0 at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/IR/OpBase.td
M mlir/lib/TableGen/Operator.cpp
M mlir/test/Dialect/Vector/invalid.mlir
M mlir/test/Dialect/Vector/ops.mlir
M mlir/tools/mlir-tblgen/OpFormatGen.cpp
Log Message:
-----------
[mlir][Vector] Add `vector.to_elements` op (#141457)
This PR introduces the `vector.to_elements` op, which decomposes a
vector into its scalar elements. This operation is symmetrical to the
existing `vector.from_elements`.
Examples:
```
// Decompose a 0-D vector.
%0 = vector.to_elements %v0 : vector<f32>
// %0 = %v0[0]
// Decompose a 1-D vector.
%0:2 = vector.to_elements %v1 : vector<2xf32>
// %0#0 = %v1[0]
// %0#1 = %v1[1]
// Decompose a 2-D.
%0:6 = vector.to_elements %v2 : vector<2x3xf32>
// %0#0 = %v2[0, 0]
// %0#1 = %v2[0, 1]
// %0#2 = %v2[0, 2]
// %0#3 = %v2[1, 0]
// %0#4 = %v2[1, 1]
// %0#5 = %v2[1, 2]
```
This op is aimed at reducing code size when modeling "structured" vector
extractions and simplifying canonicalizations of large sequences of
`vector.extract` and `vector.insert` ops into `vector.shuffle` and other
sophisticated ops that can re-arrange vector elements.
Commit: 86d1d6b2c0c1f03e82cb8e360f2672c6f0ea39d5
https://github.com/llvm/llvm-project/commit/86d1d6b2c0c1f03e82cb8e360f2672c6f0ea39d5
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/TargetInfo.cpp
M clang/lib/CodeGen/TargetInfo.h
M clang/lib/CodeGen/Targets/AMDGPU.cpp
M clang/lib/CodeGen/Targets/NVPTX.cpp
M clang/lib/CodeGen/Targets/SPIR.cpp
Log Message:
-----------
[clang] Use TargetInfo to determine device kernel calling convention (#144728)
We should abstract this logic away to `TargetInfo`. See
https://github.com/llvm/llvm-project/pull/137882 for more information.
---------
Signed-off-by: Sarnie, Nick <nick.sarnie at intel.com>
Commit: 03bdc0a1f68adcddef80a4e7931dbfae914e5652
https://github.com/llvm/llvm-project/commit/03bdc0a1f68adcddef80a4e7931dbfae914e5652
Author: Chelsea Cassanova <chelsea_cassanova at apple.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M lldb/source/Target/Target.cpp
M lldb/test/API/functionalities/progress_reporting/TestProgressReporting.py
Log Message:
-----------
[lldb][target] Add progress report for wait-attaching to process (#144768)
This commit adds a progress report when wait-attaching to a process as
well as a test for this.
Commit: 4dca4459a328b8d589d81cd1f203b798c36ebf35
https://github.com/llvm/llvm-project/commit/4dca4459a328b8d589d81cd1f203b798c36ebf35
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp
M clang/lib/CIR/CodeGen/CIRGenValue.h
M clang/test/CIR/CodeGen/complex.cpp
Log Message:
-----------
[CIR] Upstream ComplexType builtin_complex (#144225)
This change adds support for builtin_complex
https://github.com/llvm/llvm-project/issues/141365
Commit: ac37a0df949afc31d12de75f85306db32dd50713
https://github.com/llvm/llvm-project/commit/ac37a0df949afc31d12de75f85306db32dd50713
Author: Diego Caballero <dieg0ca6aller0 at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/include/mlir/IR/OpBase.td
Log Message:
-----------
[mlir] Fix integer comparison warning (#144794)
Introduced by https://github.com/llvm/llvm-project/pull/141457
Commit: d10079e305acae58b44dc773cb94f7127de197ef
https://github.com/llvm/llvm-project/commit/d10079e305acae58b44dc773cb94f7127de197ef
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
Log Message:
-----------
[RISCV] Reduce the VL of both operands in VMERGE_VVM (#144759)
The `tryToReduceVL` function in RISCVVectorPeephole currently only
reduces the VL of the instruction that defines the true operand in
VMERGE_VVM. We should be able to reduce VL of both operands. This patch
generalizes this function to support multiple operands from a single
instruction.
Commit: c4d7ea8049688a1d6d6d93129893fd1700a9f7e5
https://github.com/llvm/llvm-project/commit/c4d7ea8049688a1d6d6d93129893fd1700a9f7e5
Author: Javier Lopez-Gomez <javier.lopez.gomez at proton.me>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/DebugInfo/LogicalView/Core/LVElement.h
M llvm/include/llvm/DebugInfo/LogicalView/Core/LVScope.h
M llvm/include/llvm/DebugInfo/LogicalView/Core/LVSupport.h
Log Message:
-----------
[llvm-debuginfo-analyzer] Apply various memory savings in Core/LVxxx base classes (#144399)
This small changelist reduces memory footprint of instances of the Core
classes. Specifically,
- For `LVProperties`, use underlying type of `uint32_t` if there are at
most 32 properties to keep track of. Otherwise, fallback to the generic
`std::bitset<N>`.
The use of `llvm::SmallBitVector` is disregarded in this case, as the
upper bound on the size of the bitset can be determined statically (no
heap alloc ever needed).
- Reorder members in `LVElement` s.t. padding between members is
reduced.
- `LVScopeCompileUnit`: fix a couple of members which should be `static
constexpr` instead.
Commit: 51aa6a4993ea18c968a087352d1cf569c840c41f
https://github.com/llvm/llvm-project/commit/51aa6a4993ea18c968a087352d1cf569c840c41f
Author: Ebuka Ezike <yerimyah1 at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M lldb/test/API/tools/lldb-dap/memory/TestDAP_memory.py
M lldb/tools/lldb-dap/Handler/ReadMemoryRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
M lldb/unittests/DAP/ProtocolTypesTest.cpp
Log Message:
-----------
[lldb-dap] Use protocol types for ReadMemory request (#144552)
Read memory from process instead of target.
Commit: 118bfcda46c17349575217bc901e8e5942521955
https://github.com/llvm/llvm-project/commit/118bfcda46c17349575217bc901e8e5942521955
Author: Jianhui Li <jian.hui.li at intel.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
M mlir/test/Dialect/XeGPU/xegpu-blocking.mlir
M mlir/test/lib/Dialect/XeGPU/TestXeGPUTransforms.cpp
Log Message:
-----------
[MLIR][XEGPU] Add blocking support for scatter ops (#144766)
Add blocking support for scatter ops: Create_tdesc, update, prefetch,
load and store. It also enables the load/store with chunk size.
Commit: 7b6963ea672f8fedbbaefd15eaca943495709d37
https://github.com/llvm/llvm-project/commit/7b6963ea672f8fedbbaefd15eaca943495709d37
Author: Muhammad Omair Javaid <omair.javaid at linaro.org>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M compiler-rt/lib/fuzzer/tests/CMakeLists.txt
Log Message:
-----------
[compiler-rt] [Fuzzer] Fix tests linking buildbot failure (#144495)
Fix for #144495 by 6f4add3 broke sanitizer-aarch64-linux buildbot.
compiler-rt/lib/fuzzer/tests build failed because the linker was
looking gcc_s without '-l' appended.
The CMake script was adding the library name without the required
'-l' prefix. This patch adds the -l prefix changing gcc_s to -lgcc_s
and gcc to -lgcc.
https://lab.llvm.org/buildbot/#/builders/51/builds/18170
Commit: 00ae89a1cbece94412cf832e47fdf449a611ad24
https://github.com/llvm/llvm-project/commit/00ae89a1cbece94412cf832e47fdf449a611ad24
Author: zGoldthorpe <Zach.Goldthorpe at amd.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/include/llvm/Transforms/IPO/Attributor.h
M llvm/lib/Transforms/IPO/Attributor.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
R llvm/test/Transforms/Attributor/AMDGPU/tag-invariant-loads.ll
M llvm/test/Transforms/Attributor/dereferenceable-1.ll
M llvm/test/Transforms/Attributor/value-simplify-local-remote.ll
Log Message:
-----------
Revert "[IPO] Added attributor for identifying invariant loads" (#144808)
Reverts llvm/llvm-project#141800
The implementation critically misunderstands the `AAMemoryBehavior`
attributor, which it relies on heavily.
@shiltian, since I do not have commit permissions.
Commit: e0933ab5ae4856c4aa188a5ea16716b3a8d0840b
https://github.com/llvm/llvm-project/commit/e0933ab5ae4856c4aa188a5ea16716b3a8d0840b
Author: Chelsea Cassanova <chelsea_cassanova at apple.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M lldb/source/Target/Target.cpp
M lldb/test/API/functionalities/progress_reporting/TestProgressReporting.py
Log Message:
-----------
Revert "[lldb][target] Add progress report for wait-attaching to process" (#144810)
This is breaking TestCreateAfterAttach.py on Ubuntu:
```
======================================================================
FAIL: test_create_after_attach_dwo (TestCreateAfterAttach.CreateAfterAttachTestCase.test_create_after_attach_dwo)
Test thread creation after process attach.
----------------------------------------------------------------------
Traceback (most recent call last):
File "/home/buildbot/worker/as-builder-9/lldb-remote-linux-ubuntu/llvm-project/lldb/packages/Python/lldbsuite/test/lldbtest.py", line 1804, in test_method
return attrvalue(self)
^^^^^^^^^^^^^^^
File "/home/buildbot/worker/as-builder-9/lldb-remote-linux-ubuntu/llvm-project/lldb/packages/Python/lldbsuite/test/decorators.py", line 149, in wrapper
return func(*args, **kwargs)
^^^^^^^^^^^^^^^^^^^^^
File "/home/buildbot/worker/as-builder-9/lldb-remote-linux-ubuntu/llvm-project/lldb/test/API/functionalities/thread/create_after_attach/TestCreateAfterAttach.py", line 36, in test_create_after_attach
self.runCmd("process attach -p " + str(pid))
File "/home/buildbot/worker/as-builder-9/lldb-remote-linux-ubuntu/llvm-project/lldb/packages/Python/lldbsuite/test/lldbtest.py", line 1005, in runCmd
self.assertTrue(self.res.Succeeded(), msg + output)
AssertionError: False is not true : Command 'process attach -p 1474309' did not return successfully
Error output:
error: attach failed: lost connection
```
on the buildbots for lldb-remote-linux-ubuntu, lldb-arm-ubuntu,
lldb-aarch64-ubuntu, lldb-arm-ubuntu.
Commit: 780c0ef7fb97027aa21c2ee6b02282693f908a20
https://github.com/llvm/llvm-project/commit/780c0ef7fb97027aa21c2ee6b02282693f908a20
Author: Andrew Rogers <andrurogerz at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/tools/llvm-jitlink/llvm-jitlink-executor/CMakeLists.txt
Log Message:
-----------
[llvm] explicitly link llvm-jitlink-executor with ExecutionEngine (#144778)
## Overview
Explicitly link `llvm-jitlink-executor` with `ExecutionEngine` to avoid
link failures when building LLVM as a Windows DLL. This link dependency
should probably have always been declared here, but didn't matter when
building against an LLVM static library because it was (presumably)
picked up as a transitive dependency.
This change is required to enable the Windows DLL build because
`llvm-jitlink-executor` is declared using `add_llvm_utility` which
invokes `add_llvm_executable` with
[`DISABLE_LLVM_LINK_LLVM_DYLIB`](https://github.com/llvm/llvm-project/blob/main/llvm/cmake/modules/AddLLVM.cmake#L500-L502)
so it links statically against its dependencies instead of against the
main LLVM library.
## Background
The effort to support building LLVM as a Windows DLL is tracked in
#109483. Additional context is provided in [this
discourse](https://discourse.llvm.org/t/psa-annotating-llvm-public-interface/85307).
Commit: bb1f5c3189c4d8d30e3b1273e0b774a7ccdbd86a
https://github.com/llvm/llvm-project/commit/bb1f5c3189c4d8d30e3b1273e0b774a7ccdbd86a
Author: Guy David <49722543+guy-david at users.noreply.github.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/test/CodeGen/AArch64/min-jump-table.ll
Log Message:
-----------
[AArch64] Lower jump table cases threshold to 10 (#143632)
Previous stabs at this setting
(https://github.com/llvm/llvm-project/pull/71166) hypertuned it for
SPEC2017, but Clang's own compilation can benefit from a slightly lower
threshold, yielding a 0.3% improvement in compile time, while still not
regressing SPEC.
Most notable beneficiaries of this change are:
- `llvm::Instruction::getNumSuccessors` (11 cases)
- `llvm::Instruction::getSuccessor` (11 cases)
Test Suite with a bootstrapped build:
```
Tests: 4316
Metric: compile_time
Program compile_time
lhs rhs diff
SingleSour...ce/UnitTests/SignlessTypes/div 0.02 0.02 3.0%
SingleSour.../UnitTests/SignlessTypes/cast2 0.02 0.02 2.8%
SingleSource/Benchmarks/Misc/flops-4 0.02 0.02 1.9%
SingleSour...ebra/solvers/cholesky/cholesky 0.05 0.05 1.8%
SingleSour...tTests/2020-01-06-coverage-006 0.02 0.02 1.7%
SingleSour...ce/Benchmarks/Stanford/FloatMM 0.03 0.03 1.7%
SingleSour...9-04-16-BitfieldInitialization 0.02 0.02 1.7%
SingleSour...nitTests/2003-07-08-BitOpsTest 0.02 0.02 1.7%
MultiSourc...marks/Prolangs-C++/vcirc/vcirc 0.02 0.02 1.6%
MultiSourc...Prolangs-C/fixoutput/fixoutput 0.05 0.05 1.5%
SingleSour...h/stencils/jacobi-1d/jacobi-1d 0.04 0.04 1.4%
MultiSourc...rks/Prolangs-C++/office/office 0.28 0.28 1.4%
SingleSour...arks/Adobe-C++/functionobjects 0.39 0.40 1.3%
SingleSour...Tests/2003-10-29-ScalarReplBug 0.02 0.02 1.2%
SingleSour...arks/Adobe-C++/stepanov_vector 0.41 0.42 1.2%
Geomean difference -0.3%
compile_time
l/r lhs rhs diff
count 4316.000000 4316.000000 469.000000
mean 0.057747 0.057595 -0.003034
std 0.544528 0.543139 0.007625
min 0.000000 0.000000 -0.035294
25% 0.000000 0.000000 -0.007006
50% 0.000000 0.000000 -0.003257
75% 0.000000 0.000000 0.000000
max 18.295300 18.252500 0.030151
```
Commit: 5f69d680e2cc94dcb30a7f29e8144725530a6da4
https://github.com/llvm/llvm-project/commit/5f69d680e2cc94dcb30a7f29e8144725530a6da4
Author: Steven Perron <stevenperron at google.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaHLSL.cpp
R clang/test/AST/HLSL/vk.spec-constant.usage.hlsl
A clang/test/CodeGenHLSL/inline-spirv/SpirvType.alignment.hlsl
A clang/test/CodeGenHLSL/inline-spirv/SpirvType.hlsl
R clang/test/CodeGenHLSL/vk-features/SpirvType.alignment.hlsl
R clang/test/CodeGenHLSL/vk-features/SpirvType.hlsl
R clang/test/CodeGenHLSL/vk-features/vk.spec-constant.hlsl
R clang/test/SemaHLSL/vk.spec-constant.error.hlsl
Log Message:
-----------
Revert "[HLSL][SPIRV] Add vk::constant_id attribute." (#144812)
Reverts llvm/llvm-project#143544
Commit: d265105b8f50718a684d792d3ca957231d668533
https://github.com/llvm/llvm-project/commit/d265105b8f50718a684d792d3ca957231d668533
Author: David Justo <david.justo.1996 at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M compiler-rt/test/fuzzer/uncaught-exception.test
Log Message:
-----------
Augment `uncaught-exception.test` fuzzer test to be msvc-compatible (#125924)
Today, the `uncaught-exception.test` fuzzer test checks for the string
"libFuzzer: deadly signal" in the program output as the result of an
uncaught exception.
Although this is correct for `clang`, `msvc` reports a different error
message: "libFuzzer: uncaught C++ exception". Since `msvc` reuses the
`libFuzzer` infrastructure for ASan regression testing, it would help us
greatly if the test handled the `msvc` divergence more gracefully.
**This PR:** augments this test so check for a different string (namely
"libFuzzer: uncaught C++ exception") if the compiler target matches the
`msvc` naming scheme.
I understand if this is outside the scope of support for LLVM as well,
and I'm also open for different approaches here. Thanks!
Commit: bc8908a4e93b0641e1c17f408885c8aebb308bbe
https://github.com/llvm/llvm-project/commit/bc8908a4e93b0641e1c17f408885c8aebb308bbe
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Target/ARM/ARMISelLowering.h
Log Message:
-----------
ARM: Move declaration of supportSplitCSR to be public (#144679)
This is an implementation of a public method from the base
class, so it should also be public. Avoids unrelated diff
in a future patch.
Commit: 874a02f05b6ebb4b5dbe0ab09beb9c3d5b36e237
https://github.com/llvm/llvm-project/commit/874a02f05b6ebb4b5dbe0ab09beb9c3d5b36e237
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMAsmPrinter.h
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
Log Message:
-----------
ARM: Move ABI helpers from Subtarget to TargetMachine (#144680)
These are module level concepts, and attaching them to the
function level subtarget is confusing. Similarly these other
helpers that only operate on the triple should also be removed
from the subtarget.
Commit: 6e5ee4aa98f1dc16e6a75a7fd298a59f1edd1c6e
https://github.com/llvm/llvm-project/commit/6e5ee4aa98f1dc16e6a75a7fd298a59f1edd1c6e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVCallingConv.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/test/CodeGen/RISCV/interrupt-attr.ll
A llvm/test/CodeGen/RISCV/rvv/interrupt-attr-nocall.ll
Log Message:
-----------
[RISCV] Save vector registers in interrupt handler. (#143808)
Corresponding gcc bug report
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110665
The generated code is pretty awful.
Commit: 2bcdfa198aa511479c46144c5cf95c7c685384ef
https://github.com/llvm/llvm-project/commit/2bcdfa198aa511479c46144c5cf95c7c685384ef
Author: Sirui Mu <msrlancern at gmail.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/Interfaces/CIROpInterfaces.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenCall.h
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
M clang/test/CIR/CodeGen/call.c
M clang/test/CIR/IR/call.cir
Log Message:
-----------
[CIR] Add side effect attribute to call operations (#144201)
This patch adds `side_effect` attribute to `cir.call` operation.
Other function call attributes will be added in later patches.
Commit: faf9295f4e3a23a972d29e2be85052beef409d08
https://github.com/llvm/llvm-project/commit/faf9295f4e3a23a972d29e2be85052beef409d08
Author: MingYan <99472920+NexMing at users.noreply.github.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
Log Message:
-----------
[RISCV] Fix a bug where AVL is the last MI in MBB. (#144668)
When `AVL` is the last MI, `std::next(II)` equals `MBB.end()`, and
calling `II->getParent()` at that point will cause an error.
---------
Co-authored-by: yanming <ming.yan at terapines.com>
Commit: bfee625821c07d9a05b48e4a8b0f3d73c1233107
https://github.com/llvm/llvm-project/commit/bfee625821c07d9a05b48e4a8b0f3d73c1233107
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/IR/Verifier.cpp
A llvm/test/Verifier/NVPTX/fence-proxy.tensormap.ll
M llvm/test/Verifier/NVPTX/setmaxnreg.ll
Log Message:
-----------
[NVPTX] Attach Range attr to setmaxnreg and fence intrinsics (#144120)
This patch attaches the range attribute to the setmaxnreg
and fence.proxy.tensormap.* intrinsics. The range checks
are now handled generically in the Verifier. So, this patch
removes the per-intrinsic error-handling for range-checks
from the Verifier.
This patch also adds more coverage tests for these cases.
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: 5875fafdc547889fb089c943a881a9ab6d8a23c0
https://github.com/llvm/llvm-project/commit/5875fafdc547889fb089c943a881a9ab6d8a23c0
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/test/Preprocessor/predefined-arch-macros.c
M llvm/lib/Target/X86/X86.td
M llvm/lib/TargetParser/X86TargetParser.cpp
Log Message:
-----------
[X86] Remove CLDEMOTE from Alderlake and later hybrid processors (#144662)
SDM doesn't list any hybrid processors in this feature. Besides,
physical machine also reports not supported.
Commit: 351303c28e8feb85c93d8e9480f534653b032735
https://github.com/llvm/llvm-project/commit/351303c28e8feb85c93d8e9480f534653b032735
Author: Han-Chung Wang <hanhan0912 at gmail.com>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td
M mlir/include/mlir/IR/BuiltinOps.td
Log Message:
-----------
[mlir][docs] Fix broken links to Traits documentation. (#144820)
Commit: 7b989ade35a43357f9152198ee2c76899df9a56d
https://github.com/llvm/llvm-project/commit/7b989ade35a43357f9152198ee2c76899df9a56d
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2025-06-18 (Wed, 18 Jun 2025)
Changed paths:
M lldb/examples/python/crashlog.py
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/altered_threadState.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/json.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/no_threadState.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/skipped_status_interactive_crashlog.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/text.test
Log Message:
-----------
[lldb/crashlog] Make interactive mode the new default (#144839)
This patch makes interactive mode as the default when using the crashlog
command. It replaces the existing `-i|--interactive` flag with a new
`-m|--mode` option, that can either be `interactive` or `batch`.
By default, when the option is not explicitely set by the user, the
interactive mode is selected, however, lldb will fallback to batch mode
if the command interpreter is not interactive or if stdout is not a tty.
This also adds some railguards to prevent users from using interactive
only options with the batch mode and updates the tests accordingly.
rdar://97801509
Differential Revision: https://reviews.llvm.org/D141658
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: 590066bee70db37636311881c5b232464d6d4aec
https://github.com/llvm/llvm-project/commit/590066bee70db37636311881c5b232464d6d4aec
Author: Rajat Bajpai <rbajpai at nvidia.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/docs/NVPTXUsage.rst
M llvm/lib/Target/NVPTX/NVPTX.td
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/test/CodeGen/NVPTX/sm-version.ll
Log Message:
-----------
[NVPTX] Add family-specific architectures support (#141899)
This change adds family-specific architecture variants support added in [PTX ISA
8.8](https://docs.nvidia.com/cuda/parallel-thread-execution/#ptx-isa-version-8-8).
These architecture variants have "f" suffix. For example, sm_100f.
This change doesn't promote existing features to family-specific
architecture.
Commit: 03461c9c6e21e43a6e1c699bfb254ddb3d575c93
https://github.com/llvm/llvm-project/commit/03461c9c6e21e43a6e1c699bfb254ddb3d575c93
Author: Hsiangkai Wang <hsiangkai.wang at arm.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/lib/Conversion/GPUToSPIRV/GPUToSPIRV.cpp
M mlir/test/Conversion/GPUToSPIRV/shuffle.mlir
Log Message:
-----------
[mlir][gpu][spirv] Remove rotation semantics of gpu.shuffle up/down (#139105)
>From the description of gpu.shuffle operation, shuffle up/down rotates
values in the subgroup because it applies modulo on the shifted value to
calculate the result lane ID. It is inconsistent with the definition of
SPIR-V shuffle up/down and NVVM data movement definitions within
subgroup.
In NVVM, it says
"If the computed source lane index j is in range, the returned i32 value
will be the value of %a from lane j; otherwise, it will be the the value
of %a from the current thread."
It will keep the original value if the result land ID is out of range.
In SPIR-V OpGroupNonUniformShuffleUp and OpGroupNonUniformShuffleDown,
it says
"The resulting value is undefined if Delta is greater than the current
invocation’s id within the scope or if the identified invocation is not
in scope restricted tangle."
It's an undefined value if the result land ID is out of range.
Anyway, there is no circular movement in shuffle up/down from these 2
specifications. This patch removes the circular movement in gpu.shuffle
up/down and lower gpu.shuffle up/down to SPIR-V
OpGroupNonUniformShuffleUp and OpGroupNonUniformShuffleDown directly.
Reference:
https://docs.nvidia.com/cuda/archive/12.2.1/nvvm-ir-spec/index.html#data-movement
https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#OpGroupNonUniformShuffleUp
https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#OpGroupNonUniformShuffleDown
Commit: 2c2ad9a096e78e9129f8cb2d4ee260eb7e67473f
https://github.com/llvm/llvm-project/commit/2c2ad9a096e78e9129f8cb2d4ee260eb7e67473f
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/AST/StmtProfile.cpp
M clang/test/SemaCXX/exception-spec.cpp
M clang/test/SemaTemplate/concepts-out-of-line-def.cpp
Log Message:
-----------
Reapply "[Clang] Profile singly-resolved UnresolvedLookupExpr with the declaration" (#140680)
For a dependent variable template specialization, we don't build a
dependent Decl node or a DeclRefExpr to represent it. Instead, we
preserve the UnresolvedLookupExpr until instantiation.
However, this approach isn't ideal for constraint normalization. We
consider the qualifier during profiling, but since that's based on the
written code, it can introduce confusing differences, even when the
expressions resolve to the same declaration.
This change profiles the underlying VarTemplateDecl if
UnresolvedLookupExpr is used to model a dependent use of it.
Fixes https://github.com/llvm/llvm-project/issues/139476
Commit: 9ee55e717308757b580dff182fc23b40d1c18a56
https://github.com/llvm/llvm-project/commit/9ee55e717308757b580dff182fc23b40d1c18a56
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/lib/CIR/Dialect/Transforms/CIRSimplify.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
A clang/test/CIR/Transforms/vector-splat.cir
Log Message:
-----------
[CIR] Implement folder for VecSplatOp (#143771)
This change adds a folder for the VecSplatOp
Issue https://github.com/llvm/llvm-project/issues/136487
Commit: 408e55098d7d8f7064d7a288b5e3fe6fdbbc2ad4
https://github.com/llvm/llvm-project/commit/408e55098d7d8f7064d7a288b5e3fe6fdbbc2ad4
Author: quic_hchandel <quic_hchandel at quicinc.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/test/MC/RISCV/xqciac-valid.s
M llvm/utils/TableGen/CompressInstEmitter.cpp
Log Message:
-----------
[RISCV] Add support for handling one tied operand in the source instruction for compress patterns (#143660)
This update enables compress patterns to handle one tied operand in
source instructions, which was previously unsupported. Qualcomm's uC
extension Xqci includes several instructions with tied operands that can
be compressed into smaller forms. This change adds the necessary support
to enable such compression. Additionally, a compress pattern for the
qc.muliadd instruction has been implemented.
Commit: 3e795c60c73e990fbbf254715cb47855c32bcfae
https://github.com/llvm/llvm-project/commit/3e795c60c73e990fbbf254715cb47855c32bcfae
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M lldb/test/API/python_api/watchpoint/watchlocation/TestTargetWatchAddress.py
Log Message:
-----------
[lldb] Disable TestTargetWatchAddress on Windows x86_64 (#144779)
See #144777 for details.
Commit: a9a71b6d311892d6add6aab3790b20fe945cca38
https://github.com/llvm/llvm-project/commit/a9a71b6d311892d6add6aab3790b20fe945cca38
Author: S. B. Tam <cpplearner at outlook.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M libcxx/test/std/utilities/format/format.functions/escaped_output.unicode.pass.cpp
M libcxx/test/std/utilities/format/format.functions/fill.unicode.pass.cpp
Log Message:
-----------
[libc++][test] Don't pass ill-formed UTF-8 to MAKE_STRING_VIEW (#136403)
Commit: 50a7511138a42d2c7a69b68237ce88cc027b91bc
https://github.com/llvm/llvm-project/commit/50a7511138a42d2c7a69b68237ce88cc027b91bc
Author: Paschalis Mpeis <paschalis.mpeis at arm.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M bolt/test/AArch64/r_aarch64_prelxx.s
Log Message:
-----------
[BOLT][AArch64] Fix PREL Relocs on RHEL8 (#144505)
Commit: e73bff89ef8e3c8cdd8895cdc3d021fc4dcabd76
https://github.com/llvm/llvm-project/commit/e73bff89ef8e3c8cdd8895cdc3d021fc4dcabd76
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
Log Message:
-----------
[AMDGPU] New RegBankSelect: Handle all 32/64 bit pointer types for B32/B64 rule (#142560)
The previous system explicitly enumerated the types. P0 was missing and thus we couldn't handle a select of P0s for example.
Generalize the logic to simply check the width of the pointer for 32/64 bit pointers, this should handle all common address spaces
Commit: db8e6fc64534e986f5bf96cceaa76cc5007ac1c7
https://github.com/llvm/llvm-project/commit/db8e6fc64534e986f5bf96cceaa76cc5007ac1c7
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
Log Message:
-----------
[AMDGPU] New RegBanKSelect: Add S128 types (#142601)
Commit: 26d4b3cb4ca2f882384d940f3dad28f8d79451eb
https://github.com/llvm/llvm-project/commit/26d4b3cb4ca2f882384d940f3dad28f8d79451eb
Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/test/CodeGen/RISCV/xqcibm-extract.ll
Log Message:
-----------
[RISCV] Don't prefer QC_EXT for SEXT_INREG patterns when Zbb is enabled (#144837)
`Zbb` has the `sext.b` and `sext.h` instructions that are compressible.
Commit: 7ceea22a7adad5d21328839facbc6a6d0151e056
https://github.com/llvm/llvm-project/commit/7ceea22a7adad5d21328839facbc6a6d0151e056
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
Log Message:
-----------
[AMDGPU] New RegBankSelect: Add Ptr32/Ptr64/Ptr128 (#142602)
There's quite a few opcodes that do not care about the exact AS of the pointer, just its size.
Adding generic types for these will help reduce duplication in the rule definitions.
I also moved the usual B types to use the new `isAnyPtr` helper I added to make sure they're supersets of the `Ptr` cases
Commit: 52ff58c3300338876ae63126ce0d33331000f1ba
https://github.com/llvm/llvm-project/commit/52ff58c3300338876ae63126ce0d33331000f1ba
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/lib/Headers/CMakeLists.txt
R clang/lib/Headers/cuda_wrappers/bits/c++config.h
Log Message:
-----------
Revert "[CUDA][HIP] Add a __device__ version of std::__glibcxx_assert_fail()" (#144850)
Reverts llvm/llvm-project#136133
Commit: 650b451d0065c8ea6a1f87e7fdc6d07648729549
https://github.com/llvm/llvm-project/commit/650b451d0065c8ea6a1f87e7fdc6d07648729549
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M libcxx/include/__memory/pointer_traits.h
Log Message:
-----------
[libc++] Simplify the implementation of pointer_traits a bit (#142260)
Commit: 1ab0e7dd60e26ac7c7fc64a273485522f5c5ba02
https://github.com/llvm/llvm-project/commit/1ab0e7dd60e26ac7c7fc64a273485522f5c5ba02
Author: Jiachen (Yangyang) Wang <130888597+WanderingAura at users.noreply.github.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll
M llvm/test/Transforms/LICM/call-hoisting.ll
Log Message:
-----------
[LICM] Hoisting writeonly calls (#143799)
Adds support for hoisting `writeonly` calls in LICM.
This patch adds a missing optimization that allows hoisting of
`writeonly` function calls out of loops when it is safe to do so.
Previously, such calls were conservatively retained inside the loop
body, and the redundant calls were only reduced through unrolling,
relying on target-dependent heuristics.
Closes #143267
Testing:
- Modified previously negative tests for hoisting writeonly calls to be
instead positive
- Added test cases for hoisting of two writeonly calls where the
pointers do/do not alias
- Added a test case for not argmemonly writeonly calls.
Commit: 0e1aab1ec833d7f8e9897b0940c634385036fdee
https://github.com/llvm/llvm-project/commit/0e1aab1ec833d7f8e9897b0940c634385036fdee
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
Log Message:
-----------
[AMDGPU] Improve test coverage for G_INTTOPTR and G_PTRTOINT (#142603)
Test P0 through P6 + P8 for both S/VGPRs.
Commit: 62fe5e428acc2c5ef9b144c5737d55b17b55feac
https://github.com/llvm/llvm-project/commit/62fe5e428acc2c5ef9b144c5737d55b17b55feac
Author: Sameer Sahasrabuddhe <sameer.sahasrabuddhe at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Log Message:
-----------
[NFC][AMDGPU] print more info when debugging SIInsertWaitcnts pass (#144629)
Commit: 8f82c027c8969d965c43909da639e7790af19956
https://github.com/llvm/llvm-project/commit/8f82c027c8969d965c43909da639e7790af19956
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
Log Message:
-----------
[AMDGPU] New RegBankSelect: Add rules for `G_PTRTOINT` and `G_INTTOPTR` (#142604)
Commit: 681db064d221e9eef024ce0aef6165caa37fbfd2
https://github.com/llvm/llvm-project/commit/681db064d221e9eef024ce0aef6165caa37fbfd2
Author: Kunqiu Chen <camsyn at foxmail.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M compiler-rt/lib/tsan/rtl/tsan_platform.h
M compiler-rt/lib/tsan/rtl/tsan_rtl_access.cpp
Log Message:
-----------
[TSan] Make Shadow/Meta region inclusive-exclusive (#144647)
This commit changes the interval shadow/meta address check from
inclusive-inclusive ( $[\mathrm{start}, \mathrm{end}]$ ) to
inclusive-exclusive ( $[\mathrm{start}, \mathrm{end})$ ), to resolve the
ambiguity of the end point address. This also aligns the logic with the
check for `isAppMem` (i.e., inclusive-exclusive), ensuring consistent
behavior across all memory classifications.
1. The `isShadowMem` and `isMetaMem` checks previously used an
inclusive-inclusive interval, i.e., $[\mathrm{start}, \mathrm{end}]$,
which could lead to a boundary address being incorrectly classified as
both Shadow and Meta memory, e.g., 0x3000_0000_0000 in
`Mapping48AddressSpace`.
- What's more, even when Shadow doesn't border Meta, `ShadowMem::end`
cannot be considered a legal shadow address, as TSan protects the gap,
i.e., `ProtectRange(ShadowEnd(), MetaShadowBeg());`
2. `ShadowMem`/`MetaMem` addresses are derived from `AppMem` using an
affine-like transformation (`* factor + bias`). This transformation
includes two extra modifications: high- and low-order bits are masked
out, and for Shadow Memory, an optional XOR operation may be applied to
prevent conflicts with certain AppMem regions.
- Given that all AppMem regions are defined as inclusive-exclusive
intervals, $[\mathrm{start}, \mathrm{end})$, the resulting Shadow/Meta
regions should logically also be inclusive-exclusive.
Note: This change is purely for improving code consistency and should
have no functional impact. In practice, the exact endpoint addresses of
the Shadow/Meta regions are generally not reached.
Commit: 584cc376870505821b5ff0b0e80be85ee563ff0c
https://github.com/llvm/llvm-project/commit/584cc376870505821b5ff0b0e80be85ee563ff0c
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M libcxx/include/__math/abs.h
M libcxx/include/math.h
M libcxx/include/stdlib.h
M libcxx/test/std/numerics/c.math/abs.verify.cpp
Log Message:
-----------
[libc++] Move std::abs into __math/abs.h (#139586)
`template <class = int>` is also added to our implementations to avoid
an ambiguity between the libc's version and our version when both are
visible.
This avoids including `<stdlib.h>` in `<math.h>`.
Commit: 20245bbf66977ca9de5a2b6e29e8617a3a5d9fb5
https://github.com/llvm/llvm-project/commit/20245bbf66977ca9de5a2b6e29e8617a3a5d9fb5
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M libcxx/test/std/numerics/c.math/abs.pass.cpp
Log Message:
-----------
[libc++][NFC] Format abs.pass.cpp test
I will modify the test in an upcoming PR. I'm formatting it now to avoid
a bunch of whitespace changes in that PR.
Commit: 6273c5d4d3540204cb0d298cf1cf74ba94ed2a6c
https://github.com/llvm/llvm-project/commit/6273c5d4d3540204cb0d298cf1cf74ba94ed2a6c
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
Log Message:
-----------
[lldb][AArch64] Correctly invalidate svg when vg is written (#140875)
Recently the Linux Kernel has fixed a bunch of issues in SME support and
while testing that, I found two tests failing:
FAIL: test_za_register_dynamic_config_main_disabled
(TestZAThreadedDynamic.AArch64ZAThreadedTestCase)
FAIL: test_za_register_dynamic_config_main_enabled
(TestZAThreadedDynamic.AArch64ZAThreadedTestCase)
These tests write to vg during streaming mode from lldb and expect to
see that za has been resized to match it. Instead, it was unavailable.
lldb-server was sending the correct amount of data but lldb client was
expecting the old size.
Turns out that instead of a write to vg invalidating svg, it was
invalidating... something else. I'm still not sure how these tests ever
worked but with this one line fix, they pass again.
I did not see this issue with SVE or streaming SVE Z registers because
those always resize using the value of vg, and vg always has the value
we just wrote.
(remember that vg is the vector length of the **current** mode, not of
non-streaming mode, whereas svg is the vector length of streaming mode,
even if you are currently in non-streaming mode)
Commit: c0a9c908a697a150f797d0dff7f0bcd3782abed9
https://github.com/llvm/llvm-project/commit/c0a9c908a697a150f797d0dff7f0bcd3782abed9
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
Log Message:
-----------
[MLIR][NVVM-Docs] Fix rendering of a few tables in NVVM Docs (#144764)
This patch corrects the formatting of tables
in the tcgen05 ld/st and smem_descriptor Ops.
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: 97c1a2444574b32dd7a283c53be248c5dbbf62e9
https://github.com/llvm/llvm-project/commit/97c1a2444574b32dd7a283c53be248c5dbbf62e9
Author: Fabian Mora <fmora.dev at gmail.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td
M mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
M mlir/include/mlir/Dialect/Linalg/Utils/Utils.h
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/Padding.cpp
M mlir/lib/Dialect/Linalg/Utils/Utils.cpp
M mlir/test/Dialect/Linalg/transform-op-pad.mlir
Log Message:
-----------
[mlir][linalg] Add option to pad dynamic dims to `linalg::rewriteAsPaddedOp` (#144354)
This patch makes the following changes:
- Add a `ValueRange typeDynDims` argument to
`linalg::makeComposedPadHighOp`, allowing to pad a tensor with dynamic
dimensions using `tensor::createPadHighOp`.
- Add a `DenseMap<std::pair<unsigned, unsigned>, OpFoldResult>
sizeToPadTo;` option to `LinalgPaddingOptions`. This option allows
setting the size to use when padding a dimension of an operand, allowing
to pad operands even in the case they don't have a constant upper
bounding box. If the value is not provided, then the constant upper
bound is used by default.
- Add a `use_prescribed_tensor_shapes` option to
`transform.structured.pad`. If set to true then `tensor.dim` will be
used as dimensions to compute the size of the padded dim instead of
computing the constant upper bound.
- This patch also changes the behavior for computing the padded shape
`linalg::rewriteAsPaddedOp`, by using the newly added options in
`LinalgPaddingOptions`.
- Finally it adds tests verifying the behavior.
Commit: af51c9d9df9d482503fe30c80dd788a02161cea6
https://github.com/llvm/llvm-project/commit/af51c9d9df9d482503fe30c80dd788a02161cea6
Author: David Sherwood <david.sherwood at arm.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/branch-weights.ll
Log Message:
-----------
[LV][NFC] Add branch weight test showing incorrect behaviour (#144682)
This patch adds a test that shows incorrect branch weights being set in
function
EpilogueVectorizerEpilogueLoop::emitMinimumVectorEpilogueIterCountCheck
Commit: 0fe78c4a290517925acc03d59f235926f440f155
https://github.com/llvm/llvm-project/commit/0fe78c4a290517925acc03d59f235926f440f155
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/include/clang/Serialization/ASTReader.h
M clang/include/clang/Serialization/ASTRecordWriter.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
Log Message:
-----------
[NFC] [Serialization] Some Code Cleanups for Name lookup table things
Commit: 5bee2c34bde1aa8b0fb5aed7d5ce330f094f6436
https://github.com/llvm/llvm-project/commit/5bee2c34bde1aa8b0fb5aed7d5ce330f094f6436
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.h
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/lib/Object/IRSymtab.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
Log Message:
-----------
RuntimeLibcalls: Pass in FloatABI and EABI type (#144691)
We need the full set of ABI options to accurately compute
the full set of libcalls. This partially resolves missing
information required to compute the set of ARM calls.
Commit: 305953a32ded8a43b22f65cf73d9214729feb1fc
https://github.com/llvm/llvm-project/commit/305953a32ded8a43b22f65cf73d9214729feb1fc
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/include/llvm/MC/MCTargetOptions.h
M llvm/include/llvm/Support/CodeGen.h
Log Message:
-----------
MC: Move ExceptionHandling enum to Support (#144692)
Similar to b5967264b0fbfd502b3a7edec27409e966fb68be, we need
to use this in RuntimeLibcalls to compute the set of library
calls.
Commit: 1c35fe4e6b2596d153da82b23d04a3779fb12730
https://github.com/llvm/llvm-project/commit/1c35fe4e6b2596d153da82b23d04a3779fb12730
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.h
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/lib/Target/VE/VEISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
RuntimeLibcalls: Pass in exception handling type (#144696)
All of the ABI options that influence libcall decisions need
to be passed in.
Commit: 74054cab7a3e04b323828850409343932e975737
https://github.com/llvm/llvm-project/commit/74054cab7a3e04b323828850409343932e975737
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/include/llvm/Analysis/HashRecognize.h
M llvm/lib/Analysis/HashRecognize.cpp
M llvm/lib/Passes/PassRegistry.def
Log Message:
-----------
[HashRecognize] Make it a non-PM analysis (#144742)
Make HashRecognize a non-PassManager analysis that can be called to get
the result on-demand, creating a new getResult() entry-point. The issue
was discovered when attempting to use the analysis to perform a
transform in LoopIdiomRecognize.
Commit: 30824c449a893771c3f25f0eb29cfa9d2cfd4f15
https://github.com/llvm/llvm-project/commit/30824c449a893771c3f25f0eb29cfa9d2cfd4f15
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
Log Message:
-----------
[lldb][DWARFASTParserClang] GetCXXObjectParameter to take DeclContext DIE parameter (#144876)
I'm trying to call `GetCXXObjectParameter` from unit-tests in a
follow-up patch and taking a `DWARFDIE` instead of `clang::DeclContext`
makes that much simpler. These should be equivalent, since all we're
trying to check is that the parent context is a record type.
Commit: 046e2f545ef568b2ce577c9172a0f147dc376071
https://github.com/llvm/llvm-project/commit/046e2f545ef568b2ce577c9172a0f147dc376071
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
A llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-interleave.ll
Log Message:
-----------
[LV] Add interleaving test with partial reductions and non-const start.
Add test coverage for mis-compile after
https://github.com/llvm/llvm-project/pull/142290.
Commit: e33f13ba4824d807e846e7783a48efd6c0bf58ee
https://github.com/llvm/llvm-project/commit/e33f13ba4824d807e846e7783a48efd6c0bf58ee
Author: Matthias Springer <me at m-sp.org>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td
M mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
M mlir/test/Dialect/Arith/ops.mlir
Log Message:
-----------
[mlir][arith] Add overflow flags to `arith.trunci` (#144863)
LLVM already supports overflow flags on `llvm.trunc` for a while. This
commit adds support for these flags to `arith.trunci`.
Commit: b73720cf6c5380854bf27d4453abf21cc87ae642
https://github.com/llvm/llvm-project/commit/b73720cf6c5380854bf27d4453abf21cc87ae642
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/StaticAnalyzer/Checkers/DynamicTypePropagation.cpp
Log Message:
-----------
[analyzer] Conversion to CheckerFamily: DynamicTypePropagation (#144735)
This commit converts the class DynamicTypePropagation to a very simple
checker family, which has only one checker frontend -- but also supports
enabling the backend ("modeling checker") without the frontend.
As a tangentially related change, this commit adds the backend of
DynamicTypePropagation as a dependency of alpha.core.DynamicTypeChecker
in Checkers.td, because the header comment of DynamicTypeChecker.cpp
claims that it depends on DynamicTypePropagation and the source code
seems to confirm this.
(The lack of this dependency relationship didn't cause problems, because
'core.DynamicTypePropagation' is in the group 'core', so it is
practically always active. However, explicitly declaring the dependency
clarifies the fact that the separate existence of the modeling checker
is warranted.)
Commit: 2b4d757290226e0185e17294339aae1588efd07e
https://github.com/llvm/llvm-project/commit/2b4d757290226e0185e17294339aae1588efd07e
Author: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M bolt/include/bolt/Passes/PAuthGadgetScanner.h
M bolt/lib/Passes/PAuthGadgetScanner.cpp
A bolt/test/binary-analysis/AArch64/gs-pauth-authentication-oracles.s
M bolt/test/binary-analysis/AArch64/gs-pauth-debug-output.s
Log Message:
-----------
[BOLT] Gadget scanner: detect authentication oracles (#135663)
Implement the detection of authentication instructions whose results can
be inspected by an attacker to know whether authentication succeeded.
As the properties of output registers of authentication instructions are
inspected, add a second set of analysis-related classes to iterate over
the instructions in reverse order.
Commit: 936c5566db013225dc098ff961395bb19e1bf2a4
https://github.com/llvm/llvm-project/commit/936c5566db013225dc098ff961395bb19e1bf2a4
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Semantics/CMakeLists.txt
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
R flang/lib/Semantics/rewrite-directives.cpp
R flang/lib/Semantics/rewrite-directives.h
M flang/lib/Semantics/rewrite-parse-tree.cpp
A flang/test/Lower/OpenMP/requires-admo-acqrel.f90
A flang/test/Lower/OpenMP/requires-admo-invalid1.f90
A flang/test/Lower/OpenMP/requires-admo-invalid2.f90
R flang/test/Semantics/OpenMP/requires-atomic01.f90
R flang/test/Semantics/OpenMP/requires-atomic02.f90
Log Message:
-----------
[flang][OpenMP] Handle REQUIRES ADMO in lowering (#144362)
The previous approach rewrote the atomic constructs in the AST based on
the REQUIRES ATOMIC_DEFAULT_MEM_ORDER directives. The new approach
checks for incorrect uses of REQUIRED ADMO in the semantic analysis, and
applies it in lowering, eliminating the need for a separate
tree-rewriting procedure.
Commit: e478a22d540d336632fb3c110c5377447cd7f3b2
https://github.com/llvm/llvm-project/commit/e478a22d540d336632fb3c110c5377447cd7f3b2
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/test/CodeGen/builtin_vectorelements.c
M llvm/include/llvm/IR/IRBuilder.h
M llvm/lib/IR/IRBuilder.cpp
M llvm/test/Analysis/ValueTracking/phi-known-bits.ll
M llvm/test/Instrumentation/AddressSanitizer/asan-masked-load-store.ll
M llvm/test/Instrumentation/AddressSanitizer/asan-vp-load-store.ll
M llvm/test/Instrumentation/AddressSanitizer/vector-load-store.ll
M llvm/test/Instrumentation/BoundsChecking/simple.ll
M llvm/test/Instrumentation/HWAddressSanitizer/vector-load-store.ll
M llvm/test/Instrumentation/MemorySanitizer/vector-load-store.ll
M llvm/test/Instrumentation/MemorySanitizer/vscale.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-counting-elems.ll
M llvm/test/Transforms/InstCombine/gep-vector.ll
M llvm/test/Transforms/InstCombine/gepofconstgepi8.ll
M llvm/test/Transforms/InstCombine/getelementptr.ll
M llvm/test/Transforms/InstCombine/icmp-gep.ll
M llvm/test/Transforms/InstCombine/masked_intrinsics.ll
M llvm/test/Transforms/InstCombine/opaque-ptr.ll
M llvm/test/Transforms/InstCombine/scalable-vector-array.ll
M llvm/test/Transforms/InstCombine/scalable-vector-struct.ll
M llvm/test/Transforms/InstCombine/sub-gep.ll
M llvm/test/Transforms/InstCombine/vscale_gep.ll
M llvm/test/Transforms/LoopVectorize/AArch64/clamped-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/divs-with-scalable-vfs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/eliminate-tail-predication.ll
M llvm/test/Transforms/LoopVectorize/AArch64/gather-do-not-vectorize-addressing.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll
M llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_prefer_scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
M llvm/test/Transforms/LoopVectorize/AArch64/pr60831-sve-inv-store-crash.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-avoid-scalarization.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-reduction-inloop-cond.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
M llvm/test/Transforms/LoopVectorize/AArch64/simple_early_exit.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-inloop-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-no-remaining-iterations.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-strict-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-extract-last-veclane.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-fneg.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inv-store.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-live-out-pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-multiexit.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-runtime-check-size-based-threshold.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-forced.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-optsize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-unroll.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-vscale-based-trip-counts.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-gep.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-too-many-deps.ll
M llvm/test/Transforms/LoopVectorize/AArch64/tail-folding-styles.ll
M llvm/test/Transforms/LoopVectorize/AArch64/uniform-args-call-variants.ll
M llvm/test/Transforms/LoopVectorize/AArch64/wider-VF-for-callinst.ll
M llvm/test/Transforms/LoopVectorize/RISCV/bf16.ll
M llvm/test/Transforms/LoopVectorize/RISCV/blend-any-of-reduction-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/defaults.ll
M llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
M llvm/test/Transforms/LoopVectorize/RISCV/f16.ll
M llvm/test/Transforms/LoopVectorize/RISCV/fminimumnum.ll
M llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-masked-access.ll
M llvm/test/Transforms/LoopVectorize/RISCV/lmul.ll
M llvm/test/Transforms/LoopVectorize/RISCV/low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/RISCV/mask-index-type.ll
M llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll
M llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/RISCV/remark-reductions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse-output.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/RISCV/safe-dep-distance.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-basics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-tailfold.ll
M llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-bin-unary-ops-args.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cond-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-div.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-interleave.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-intermediate-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-iv32.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-known-no-overflow.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-masked-loadstore.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-ordered-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-safe-dep-distance.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-uniform-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_scalable.ll
M llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/scalable-inductions.ll
M llvm/test/Transforms/LoopVectorize/scalable-iv-outside-user.ll
M llvm/test/Transforms/LoopVectorize/scalable-lifetime.ll
M llvm/test/Transforms/LoopVectorize/scalable-loop-unpredicated-body-scalar-tail.ll
M llvm/test/Transforms/LoopVectorize/scalable-reduction-inloop.ll
M llvm/test/Transforms/LoopVectorize/scalable-trunc-min-bitwidth.ll
M llvm/test/Transforms/LoopVectorize/vectorize-force-tail-with-evl.ll
M llvm/test/Transforms/MemCpyOpt/vscale-crashes.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/sve-interleave-vectorization.ll
M llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-exp.ll
Log Message:
-----------
[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532)
This put the onus on the caller to ensure the result type is big enough.
In the unlikely event a cropped result is required then explicitly
truncate a safe value.
Commit: c4c2d777f4aea07c59ff85ade75816df24b05389
https://github.com/llvm/llvm-project/commit/c4c2d777f4aea07c59ff85ade75816df24b05389
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-interleave.ll
Log Message:
-----------
[VPlan] Fix handling of ReductionStartVector for rdxs when unrolling.
Update handling of ReductionStartVector in VPlanUnroll for partial
reductions. The new code makes sure all parts are properly set to the
cloned ReductionStartVector.
Fixes a mis-compile reported for
https://github.com/llvm/llvm-project/pull/142290.
Commit: 5148e085386fb1808fba055e170d88e3344220ca
https://github.com/llvm/llvm-project/commit/5148e085386fb1808fba055e170d88e3344220ca
Author: Karlo Basioli <k.basioli at gmail.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/include/clang/Serialization/ASTRecordWriter.h
Log Message:
-----------
Fix build issue caused by commit #0fe78c4 (#144888)
Noticed internally in blaze build.
Commit: dae5104eed451fdd0354ff9639feba10f9dc5440
https://github.com/llvm/llvm-project/commit/dae5104eed451fdd0354ff9639feba10f9dc5440
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.h
M lldb/unittests/SymbolFile/DWARF/DWARFASTParserClangTests.cpp
Log Message:
-----------
[lldb][DWARFASTParserClang] Make GetCXXObjectParameter public and call it from unit-tests (#144879)
My goal is to remove the `object_pointer` member on
`ParsedDWARFTypeAttributes` since it's duplicating information that we
retrieve with `GetCXXObjectParameter` anyway. To continue having
coverage for the `DW_AT_object_pointer` code-paths, instead of checking
the
`attrs.object_pointer` I'm now calling `GetCXXObjectParameter` directly.
We could find some very roundabout way to go via the Clang AST to check
that the object parameter was parsed correctly, but that quickly became
quite painful.
Depends on https://github.com/llvm/llvm-project/pull/144876
Commit: c079040eea5ce75a97285003948d141ebaac69e6
https://github.com/llvm/llvm-project/commit/c079040eea5ce75a97285003948d141ebaac69e6
Author: Charles Zablit <c_zablit at apple.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M lldb/include/lldb/Core/DemangledNameInfo.h
M lldb/unittests/Core/MangledTest.cpp
Log Message:
-----------
[lldb] add has methods to all DemangledNameInfo attributes (#144549)
Add `hasX` methods to all the attributes of `DemangledNameInfo`.
Commit: 09e794c4bb138e14b3156d7dbdac0164d9c0327b
https://github.com/llvm/llvm-project/commit/09e794c4bb138e14b3156d7dbdac0164d9c0327b
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.cpp
Log Message:
-----------
[HIP] Emit the CUID value in the module with the new driver (#144570)
Summary:
This is a weird point of divergence that was not updated when the new
driver
switched to using the CUID method, which is also apparently critical
for SPIR-V compilation not failing? Somehow if we don't emit this global
than the `llvm.compiler.used` global uses AS(0) which makes SPIR-V
unhappy, but with this global it's AS(4) which makes it happy. Either
way, this should be fixed.
Commit: e873fd157eda617ffd42edad3c4a6ab495e6e375
https://github.com/llvm/llvm-project/commit/e873fd157eda617ffd42edad3c4a6ab495e6e375
Author: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M bolt/lib/Passes/PAuthGadgetScanner.cpp
M bolt/test/binary-analysis/AArch64/gs-pauth-debug-output.s
Log Message:
-----------
[BOLT] Gadget scanner: do not crash on debug-printing CFI instructions (#136151)
Some instruction-printing code used under LLVM_DEBUG does not handle CFI
instructions well. While CFI instructions seem to be harmless for the
correctness of the analysis results, they do not convey any useful
information to the analysis either, so skip them early.
Commit: 493a359237e824216d5c572656481c42165a2cb7
https://github.com/llvm/llvm-project/commit/493a359237e824216d5c572656481c42165a2cb7
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M lldb/test/API/commands/register/register/aarch64_mte_ctrl_register/TestMTECtrlRegister.py
Log Message:
-----------
[lldb][AArch64] Fix live process test for Linux's mte_ctrl register
I forgot to update this when I changed the presentation of the
"TCF" field.
Commit: 83381ba832a5cf34b09e27a6154c7179fed2fc80
https://github.com/llvm/llvm-project/commit/83381ba832a5cf34b09e27a6154c7179fed2fc80
Author: Ilia Kuklin <ikuklin at accesssoftek.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M lldb/source/ValueObject/DILParser.cpp
M lldb/test/API/commands/frame/var-dil/basics/ArraySubscript/TestFrameVarDILArraySubscript.py
M lldb/test/API/commands/frame/var-dil/basics/ArraySubscript/main.cpp
Log Message:
-----------
[LLDB] Add negative number parsing to DIL (#144557)
Commit: 5645d6710904107d66a45f1c3ee0ee25924ff08a
https://github.com/llvm/llvm-project/commit/5645d6710904107d66a45f1c3ee0ee25924ff08a
Author: Aly ElAshram <71949028+AlyElashram at users.noreply.github.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
A libc/config/darwin/aarch64/config.json
M libc/config/darwin/aarch64/entrypoints.txt
M libc/config/darwin/aarch64/headers.txt
M libc/src/setjmp/CMakeLists.txt
A libc/src/setjmp/darwin/CMakeLists.txt
A libc/src/setjmp/darwin/sigsetjmp_epilogue.cpp
M libc/test/src/CMakeLists.txt
Log Message:
-----------
Implement `sigsetjmp` and `siglongjmp` for darwin/aarch64 (#139555)
Commit: bf79d4819edeb54c6cf528db63676110992908a8
https://github.com/llvm/llvm-project/commit/bf79d4819edeb54c6cf528db63676110992908a8
Author: zhijian lin <zhijian at ca.ibm.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/lib/Basic/Targets/PPC.cpp
M clang/test/CodeGenCXX/cxx11-thread-local-reference.cpp
M clang/test/Driver/aix-shared-lib-tls-model-opt.c
M clang/test/Driver/aix-small-local-exec-dynamic-tls.c
M clang/test/Driver/ppc-crbits.cpp
M clang/test/Driver/ppc-isa-features.cpp
M llvm/include/llvm/TargetParser/CMakeLists.txt
M llvm/include/llvm/TargetParser/PPCTargetParser.h
M llvm/include/llvm/TargetParser/TargetParser.h
M llvm/lib/Target/PowerPC/PPC.td
M llvm/lib/TargetParser/PPCTargetParser.cpp
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/utils/TableGen/Basic/CMakeLists.txt
A llvm/utils/TableGen/Basic/TargetFeaturesEmitter.cpp
A llvm/utils/TableGen/Basic/TargetFeaturesEmitter.h
M llvm/utils/TableGen/SubtargetEmitter.cpp
Log Message:
-----------
[Reland] [PowerPC] frontend get target feature from backend with cpu name (#144594)
1. The PR proceeds with a backend target hook to allow front-ends to
determine what target features are available in a compilation based on
the CPU name.
2. Fix a backend target feature bug that supports HTM for
Power8/9/10/11. However, HTM is only supported on Power8/9 according to
the ISA.
3. All target features that are hardcoded in PPC.cpp can be retrieved
from the backend target feature. I have double-checked that the
hardcoded logic for inferring target features from the CPU in the
frontend(PPC.cpp) is the same as in PPC.td.
The reland patch addressed the comment
https://github.com/llvm/llvm-project/pull/137670#discussion_r2143541120
Commit: f87b6625d64c4ba95cf26b249ce6bdbcb31d65c9
https://github.com/llvm/llvm-project/commit/f87b6625d64c4ba95cf26b249ce6bdbcb31d65c9
Author: Abdul Raheem <abdulraheembeigh at gmail.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M mlir/include/mlir/IR/Operation.h
Log Message:
-----------
[MLIR][NFC] Fixed some Typos (#144263)
-- Fixed some typos in Operation.h
Signed-off: Abdul Raheem Beigh abdulraheembeigh at gmail.com
Commit: e75e2485f2e5e627d0bdf0306df4672f69ddd6eb
https://github.com/llvm/llvm-project/commit/e75e2485f2e5e627d0bdf0306df4672f69ddd6eb
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
A llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-gfx12-fake16.mir
A llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-gfx12-true16.mir
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-fake16.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
Log Message:
-----------
[AMDGPU][True16][Codegen] keep srcmod/clamp/omod from v_s_xxx_f16 when moved to VALU (#144781)
https://github.com/llvm/llvm-project/pull/141152 causes an issue in
v_s_xxx_f16 lowering in both true16/fake16 flow.
V_S_XXX_F16 are special insts which has scalar input/output but in VALU
VOP3 format. Need to keep the srcmod/clamp/omod when lower it to its
corresponding VALU inst with vector input/output.
Commit: 278ece7c80d36bb1074fa53e655a5ca8f31145dd
https://github.com/llvm/llvm-project/commit/278ece7c80d36bb1074fa53e655a5ca8f31145dd
Author: Abhishek Kaushik <abhishek.kaushik at intel.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
A llvm/test/Transforms/InstCombine/bitcast-known-bits.ll
Log Message:
-----------
[InstCombine][NFC] Pre-commit tests for #125935 (#144111)
Pre-commit tests for #125935
---------
Co-authored-by: Simon Pilgrim <llvm-dev at redking.me.uk>
Commit: a4e4527c4b44be9a88168c0a4758de58fd1a770d
https://github.com/llvm/llvm-project/commit/a4e4527c4b44be9a88168c0a4758de58fd1a770d
Author: Matthias Springer <me at m-sp.org>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M mlir/lib/Conversion/FuncToLLVM/FuncToLLVM.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
Log Message:
-----------
[mlir][Transforms] Fix replaceUsesOfBlockArgument API (#144706)
Before this PR, users had to pass the "old" block argument when
replacing the uses of a block argument in a newly converted block. Users
can now pass the actual block argument that should be replaced.
Note for LLVM integration: Make sure to pass the current block argument
instead of the old one.
Commit: 802fa92aee3565768887615108aa3e924d4e0fc7
https://github.com/llvm/llvm-project/commit/802fa92aee3565768887615108aa3e924d4e0fc7
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Utils/PredicateInfo.cpp
Log Message:
-----------
[PredicateInfo] Avoid duplicate hash lookup (NFC)
Use try_emplace to either look up the existing entry or insert it.
Commit: 7e8f1f5f72753a1d9d3ae2810da52b82a787600b
https://github.com/llvm/llvm-project/commit/7e8f1f5f72753a1d9d3ae2810da52b82a787600b
Author: Siu Chi Chan <siuchi.chan at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/test/Driver/hip-runtime-libs-linux.hip
Log Message:
-----------
[HIP] Remove dots in HIP runtime path (#143792)
Remove the dots in the HIP path before passing to the rpath flag
Commit: 4c6f398b866030c17fd94dcdca04f4df03c5214c
https://github.com/llvm/llvm-project/commit/4c6f398b866030c17fd94dcdca04f4df03c5214c
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Driver/ToolChains/HIPAMD.h
A clang/test/Driver/spirv-amd-toolchain.c
Log Message:
-----------
[Clang] Add standalone AMDGPU SPIR-V toolchain (#144576)
Summary:
The AMDGPU toolchain uses a different set of tools than the standard
SPIR-V toolchain. The linker wrapper prefers to invoke a linker via a
clang toolchain. To make that work we introduce
`--target=spirv64-amd-amdhsa` so that it creates the linking phases that
HIP prefers. Additionally, this can be used to make LLVM-IR / SPIR-V
from C/C++ that can be linked with the HIP output.
Commit: 19360e62d0d1a1dabf9f01736927ab8f1b72c7df
https://github.com/llvm/llvm-project/commit/19360e62d0d1a1dabf9f01736927ab8f1b72c7df
Author: Nico Weber <thakis at chromium.org>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/include/llvm/TargetParser/BUILD.gn
M llvm/utils/gn/secondary/llvm/utils/TableGen/Basic/BUILD.gn
Log Message:
-----------
[gn build] port bf79d4819ede (ppc -gen-target-features)
Commit: 89efae916a5de0387710b7dc06938423817e1503
https://github.com/llvm/llvm-project/commit/89efae916a5de0387710b7dc06938423817e1503
Author: Jack Styles <jack.styles at arm.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
A flang/test/Lower/OpenMP/target-enter-data-default-openmp52.f90
Log Message:
-----------
[Flang][OpenMP] Update default MapType for Map Clauses and OpenMP 5.2 (#144715)
In OpenMP 5.2, the `target enter data` and `target exit data` constructs
now have default map types if the user does not define them in the Map
clause. For `target enter data`, this is `to` and `target exit data`
this is `from`. This behaviour is now enabled when OpenMP 5.2 or greater
is used when compiling. To enable this, the default value is now set in
the `processMap` clause, with any previous behaviour being maintained
for either older versions of OpenMP or other directives.
See also #110008
Commit: eb694b28461fdbd5e347fca59829e8a9ad021773
https://github.com/llvm/llvm-project/commit/eb694b28461fdbd5e347fca59829e8a9ad021773
Author: Tobias Gysi <tobias.gysi at nextsilicon.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/test/Dialect/Arith/canonicalize.mlir
Log Message:
-----------
[mlir][arith] Delete mul ext canonicalizations (#144844)
The Arith dialect includes patterns that canonicalize a sequence of:
- trunci(shrui(mul(sext(x), sext(y)), c)) -> mulsi_extended(x, y)
- trunci(shrui(mul(zext(x), zext(y)), c)) -> mului_extended(x, y)
These patterns return the high word of an extended multiplication, which
assumes that the shift amount is equal to the bit width of the original
operands. This check was missing, leading to incorrect canonicalizations
when the shift amount was less than the bit width.
For example, the following code:
```
%x = arith.extui %a: i32 to i33
%y = arith.extui %b: i32 to i33
%m = arith.muli %x, %y: i33
%c1 = arith.constant 1: i33
%sh = arith.shrui %m, %c1 : i33
%hi = arith.trunci %sh: i33 to i32
```
would incorrectly be canonicalized to:
```
_, %hi = arith.mului_extended %a, %b : i32
```
This commit removes the faulty canonicalizations since they are not
believed to be generally beneficial (c.f., the discussion of the
alternative https://github.com/llvm/llvm-project/pull/144787 which fixes
the canonicalizations).
Commit: 3516ad05dfd674d731487cb67bbfe48f7e1fda9c
https://github.com/llvm/llvm-project/commit/3516ad05dfd674d731487cb67bbfe48f7e1fda9c
Author: Mikhail R. Gadelha <mikhail at igalia.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/floating-point.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.s
Log Message:
-----------
[RISCV] Update SpacemiT X60 scheduling latencies based on hardware measurements (#144730)
This patch updates the RISC-V SpacemiT X60 scheduling model with latency
values collected from the X60 hardware. The previous values were
empirically derived but were slightly off.
Changes:
- LoadLatency (baseline for load instructions): 5 --> 3 cycles
- Memory operations: unified at 4 cycles
- Atomic loads/stores: 5 --> 8 cycles
- Atomic RMW operations: 5 --> 12 cycles
Hardware-measured values provide more accurate instruction scheduling
for the in-order X60 core. Testing shows NFC across benchmarks except
for 523.xalancbmk_r (known to be noisy).
https://lnt.lukelau.me/db_default/v4/nts/663?compare_to=657
Commit: fdb572681de7e12b7cd03fd33478022272eb1bae
https://github.com/llvm/llvm-project/commit/fdb572681de7e12b7cd03fd33478022272eb1bae
Author: Karlo Basioli <k.basioli at gmail.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
Fix bazel build after #144594 (#144904)
Commit: 5eb24fde11cd82a08f208509f80f428da90c89c9
https://github.com/llvm/llvm-project/commit/5eb24fde11cd82a08f208509f80f428da90c89c9
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/RISCV/shifts.ll
Log Message:
-----------
[SelectionDAG][RISCV] Preserve nneg flag when folding (trunc (zext X))->(zext X). (#144807)
If X is known non-negative, that's still true if we fold the truncate
to create a smaller zext.
In the i128 tests, SelectionDAGBuilder aggressively truncates the
`zext nneg` to i64 to match `getShiftAmountTy`. If we don't preserve
the `nneg` we can't see that the shift amount argument being `signext`
means we don't need to do any extension
Commit: 3de01d07c33c10dfefc753c87c0a926fd512425b
https://github.com/llvm/llvm-project/commit/3de01d07c33c10dfefc753c87c0a926fd512425b
Author: Karlo Basioli <k.basioli at gmail.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/TargetParser/TargetParser.cpp
Log Message:
-----------
Fix bazel build after #144594, mark variable as potentially unused (#144910)
Commit: 36af7345dfb8e84a1f2971db34089b63321e8467
https://github.com/llvm/llvm-project/commit/36af7345dfb8e84a1f2971db34089b63321e8467
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/docs/CommandGuide/clang.rst
M clang/docs/ReleaseNotes.rst
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/extend-variable-liveness.c
Log Message:
-----------
Reapply "[Clang] Enable -fextend-variable-liveness at -Og (#118026)"
Relands this feature after several fixes:
* Force fake uses to be emitted before musttail calls (#136867)
* Added soften-float legalization for fake uses (#142714)
* Treat fake uses as size-less instructions in a SystemZ assert (#144390)
If further issues with fake uses are found then this may be reverted again,
but all currently-known issues are resolved.
This reverts commit 2dc6e98169baeb1f73036da0ea50fd828d8323d0.
Commit: f4db14229cd975822c41376afda9d56a29f9396c
https://github.com/llvm/llvm-project/commit/f4db14229cd975822c41376afda9d56a29f9396c
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/include/llvm/Transforms/Utils/SCCPSolver.h
M llvm/lib/Transforms/IPO/SCCP.cpp
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
Log Message:
-----------
[SCCP] Move logic for removing ssa.copy into Solver (NFC)
So it can be reused between IPSCCP and SCCP.
Make the implementation a bit more efficient by only lookup the
PredicateInfo once.
Commit: 01d648a42939c834b6b45677e540882222b01c11
https://github.com/llvm/llvm-project/commit/01d648a42939c834b6b45677e540882222b01c11
Author: Steven Perron <stevenperron at google.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/AST/HLSL/vk.spec-constant.usage.hlsl
R clang/test/CodeGenHLSL/inline-spirv/SpirvType.alignment.hlsl
R clang/test/CodeGenHLSL/inline-spirv/SpirvType.hlsl
A clang/test/CodeGenHLSL/vk-features/SpirvType.alignment.hlsl
A clang/test/CodeGenHLSL/vk-features/SpirvType.hlsl
A clang/test/CodeGenHLSL/vk-features/vk.spec-constant.hlsl
A clang/test/SemaHLSL/vk.spec-constant.error.hlsl
Log Message:
-----------
[HLSL][SPIRV] Reapply "[HLSL][SPIRV] Add vk::constant_id attribute." (#144902)
- **Reapply "[HLSL][SPIRV] Add vk::constant_id attribute." (#144812)**
- **Fix memory leak.**
Commit: c1ac87b327861a7387c1ab9e1ffb1c002acbcd6a
https://github.com/llvm/llvm-project/commit/c1ac87b327861a7387c1ab9e1ffb1c002acbcd6a
Author: lntue <lntue at google.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M libc/src/setjmp/CMakeLists.txt
Log Message:
-----------
[libc] Fix setjmp build order. (#144917)
Fix build order issue from
https://github.com/llvm/llvm-project/pull/139555.
Commit: b8337349d9b6143669e8bfa6776926a708cacf99
https://github.com/llvm/llvm-project/commit/b8337349d9b6143669e8bfa6776926a708cacf99
Author: lntue <lntue at google.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M libc/src/__support/FPUtil/FEnvImpl.h
M libc/src/__support/macros/optimization.h
Log Message:
-----------
[libc][math] Skip setting errno and floating point exception for math functions when LIBC_MATH flag has LIBC_MATH_NO_ERRNO and LIBC_MATH_NO_EXCEPT. (#144920)
Commit: 5cf7d871b030212d021ffc9356620551f09ad402
https://github.com/llvm/llvm-project/commit/5cf7d871b030212d021ffc9356620551f09ad402
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/Expr.h
M clang/include/clang/AST/OpenACCClause.h
M clang/include/clang/AST/OpenMPClause.h
M clang/include/clang/AST/StmtOpenACC.h
M clang/include/clang/AST/Type.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/AST/ExprCXX.cpp
M clang/lib/AST/OpenMPClause.cpp
M clang/lib/AST/Type.cpp
Log Message:
-----------
[NFC][Clang][AST] Adopt simplified `getTrailingObjects` in AST (#144432)
Adopt simplified `getTrailingObjects` API in several places in clag/AST
that were missed by earlier changes.
Commit: c0cc81cdc03c97473ba771bbc3a2330bd22396bc
https://github.com/llvm/llvm-project/commit/c0cc81cdc03c97473ba771bbc3a2330bd22396bc
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
Log Message:
-----------
[NFC][Clang] Adopt simplified `getTrailingObjects` in ASTReader (#144438)
Commit: 3fe62682ef9ca514b899d0cecaebb8f1fd97baef
https://github.com/llvm/llvm-project/commit/3fe62682ef9ca514b899d0cecaebb8f1fd97baef
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
Log Message:
-----------
[mlir][vector] Use `result` consistently as the result argument name (#144739)
This patch updates the following ops to use `result` (instead of `res`)
as the name for their result argument:
* `vector.scalable.insert`
* `vector.scalable.extract`
* `vector.insert_strided_slice`
This change ensures naming consistency with other ops in the `vector`
dialect. It addresses part of:
* https://github.com/llvm/llvm-project/issues/131602
Commit: 0816bb32ac37b24d2f895f0c0464b7659fffd4fc
https://github.com/llvm/llvm-project/commit/0816bb32ac37b24d2f895f0c0464b7659fffd4fc
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
Log Message:
-----------
[Matrix] Fix heap-use-after-free after 0fa373c77ded203eddb.
We need to skip instructions in FusedInsts, as they may have been
deleted. Fixes a heap-use-after-free after #141681.
Commit: 6ce86538c11b3ef93a2a8df3bd4f817a724f42bd
https://github.com/llvm/llvm-project/commit/6ce86538c11b3ef93a2a8df3bd4f817a724f42bd
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M mlir/include/mlir/Dialect/ControlFlow/IR/ControlFlowOps.td
M mlir/lib/Dialect/ControlFlow/IR/ControlFlowOps.cpp
M mlir/test/Dialect/ControlFlow/canonicalize.mlir
Log Message:
-----------
[mlir][cf] Preserve branch weights during cf.cond_br canonicalization. (#144822)
Commit: c0c71463f6bca05eb4540b68cdcbd17c916562c9
https://github.com/llvm/llvm-project/commit/c0c71463f6bca05eb4540b68cdcbd17c916562c9
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/include/llvm/IR/PatternMatch.h
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp
A llvm/test/Transforms/InstCombine/sub-sext-add.ll
Log Message:
-----------
[InstCombine] Optimize sub(sext(add(x,y)),sext(add(x,z))). (#144174)
This pattern can be often met in Flang generated LLVM IR,
for example, for the counts of the loops generated for array
expressions like: `a(x:x+y)` or `a(x+z:x+z)` or their variations.
In order to compute the loop count, Flang needs to subtract
the lower bound of the array slice from the upper bound
of the array slice. To avoid the sign wraps, it sign extends
the original values (that may be of any user data type)
to `i64`.
This peephole is really helpful in CPU2017/548.exchange2,
where we have multiple following statements like this:
```
block(row+1:row+2, 7:9, i7) = block(row+1:row+2, 7:9, i7) - 10
```
While this is just a 2x3 iterations loop nest, LLVM cannot
figure it out, ending up vectorizing the inner loop really
hard (with a vector epilog and scalar remainder). This, in turn,
causes problems for LSR that ends up creating too many loop-carried
values in the loop containing the above statement, which are then
causing too many spills/reloads.
Alive2: https://alive2.llvm.org/ce/z/gLgfYX
Related to #143219.
Commit: 0b8179b2adbc821324c425d7cafd269f84e72d5e
https://github.com/llvm/llvm-project/commit/0b8179b2adbc821324c425d7cafd269f84e72d5e
Author: Abhishek Kaushik <abhishek.kaushik at intel.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Transforms/InstCombine/X86/x86-vector-shifts.ll
M llvm/test/Transforms/InstCombine/bitcast-known-bits.ll
Log Message:
-----------
[ValueTracking] Improve `Bitcast` handling to match SDAG (#125935)
Closes #125228
Commit: f780955e1df9105e9c4e67ebd16efded7dd279e2
https://github.com/llvm/llvm-project/commit/f780955e1df9105e9c4e67ebd16efded7dd279e2
Author: Justin King <jcking at google.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M compiler-rt/lib/lsan/lsan_interceptors.cpp
Log Message:
-----------
lsan: fix macos build after #144604 (#144818)
Fixes build failures on macOS, including
https://green.lab.llvm.org/job/llvm.org/job/clang-stage1-RA/
llvm-project/compiler-rt/lib/lsan/lsan_interceptors.cpp:579:3: error: use of undeclared identifier 'LSAN_MAYBE_INTERCEPT_FREE_SIZED'
13:23:58 579 | LSAN_MAYBE_INTERCEPT_FREE_SIZED;
13:23:58 | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
13:23:58 /Users/ec2-user/jenkins/workspace/llvm.org/as-lldb-cmake/llvm-project/compiler-rt/lib/lsan/lsan_interceptors.cpp:580:3: error: use of undeclared identifier 'LSAN_MAYBE_INTERCEPT_FREE_ALIGNED_SIZED'
13:23:58 580 | LSAN_MAYBE_INTERCEPT_FREE_ALIGNED_SIZED;
13:23:58 | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
13:23:58 2 errors generated.
Commit: 836201f1177c38f3ca0457de019bb179a04afe3c
https://github.com/llvm/llvm-project/commit/836201f1177c38f3ca0457de019bb179a04afe3c
Author: Umang Yadav <29876643+umangyadav at users.noreply.github.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/test/Conversion/AMDGPUToROCDL/mfma-gfx950.mlir
Log Message:
-----------
Allow bf16 operands on new MFMAs (#144925)
New gfx950 MFMA allows bf16 operands.
https://github.com/llvm/llvm-project/blob/c0cc81cdc03c97473ba771bbc3a2330bd22396bc/llvm/include/llvm/IR/IntrinsicsAMDGPU.td#L3434
When running `amdgpu-to-rocdl`, Current logic converts bf16 to i16
always which fails to compile for newer bf16 MFMA e.g.
`v_mfma_f32_16x16x32bf16`.
Backend expects bf16 type for the operands for those newer MFMAs. This
patch fixes it.
CC: @krzysz00 @dhernandez0 @giuseros @antiagainst @kuhar
Commit: 74ec1c287a88dffc232c38e0fdd3251f6b167d15
https://github.com/llvm/llvm-project/commit/74ec1c287a88dffc232c38e0fdd3251f6b167d15
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
A llvm/test/Transforms/LoopVectorize/ARM/mve-reductions-interleave.ll
Log Message:
-----------
[LV] Add tests interleaving extended and multiply/accumulate reductions.
Add missing test coverage for interleaving with
VPExtendedReduction/VPMulAccumulateReduction recipes.
Adds missing test coverage in preparation for
https://github.com/llvm/llvm-project/pull/144281.
Commit: 3bee9ba0156ee130fa88379a5a89de0812936a3d
https://github.com/llvm/llvm-project/commit/3bee9ba0156ee130fa88379a5a89de0812936a3d
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/test/CodeGen/AMDGPU/insert-skips-gfx12.mir
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.ll
Log Message:
-----------
AMDGPU/GFX12: Fix s_barrier_signal_isfirst for single-wave workgroups (#143634)
Barrier instructions are no-ops in single-wave workgroups. This includes
s_barrier_signal_isfirst, which will leave SCC unmodified.
Model this correctly (via an implicit use of SCC) and ensure SCC==1
before the barrier instruction (if the wave is the only one of the
workgroup, then it is the first).
---------
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
Commit: 633e740e3453bab06bf535830174c759100257f9
https://github.com/llvm/llvm-project/commit/633e740e3453bab06bf535830174c759100257f9
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/test/Driver/hip-thinlto.hip
M clang/test/Driver/openmp-offload-gpu.c
Log Message:
-----------
[Clang][AMDGPU][Driver] Add `avail-extern-gv-in-addrspace-to-local` option when ThinTLO is enabled (#144914)
On AMDGPU, we need an extra argument
`-avail-extern-gv-in-addrspace-to-local=3`
to privatize LDS global variables when ThinLTO is enabled.
Commit: baf35d7a829efb9688dc0aef6d1e161ef6bc5983
https://github.com/llvm/llvm-project/commit/baf35d7a829efb9688dc0aef6d1e161ef6bc5983
Author: William Huynh <William.Huynh at arm.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M libc/cmake/modules/LLVMLibCCompileOptionRules.cmake
Log Message:
-----------
[libc] Fix bug in LIBC_CONF_ERRNO_MODE being undefined (#144896)
A typo, set() instead of list() would cause the build to not define
LIBC_CONF_ERRNO_MODE, which would cause the wrong configuration to be
used.
Commit: 8631b4f1b4f30edd1f26b20e35b7367517aba359
https://github.com/llvm/llvm-project/commit/8631b4f1b4f30edd1f26b20e35b7367517aba359
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/lib/Optimizer/CodeGen/LowerRepackArrays.cpp
A flang/test/Integration/cold_array_repacking.f90
M flang/test/Transforms/lower-repack-arrays.fir
Log Message:
-----------
[flang] Set low probability for array repacking code. (#144830)
This allows LLVM to place the most probably cold blocks
that do the repacking out of the line of the potentially hot code.
Commit: 28808dda2c53a1dff1076cb83a9b91d0866ebf9a
https://github.com/llvm/llvm-project/commit/28808dda2c53a1dff1076cb83a9b91d0866ebf9a
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M flang/test/Integration/cold_array_repacking.f90
Log Message:
-----------
[flang] Fixed test added in #144830.
Commit: 9945ddf8675d982e8656e688713a9bee02a811e9
https://github.com/llvm/llvm-project/commit/9945ddf8675d982e8656e688713a9bee02a811e9
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-06-19 (Thu, 19 Jun 2025)
Changed paths:
M .github/new-prs-labeler.yml
M .github/workflows/libcxx-restart-preempted-jobs.yaml
M bolt/include/bolt/Passes/PAuthGadgetScanner.h
M bolt/lib/Passes/PAuthGadgetScanner.cpp
M bolt/test/AArch64/r_aarch64_prelxx.s
A bolt/test/binary-analysis/AArch64/gs-pauth-authentication-oracles.s
M bolt/test/binary-analysis/AArch64/gs-pauth-debug-output.s
M clang-tools-extra/clang-tidy/cppcoreguidelines/CMakeLists.txt
M clang-tools-extra/clang-tidy/cppcoreguidelines/CppCoreGuidelinesTidyModule.cpp
A clang-tools-extra/clang-tidy/cppcoreguidelines/UseEnumClassCheck.cpp
A clang-tools-extra/clang-tidy/cppcoreguidelines/UseEnumClassCheck.h
M clang-tools-extra/clangd/ClangdLSPServer.cpp
M clang-tools-extra/clangd/Protocol.cpp
M clang-tools-extra/clangd/Protocol.h
A clang-tools-extra/clangd/test/positionencoding.test
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines/use-enum-class.rst
M clang-tools-extra/docs/clang-tidy/checks/list.rst
M clang-tools-extra/docs/clang-tidy/checks/performance/enum-size.rst
A clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/use-enum-class.cpp
M clang/docs/CommandGuide/clang.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/Toolchain.rst
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/Expr.h
M clang/include/clang/AST/OpenACCClause.h
M clang/include/clang/AST/OpenMPClause.h
M clang/include/clang/AST/StmtOpenACC.h
M clang/include/clang/AST/StmtOpenMP.h
M clang/include/clang/AST/Type.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/Interfaces/CIROpInterfaces.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/Parse/Parser.h
M clang/include/clang/Sema/SemaHLSL.h
M clang/include/clang/Sema/SemaObjC.h
M clang/include/clang/Serialization/ASTReader.h
M clang/include/clang/Serialization/ASTRecordWriter.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Descriptor.cpp
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/Floating.h
M clang/lib/AST/ByteCode/Integral.h
M clang/lib/AST/ByteCode/IntegralAP.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
M clang/lib/AST/ByteCode/InterpState.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ByteCode/PrimType.h
M clang/lib/AST/ByteCode/Program.h
M clang/lib/AST/Decl.cpp
M clang/lib/AST/ExprCXX.cpp
M clang/lib/AST/OpenMPClause.cpp
M clang/lib/AST/StmtOpenMP.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/AST/Type.cpp
M clang/lib/Basic/Targets/PPC.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenCall.h
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp
M clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenStmt.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CIR/CodeGen/CIRGenValue.h
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/Transforms/CIRSimplify.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/TargetInfo.cpp
M clang/lib/CodeGen/TargetInfo.h
M clang/lib/CodeGen/Targets/AMDGPU.cpp
M clang/lib/CodeGen/Targets/NVPTX.cpp
M clang/lib/CodeGen/Targets/SPIR.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/BareMetal.cpp
M clang/lib/Driver/ToolChains/BareMetal.h
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Driver/ToolChains/HIPAMD.h
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/lib/Headers/CMakeLists.txt
M clang/lib/Headers/bmiintrin.h
R clang/lib/Headers/cuda_wrappers/bits/c++config.h
M clang/lib/Headers/immintrin.h
M clang/lib/Headers/keylockerintrin.h
M clang/lib/Headers/x86gprintrin.h
M clang/lib/Headers/x86intrin.h
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Sema/SemaCast.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaExprObjC.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/StaticAnalyzer/Checkers/DynamicTypePropagation.cpp
M clang/lib/StaticAnalyzer/Core/Z3CrosscheckVisitor.cpp
M clang/test/AST/ByteCode/builtin-bit-cast-long-double.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
A clang/test/AST/HLSL/vk.spec-constant.usage.hlsl
M clang/test/CIR/CodeGen/builtin_call.cpp
M clang/test/CIR/CodeGen/call.c
M clang/test/CIR/CodeGen/complex.cpp
M clang/test/CIR/CodeGen/string-literals.c
A clang/test/CIR/CodeGen/string-literals.cpp
M clang/test/CIR/CodeGen/struct.c
M clang/test/CIR/IR/call.cir
A clang/test/CIR/Transforms/vector-splat.cir
M clang/test/CodeGen/builtin_vectorelements.c
M clang/test/CodeGenCXX/cxx11-thread-local-reference.cpp
M clang/test/CodeGenHLSL/builtins/firstbithigh.hlsl
M clang/test/CodeGenHLSL/builtins/firstbitlow.hlsl
R clang/test/CodeGenHLSL/inline-spirv/SpirvType.alignment.hlsl
R clang/test/CodeGenHLSL/inline-spirv/SpirvType.hlsl
M clang/test/CodeGenHLSL/semantics/SV_Position.ps.hlsl
A clang/test/CodeGenHLSL/vk-features/SpirvType.alignment.hlsl
A clang/test/CodeGenHLSL/vk-features/SpirvType.hlsl
A clang/test/CodeGenHLSL/vk-features/vk.spec-constant.hlsl
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/include/c++/8.2.1/.keep
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/lib/.keep
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/aarch64-none-elf/lib/crt0.o
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/bin/aarch64-none-elf-ld
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/crtbegin.o
R clang/test/Driver/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/crtend.o
R clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crt0.o
R clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crtbegin.o
R clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/aarch64-none-elf/lib/crtend.o
R clang/test/Driver/Inputs/basic_aarch64_nogcc_tree/bin/aarch64-none-elf-ld
R clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/include/c++/8.2.1/.keep
R clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/lib/.keep
R clang/test/Driver/Inputs/basic_arm_gcc_tree/armv6m-none-eabi/lib/crt0.o
R clang/test/Driver/Inputs/basic_arm_gcc_tree/bin/armv6m-none-eabi-ld
R clang/test/Driver/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/crtbegin.o
R clang/test/Driver/Inputs/basic_arm_gcc_tree/lib/gcc/armv6m-none-eabi/8.2.1/crtend.o
R clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crt0.o
R clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crtbegin.o
R clang/test/Driver/Inputs/basic_arm_nogcc_tree/armv6m-none-eabi/lib/crtend.o
R clang/test/Driver/Inputs/basic_arm_nogcc_tree/bin/armv6m-none-eabi-ld
R clang/test/Driver/aarch64-gnutools.c
R clang/test/Driver/aarch64-toolchain-extra.c
R clang/test/Driver/aarch64-toolchain.c
M clang/test/Driver/aix-shared-lib-tls-model-opt.c
M clang/test/Driver/aix-small-local-exec-dynamic-tls.c
R clang/test/Driver/arm-gnutools.c
R clang/test/Driver/arm-toolchain-extra.c
R clang/test/Driver/arm-toolchain.c
M clang/test/Driver/baremetal.cpp
R clang/test/Driver/check-no-multlib-warning.c
M clang/test/Driver/extend-variable-liveness.c
M clang/test/Driver/hip-runtime-libs-linux.hip
M clang/test/Driver/hip-thinlto.hip
M clang/test/Driver/openmp-offload-gpu.c
M clang/test/Driver/ppc-crbits.cpp
M clang/test/Driver/ppc-isa-features.cpp
M clang/test/Driver/print-supported-extensions-riscv.c
A clang/test/Driver/spirv-amd-toolchain.c
M clang/test/PCH/ignored-pch.c
M clang/test/Preprocessor/predefined-arch-macros.c
M clang/test/Preprocessor/riscv-target-features-andes.c
M clang/test/SemaCXX/builtin-is-constant-evaluated.cpp
M clang/test/SemaCXX/class.cpp
M clang/test/SemaCXX/cxx0x-class.cpp
M clang/test/SemaCXX/cxx2a-consteval.cpp
M clang/test/SemaCXX/exception-spec.cpp
A clang/test/SemaHLSL/vk.spec-constant.error.hlsl
M clang/test/SemaObjCXX/arc-type-conversion.mm
M clang/test/SemaTemplate/concepts-out-of-line-def.cpp
M clang/test/SemaTemplate/instantiate-static-var.cpp
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M compiler-rt/lib/builtins/CMakeLists.txt
M compiler-rt/lib/fuzzer/tests/CMakeLists.txt
M compiler-rt/lib/lsan/lsan_interceptors.cpp
M compiler-rt/lib/msan/msan_interceptors.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_malloc_mac.inc
M compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
M compiler-rt/lib/scudo/standalone/chunk.h
M compiler-rt/lib/scudo/standalone/combined.h
M compiler-rt/lib/scudo/standalone/report.cpp
M compiler-rt/lib/scudo/standalone/report.h
M compiler-rt/lib/tsan/rtl/tsan_platform.h
M compiler-rt/lib/tsan/rtl/tsan_rtl_access.cpp
M compiler-rt/test/fuzzer/uncaught-exception.test
A compiler-rt/test/sanitizer_common/TestCases/Linux/free_aligned_sized.c
A compiler-rt/test/sanitizer_common/TestCases/Linux/free_sized.c
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/include/flang/Semantics/dump-expr.h
M flang/include/flang/Support/Fortran-features.h
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/Builder/FIRBuilder.cpp
M flang/lib/Optimizer/CodeGen/LowerRepackArrays.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/Transforms/ControlFlowConverter.cpp
M flang/lib/Semantics/CMakeLists.txt
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/dump-expr.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/resolve-names.cpp
R flang/lib/Semantics/rewrite-directives.cpp
R flang/lib/Semantics/rewrite-directives.h
M flang/lib/Semantics/rewrite-parse-tree.cpp
M flang/lib/Support/Fortran-features.cpp
A flang/test/Fir/cfg-conversion-if.fir
M flang/test/Fir/fir-ops.fir
M flang/test/Fir/invalid.fir
A flang/test/HLFIR/fir-local-alloca-block.fir
A flang/test/Integration/cold_array_repacking.f90
A flang/test/Lower/OpenMP/Todo/declare-mapper-iterator.f90
R flang/test/Lower/OpenMP/Todo/omp-doconcurrent.f90
A flang/test/Lower/OpenMP/requires-admo-acqrel.f90
A flang/test/Lower/OpenMP/requires-admo-invalid1.f90
A flang/test/Lower/OpenMP/requires-admo-invalid2.f90
A flang/test/Lower/OpenMP/target-enter-data-default-openmp52.f90
M flang/test/Semantics/OpenMP/allocate-align01.f90
M flang/test/Semantics/OpenMP/allocate01.f90
M flang/test/Semantics/OpenMP/allocate02.f90
M flang/test/Semantics/OpenMP/allocate03.f90
M flang/test/Semantics/OpenMP/allocate05.f90
M flang/test/Semantics/OpenMP/allocate06.f90
M flang/test/Semantics/OpenMP/allocate09.f90
M flang/test/Semantics/OpenMP/atomic-update-only.f90
M flang/test/Semantics/OpenMP/atomic03.f90
M flang/test/Semantics/OpenMP/atomic04.f90
M flang/test/Semantics/OpenMP/clause-validity01.f90
M flang/test/Semantics/OpenMP/deprecation.f90
A flang/test/Semantics/OpenMP/do-concurrent-collapse.f90
M flang/test/Semantics/OpenMP/flush02.f90
M flang/test/Semantics/OpenMP/nested-barrier.f90
M flang/test/Semantics/OpenMP/nested-master.f90
M flang/test/Semantics/OpenMP/nested-teams.f90
M flang/test/Semantics/OpenMP/ordered-simd.f90
M flang/test/Semantics/OpenMP/parallel-master-goto.f90
R flang/test/Semantics/OpenMP/requires-atomic01.f90
R flang/test/Semantics/OpenMP/requires-atomic02.f90
M flang/test/Transforms/lower-repack-arrays.fir
M libc/cmake/modules/LLVMLibCCompileOptionRules.cmake
A libc/config/darwin/aarch64/config.json
M libc/config/darwin/aarch64/entrypoints.txt
M libc/config/darwin/aarch64/headers.txt
M libc/src/__support/FPUtil/FEnvImpl.h
M libc/src/__support/FPUtil/dyadic_float.h
M libc/src/__support/HashTable/CMakeLists.txt
M libc/src/__support/HashTable/randomness.h
M libc/src/__support/OSUtil/linux/CMakeLists.txt
A libc/src/__support/OSUtil/linux/getrandom.h
M libc/src/__support/macros/optimization.h
M libc/src/__support/wchar/character_converter.cpp
M libc/src/setjmp/CMakeLists.txt
A libc/src/setjmp/darwin/CMakeLists.txt
A libc/src/setjmp/darwin/sigsetjmp_epilogue.cpp
M libc/src/sys/random/linux/getrandom.cpp
M libc/test/src/CMakeLists.txt
M libc/test/src/stdio/CMakeLists.txt
M libc/test/src/stdio/fdopen_test.cpp
M libc/test/src/stdio/fgetc_test.cpp
M libc/test/src/stdio/fgetc_unlocked_test.cpp
M libc/test/src/stdio/fgets_test.cpp
M libc/test/src/stdio/fileop_test.cpp
M libc/test/src/stdio/fopencookie_test.cpp
M libc/test/src/stdio/remove_test.cpp
M libc/test/src/stdio/rename_test.cpp
M libc/test/src/stdio/setvbuf_test.cpp
M libc/test/src/stdio/unlocked_fileop_test.cpp
M libc/test/src/stdlib/StrtolTest.h
M libc/test/src/stdlib/strtold_test.cpp
M libcxx/docs/ABIGuarantees.rst
M libcxx/docs/FeatureTestMacroTable.rst
M libcxx/docs/ReleaseNotes/21.rst
M libcxx/include/__algorithm/for_each.h
M libcxx/include/__algorithm/for_each_n.h
M libcxx/include/__algorithm/ranges_for_each.h
M libcxx/include/__algorithm/ranges_for_each_n.h
M libcxx/include/__iterator/iterator_traits.h
M libcxx/include/__math/abs.h
M libcxx/include/__memory/pointer_traits.h
M libcxx/include/experimental/iterator
M libcxx/include/forward_list
M libcxx/include/fstream
M libcxx/include/list
M libcxx/include/math.h
M libcxx/include/mutex
M libcxx/include/shared_mutex
M libcxx/include/stdlib.h
M libcxx/include/streambuf
M libcxx/include/version
M libcxx/test/benchmarks/algorithms/nonmodifying/for_each.bench.cpp
M libcxx/test/benchmarks/algorithms/nonmodifying/for_each_n.bench.cpp
M libcxx/test/libcxx/odr_signature.exceptions.sh.cpp
M libcxx/test/libcxx/odr_signature.hardening.sh.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.foreach/ranges.for_each.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.foreach/ranges.for_each_n.pass.cpp
M libcxx/test/std/containers/sequences/list/compare.pass.cpp
M libcxx/test/std/containers/sequences/list/compare.three_way.pass.cpp
M libcxx/test/std/containers/sequences/list/get_allocator.pass.cpp
M libcxx/test/std/containers/sequences/list/incomplete_type.pass.cpp
M libcxx/test/std/containers/sequences/list/iterators.pass.cpp
M libcxx/test/std/containers/sequences/list/list.capacity/empty.pass.cpp
M libcxx/test/std/containers/sequences/list/list.capacity/max_size.pass.cpp
M libcxx/test/std/containers/sequences/list/list.capacity/resize_size.pass.cpp
M libcxx/test/std/containers/sequences/list/list.capacity/resize_size_value.pass.cpp
M libcxx/test/std/containers/sequences/list/list.capacity/size.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/assign_copy.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/assign_initializer_list.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/assign_move.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/copy.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/copy_alloc.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/default.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/default_stack_alloc.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/from_range.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/initializer_list.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/initializer_list_alloc.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/input_iterator.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/move.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/move_alloc.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/op_equal_initializer_list.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/size_type.pass.cpp
M libcxx/test/std/containers/sequences/list/list.cons/size_value_alloc.pass.cpp
M libcxx/test/std/containers/sequences/list/list.erasure/erase.pass.cpp
M libcxx/test/std/containers/sequences/list/list.erasure/erase_if.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/append_range.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/assign_range.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/clear.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/emplace.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/emplace_back.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/emplace_front.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/erase_iter.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/erase_iter_iter.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/insert_iter_initializer_list.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/insert_iter_iter_iter.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/insert_iter_rvalue.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/insert_iter_size_value.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/insert_iter_value.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/insert_range.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/pop_back.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/pop_front.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/prepend_range.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/push_back.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/push_back_rvalue.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/push_front.pass.cpp
M libcxx/test/std/containers/sequences/list/list.modifiers/push_front_rvalue.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/merge.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/merge_comp.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/remove.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/remove_if.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/reverse.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/sort.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/sort_comp.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/splice_pos_list.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/splice_pos_list_iter.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/splice_pos_list_iter_iter.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/unique.pass.cpp
M libcxx/test/std/containers/sequences/list/list.ops/unique_pred.pass.cpp
M libcxx/test/std/containers/sequences/list/list.special/swap.pass.cpp
M libcxx/test/std/containers/sequences/list/list.special/swap_noexcept.pass.cpp
M libcxx/test/std/input.output/stream.buffers/streambuf/streambuf.protected/streambuf.get.area/setg.assert.pass.cpp
M libcxx/test/std/input.output/stream.buffers/streambuf/streambuf.protected/streambuf.put.area/setp.assert.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/list.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
M libcxx/test/std/numerics/c.math/abs.pass.cpp
M libcxx/test/std/numerics/c.math/abs.verify.cpp
M libcxx/test/std/utilities/format/format.functions/escaped_output.unicode.pass.cpp
M libcxx/test/std/utilities/format/format.functions/fill.unicode.pass.cpp
M libcxx/test/support/min_allocator.h
M libcxx/utils/generate_feature_test_macro_components.py
M lldb/examples/python/crashlog.py
M lldb/include/lldb/Core/Debugger.h
M lldb/include/lldb/Core/DemangledNameInfo.h
M lldb/include/lldb/Core/PluginManager.h
M lldb/source/Breakpoint/Breakpoint.cpp
M lldb/source/Core/CoreProperties.td
M lldb/source/Core/Debugger.cpp
M lldb/source/Core/DynamicLoader.cpp
M lldb/source/Core/PluginManager.cpp
M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
M lldb/source/Plugins/Process/minidump/MinidumpParser.cpp
M lldb/source/Plugins/Process/minidump/MinidumpParser.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.h
M lldb/source/ValueObject/DILParser.cpp
M lldb/test/API/commands/frame/var-dil/basics/ArraySubscript/TestFrameVarDILArraySubscript.py
M lldb/test/API/commands/frame/var-dil/basics/ArraySubscript/main.cpp
A lldb/test/API/commands/plugin/TestPlugin.py
M lldb/test/API/commands/register/register/aarch64_mte_ctrl_register/TestMTECtrlRegister.py
M lldb/test/API/python_api/watchpoint/watchlocation/TestTargetWatchAddress.py
A lldb/test/API/terminal/TestDisabledBreakpoints.py
M lldb/test/API/tools/lldb-dap/memory/TestDAP_memory.py
M lldb/test/Shell/Commands/command-plugin-list.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/altered_threadState.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/json.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/no_threadState.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/skipped_status_interactive_crashlog.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/text.test
M lldb/test/Shell/SymbolFile/DWARF/x86/explicit-member-function-quals.cpp
M lldb/tools/lldb-dap/Handler/ReadMemoryRequestHandler.cpp
M lldb/tools/lldb-dap/Handler/RequestHandler.h
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
M lldb/unittests/Core/MangledTest.cpp
M lldb/unittests/DAP/ProtocolTypesTest.cpp
M lldb/unittests/SymbolFile/DWARF/DWARFASTParserClangTests.cpp
M llvm/cmake/modules/AddLLVM.cmake
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/CommandGuide/llvm-opt-report.rst
M llvm/docs/NVPTXUsage.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/docs/Remarks.rst
M llvm/include/llvm-c/ExecutionEngine.h
M llvm/include/llvm/Analysis/HashRecognize.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/BinaryFormat/DXContainer.h
M llvm/include/llvm/BinaryFormat/DXContainerConstants.def
M llvm/include/llvm/BinaryFormat/Dwarf.h
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/CodeGen/FunctionLoweringInfo.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/include/llvm/CodeGen/SDPatternMatch.h
A llvm/include/llvm/DebugInfo/DWARF/DWARFCFIPrinter.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFCFIProgram.h
M llvm/include/llvm/DebugInfo/LogicalView/Core/LVElement.h
M llvm/include/llvm/DebugInfo/LogicalView/Core/LVScope.h
M llvm/include/llvm/DebugInfo/LogicalView/Core/LVSupport.h
M llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h
M llvm/include/llvm/Frontend/HLSL/HLSLRootSignatureUtils.h
M llvm/include/llvm/IR/IRBuilder.h
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/PatternMatch.h
M llvm/include/llvm/IR/RuntimeLibcalls.h
M llvm/include/llvm/MC/MCTargetOptions.h
M llvm/include/llvm/Object/ELF.h
M llvm/include/llvm/Remarks/RemarkFormat.h
M llvm/include/llvm/Remarks/RemarkLinker.h
M llvm/include/llvm/Remarks/RemarkParser.h
M llvm/include/llvm/Remarks/YAMLRemarkSerializer.h
M llvm/include/llvm/Support/CodeGen.h
M llvm/include/llvm/Target/CGPassBuilderOption.h
M llvm/include/llvm/Target/TargetLoweringObjectFile.h
M llvm/include/llvm/Target/TargetMachine.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/include/llvm/TargetParser/CMakeLists.txt
M llvm/include/llvm/TargetParser/PPCTargetParser.h
M llvm/include/llvm/TargetParser/TargetParser.h
M llvm/include/llvm/Transforms/IPO/Attributor.h
M llvm/include/llvm/Transforms/Scalar/JumpThreading.h
M llvm/include/llvm/Transforms/Utils/SCCPSolver.h
M llvm/lib/Analysis/HashRecognize.cpp
M llvm/lib/Analysis/IR2Vec.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/BinaryFormat/Dwarf.cpp
M llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/DebugInfo/DWARF/CMakeLists.txt
A llvm/lib/DebugInfo/DWARF/DWARFCFIPrinter.cpp
M llvm/lib/DebugInfo/DWARF/DWARFCFIProgram.cpp
M llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp
M llvm/lib/Frontend/HLSL/HLSLRootSignatureUtils.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/DiagnosticInfo.cpp
M llvm/lib/IR/IRBuilder.cpp
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Object/IRSymtab.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Remarks/BitstreamRemarkParser.cpp
M llvm/lib/Remarks/BitstreamRemarkParser.h
M llvm/lib/Remarks/RemarkFormat.cpp
M llvm/lib/Remarks/RemarkLinker.cpp
M llvm/lib/Remarks/RemarkParser.cpp
M llvm/lib/Remarks/RemarkSerializer.cpp
M llvm/lib/Remarks/RemarkStreamer.cpp
M llvm/lib/Remarks/YAMLRemarkParser.cpp
M llvm/lib/Remarks/YAMLRemarkParser.h
M llvm/lib/Remarks/YAMLRemarkSerializer.cpp
M llvm/lib/Support/BLAKE3/CMakeLists.txt
M llvm/lib/Support/Unix/Process.inc
M llvm/lib/Target/AArch64/AArch64.td
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64Processors.td
A llvm/lib/Target/AArch64/AArch64SchedA320.td
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
M llvm/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMAsmPrinter.h
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
M llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
M llvm/lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp
M llvm/lib/Target/AVR/AVRAsmPrinter.cpp
M llvm/lib/Target/AVR/AVRTargetMachine.cpp
M llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
M llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.cpp
M llvm/lib/Target/AVR/TargetInfo/AVRTargetInfo.cpp
M llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
M llvm/lib/Target/BPF/BPFAsmPrinter.cpp
M llvm/lib/Target/BPF/BPFTargetMachine.cpp
M llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
M llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp
M llvm/lib/Target/BPF/TargetInfo/BPFTargetInfo.cpp
M llvm/lib/Target/DirectX/DXILPrepare.cpp
M llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
M llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
M llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp
M llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
M llvm/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp
M llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
M llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp
M llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp
M llvm/lib/Target/Lanai/LanaiTargetMachine.cpp
M llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp
M llvm/lib/Target/Lanai/TargetInfo/LanaiTargetInfo.cpp
M llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
M llvm/lib/Target/LoongArch/Disassembler/LoongArchDisassembler.cpp
M llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
M llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp
M llvm/lib/Target/LoongArch/TargetInfo/LoongArchTargetInfo.cpp
M llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
M llvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp
M llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp
M llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp
M llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
M llvm/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp
M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
M llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.cpp
M llvm/lib/Target/Mips/MipsTargetMachine.cpp
M llvm/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp
M llvm/lib/Target/NVPTX/NVPTX.td
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
M llvm/lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.cpp
M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
M llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
M llvm/lib/Target/PowerPC/PPC.td
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.h
M llvm/lib/Target/PowerPC/PPCInstrMMA.td
M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVCallingConv.td
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCTargetDesc.cpp
M llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/SPIRV/TargetInfo/SPIRVTargetInfo.cpp
M llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
M llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
M llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
M llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
M llvm/lib/Target/Sparc/SparcTargetMachine.cpp
M llvm/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp
M llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
M llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
M llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
M llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
M llvm/lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp
M llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
M llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp
M llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.cpp
M llvm/lib/Target/VE/TargetInfo/VETargetInfo.cpp
M llvm/lib/Target/VE/VEAsmPrinter.cpp
M llvm/lib/Target/VE/VEISelLowering.cpp
M llvm/lib/Target/VE/VETargetMachine.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
M llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp
M llvm/lib/Target/WebAssembly/TargetInfo/WebAssemblyTargetInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86AsmPrinter.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
M llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
M llvm/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp
M llvm/lib/Target/XCore/XCoreAsmPrinter.cpp
M llvm/lib/Target/XCore/XCoreTargetMachine.cpp
M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
M llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.h
M llvm/lib/Target/Xtensa/XtensaFeatures.td
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
M llvm/lib/Target/Xtensa/XtensaSubtarget.h
M llvm/lib/TargetParser/PPCTargetParser.cpp
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/lib/Transforms/IPO/Attributor.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/IPO/ElimAvailExtern.cpp
M llvm/lib/Transforms/IPO/FunctionSpecialization.cpp
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
M llvm/lib/Transforms/IPO/SCCP.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
M llvm/lib/Transforms/Utils/LoopPeel.cpp
M llvm/lib/Transforms/Utils/PredicateInfo.cpp
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/test/Analysis/CostModel/AMDGPU/canonicalize.ll
M llvm/test/Analysis/CostModel/AMDGPU/copysign.ll
A llvm/test/Analysis/CostModel/AMDGPU/maximumnum.ll
A llvm/test/Analysis/CostModel/AMDGPU/minimumnum.ll
A llvm/test/Analysis/CostModel/AMDGPU/special-argument-intrinsics.ll
M llvm/test/Analysis/HashRecognize/cyclic-redundancy-check.ll
M llvm/test/Analysis/ValueTracking/phi-known-bits.ll
A llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmov-gpr32.ll
R llvm/test/CodeGen/AArch64/arm64-zero-cycle-regmov.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-splat-scalable.ll
M llvm/test/CodeGen/AArch64/min-jump-table.ll
M llvm/test/CodeGen/AArch64/stack-hazard.ll
A llvm/test/CodeGen/AArch64/sve2p1-vector-shuffles.ll
M llvm/test/CodeGen/AArch64/trampoline.ll
A llvm/test/CodeGen/AArch64/vector-ldst-offset.ll
M llvm/test/CodeGen/AArch64/zext-to-tbl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
A llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-gfx12-fake16.mir
A llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-gfx12-true16.mir
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/insert-skips-gfx12.mir
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-fake16.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
A llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/DirectX/llc-vector-load-scalarize.ll
A llvm/test/CodeGen/DirectX/noop_bitcast_global_array_type.ll
M llvm/test/CodeGen/NVPTX/sm-version.ll
M llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll
M llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
M llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
M llvm/test/CodeGen/PowerPC/aix-cc-byval-mir.ll
M llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-mir.ll
M llvm/test/CodeGen/PowerPC/aix-vec-arg-spills.ll
M llvm/test/CodeGen/PowerPC/aix-vector-vararg-caller.ll
M llvm/test/CodeGen/PowerPC/aix-vector-vararg-fixed-caller.ll
A llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg-mir.ll
M llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
A llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg-mir.ll
M llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll
M llvm/test/CodeGen/PowerPC/all-atomics.ll
M llvm/test/CodeGen/PowerPC/dmr-spill.ll
A llvm/test/CodeGen/PowerPC/dmrp-spill.ll
M llvm/test/CodeGen/PowerPC/f128-arith.ll
M llvm/test/CodeGen/PowerPC/loop-comment.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/fallback.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/features-info.ll
A llvm/test/CodeGen/RISCV/icmp-non-byte-sized.ll
M llvm/test/CodeGen/RISCV/interrupt-attr.ll
M llvm/test/CodeGen/RISCV/memcmp-optsize.ll
M llvm/test/CodeGen/RISCV/memcmp.ll
M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/get_vector_length.ll
M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
A llvm/test/CodeGen/RISCV/rvv/interrupt-attr-nocall.ll
M llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/legalize-store-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
M llvm/test/CodeGen/RISCV/shifts.ll
A llvm/test/CodeGen/RISCV/xqcibm-cto-clo.ll
M llvm/test/CodeGen/RISCV/xqcibm-extract.ll
A llvm/test/CodeGen/SPIRV/linkage/link-attribute-vk.ll
A llvm/test/CodeGen/SystemZ/fake-use-size.ll
M llvm/test/CodeGen/Thumb2/mve-shuffle.ll
M llvm/test/CodeGen/Thumb2/mve-vld3.ll
M llvm/test/CodeGen/Thumb2/schedm7-hazard.ll
A llvm/test/CodeGen/X86/fold-masked-merge-demorgan.ll
M llvm/test/CodeGen/X86/kcfi-arity.ll
M llvm/test/CodeGen/X86/remarks-section.ll
M llvm/test/Instrumentation/AddressSanitizer/asan-masked-load-store.ll
M llvm/test/Instrumentation/AddressSanitizer/asan-vp-load-store.ll
M llvm/test/Instrumentation/AddressSanitizer/vector-load-store.ll
M llvm/test/Instrumentation/BoundsChecking/simple.ll
M llvm/test/Instrumentation/HWAddressSanitizer/vector-load-store.ll
M llvm/test/Instrumentation/MemorySanitizer/vector-load-store.ll
M llvm/test/Instrumentation/MemorySanitizer/vscale.ll
M llvm/test/Instrumentation/ThreadSanitizer/atomic-non-integer.ll
A llvm/test/MC/Disassembler/Xtensa/coprocessor.txt
A llvm/test/MC/Disassembler/Xtensa/debug.txt
A llvm/test/MC/Disassembler/Xtensa/exception.txt
A llvm/test/MC/Disassembler/Xtensa/highinterrupts.txt
A llvm/test/MC/Disassembler/Xtensa/interrupt.txt
A llvm/test/MC/Disassembler/Xtensa/prid.txt
A llvm/test/MC/Disassembler/Xtensa/timer.txt
A llvm/test/MC/RISCV/xandesvbfhcvt-valid.s
M llvm/test/MC/RISCV/xqciac-valid.s
M llvm/test/MC/Xtensa/Core/processor-control.s
A llvm/test/MC/Xtensa/coprocessor.s
A llvm/test/MC/Xtensa/debug-invalid.s
A llvm/test/MC/Xtensa/debug.s
A llvm/test/MC/Xtensa/exception.s
A llvm/test/MC/Xtensa/highinterrupts.s
A llvm/test/MC/Xtensa/interrupt.s
A llvm/test/MC/Xtensa/prid.s
A llvm/test/MC/Xtensa/timer.s
R llvm/test/Transforms/Attributor/AMDGPU/tag-invariant-loads.ll
M llvm/test/Transforms/Attributor/dereferenceable-1.ll
M llvm/test/Transforms/Attributor/value-simplify-local-remote.ll
A llvm/test/Transforms/EliminateAvailableExternally/convert-global-variables-to-local.ll
M llvm/test/Transforms/GVN/opt-remarks.ll
M llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-counting-elems.ll
M llvm/test/Transforms/InstCombine/AMDGPU/image-d16.ll
M llvm/test/Transforms/InstCombine/X86/x86-vector-shifts.ll
A llvm/test/Transforms/InstCombine/bitcast-known-bits.ll
A llvm/test/Transforms/InstCombine/fmul-tan-cos.ll
M llvm/test/Transforms/InstCombine/gep-vector.ll
M llvm/test/Transforms/InstCombine/gepofconstgepi8.ll
M llvm/test/Transforms/InstCombine/getelementptr.ll
M llvm/test/Transforms/InstCombine/icmp-gep.ll
M llvm/test/Transforms/InstCombine/masked_intrinsics.ll
M llvm/test/Transforms/InstCombine/opaque-ptr.ll
M llvm/test/Transforms/InstCombine/scalable-vector-array.ll
M llvm/test/Transforms/InstCombine/scalable-vector-struct.ll
M llvm/test/Transforms/InstCombine/sub-gep.ll
A llvm/test/Transforms/InstCombine/sub-sext-add.ll
M llvm/test/Transforms/InstCombine/vp-reverse.ll
M llvm/test/Transforms/InstCombine/vscale_gep.ll
M llvm/test/Transforms/LICM/call-hoisting.ll
M llvm/test/Transforms/LICM/funclet.ll
M llvm/test/Transforms/LoopUnroll/peel-last-iteration-minmax.ll
M llvm/test/Transforms/LoopVectorize/AArch64/clamped-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/divs-with-scalable-vfs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/eliminate-tail-predication.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/AArch64/gather-do-not-vectorize-addressing.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll
M llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_prefer_scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
A llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-interleave.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
M llvm/test/Transforms/LoopVectorize/AArch64/pr60831-sve-inv-store-crash.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-avoid-scalarization.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-reduction-inloop-cond.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
M llvm/test/Transforms/LoopVectorize/AArch64/simple_early_exit.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-inloop-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-no-remaining-iterations.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-strict-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-extract-last-veclane.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-fneg.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inv-store.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-live-out-pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-multiexit.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-runtime-check-size-based-threshold.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-forced.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-optsize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-unroll.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-vscale-based-trip-counts.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-gep.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-too-many-deps.ll
M llvm/test/Transforms/LoopVectorize/AArch64/tail-folding-styles.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-remove-loop-region.ll
M llvm/test/Transforms/LoopVectorize/AArch64/uniform-args-call-variants.ll
M llvm/test/Transforms/LoopVectorize/AArch64/wider-VF-for-callinst.ll
A llvm/test/Transforms/LoopVectorize/ARM/mve-reductions-interleave.ll
M llvm/test/Transforms/LoopVectorize/ARM/optsize_minsize.ll
M llvm/test/Transforms/LoopVectorize/RISCV/bf16.ll
M llvm/test/Transforms/LoopVectorize/RISCV/blend-any-of-reduction-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/defaults.ll
M llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
M llvm/test/Transforms/LoopVectorize/RISCV/f16.ll
M llvm/test/Transforms/LoopVectorize/RISCV/first-order-recurrence-scalable-vf1.ll
M llvm/test/Transforms/LoopVectorize/RISCV/fminimumnum.ll
M llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-masked-access.ll
M llvm/test/Transforms/LoopVectorize/RISCV/lmul.ll
M llvm/test/Transforms/LoopVectorize/RISCV/low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/RISCV/mask-index-type.ll
M llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll
M llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
M llvm/test/Transforms/LoopVectorize/RISCV/remark-reductions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse-output.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/RISCV/safe-dep-distance.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-basics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-tailfold.ll
M llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-bin-unary-ops-args.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cond-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-div.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-interleave.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-intermediate-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-iv32.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-known-no-overflow.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-masked-loadstore.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-ordered-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-safe-dep-distance.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-uniform-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-vp-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/X86/constant-fold.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/outer_loop_test1_no_explicit_vect_width.ll
M llvm/test/Transforms/LoopVectorize/X86/scatter_crash.ll
M llvm/test/Transforms/LoopVectorize/branch-weights.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-any-of-reductions.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-scalable-vf1.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/load-deref-pred-poison-ub-ops-feeding-pointer.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_scalable.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
M llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/scalable-inductions.ll
M llvm/test/Transforms/LoopVectorize/scalable-iv-outside-user.ll
M llvm/test/Transforms/LoopVectorize/scalable-lifetime.ll
M llvm/test/Transforms/LoopVectorize/scalable-loop-unpredicated-body-scalar-tail.ll
M llvm/test/Transforms/LoopVectorize/scalable-reduction-inloop.ll
M llvm/test/Transforms/LoopVectorize/scalable-trunc-min-bitwidth.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit_live_outs.ll
M llvm/test/Transforms/LoopVectorize/uniform-blend.ll
M llvm/test/Transforms/LoopVectorize/vectorize-force-tail-with-evl.ll
M llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll
A llvm/test/Transforms/LowerMatrixIntrinsics/phi.ll
M llvm/test/Transforms/LowerMatrixIntrinsics/propagate-backwards-unsupported.ll
M llvm/test/Transforms/LowerTypeTests/blockaddress-2.ll
M llvm/test/Transforms/LowerTypeTests/cfi-icall-alias.ll
M llvm/test/Transforms/LowerTypeTests/export-alias.ll
M llvm/test/Transforms/LowerTypeTests/export-icall.ll
M llvm/test/Transforms/LowerTypeTests/function-disjoint.ll
M llvm/test/Transforms/LowerTypeTests/function.ll
M llvm/test/Transforms/LowerTypeTests/icall-branch-funnel.ll
M llvm/test/Transforms/LowerTypeTests/pr37625.ll
M llvm/test/Transforms/LowerTypeTests/section.ll
M llvm/test/Transforms/MemCpyOpt/memcpy-memcpy-offset.ll
M llvm/test/Transforms/MemCpyOpt/variable-sized-memcpy-memcpy.ll
M llvm/test/Transforms/MemCpyOpt/vscale-crashes.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/sve-interleave-vectorization.ll
A llvm/test/Transforms/PhaseOrdering/X86/fmaddsub.ll
M llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-exp.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f16.ll
A llvm/test/Verifier/NVPTX/fence-proxy.tensormap.ll
M llvm/test/Verifier/NVPTX/setmaxnreg.ll
A llvm/test/tools/llvm-mca/AArch64/Cortex/A320-basic-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Cortex/A320-neon-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Cortex/A320-sve-instructions.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/floating-point.s
M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.s
A llvm/test/tools/llvm-remarkutil/Inputs/broken-remark-magic.bitstream
M llvm/test/tools/llvm-remarkutil/annotation-count.test
A llvm/test/tools/llvm-remarkutil/broken-bitstream-remark-magic.test
M llvm/test/tools/llvm-remarkutil/empty-file.test
M llvm/test/tools/llvm-remarkutil/instruction-count.test
M llvm/test/tools/llvm-remarkutil/instruction-mix.test
M llvm/test/tools/llvm-remarkutil/size-diff/no-difference.test
M llvm/tools/llvm-jitlink/llvm-jitlink-executor/CMakeLists.txt
M llvm/tools/llvm-readobj/DwarfCFIEHPrinter.h
M llvm/tools/llvm-remarkutil/RemarkUtilHelpers.h
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
M llvm/unittests/Frontend/CMakeLists.txt
M llvm/unittests/Frontend/HLSLRootSignatureDumpTest.cpp
A llvm/unittests/Frontend/HLSLRootSignatureRangesTest.cpp
M llvm/unittests/Remarks/RemarksLinkingTest.cpp
M llvm/unittests/Remarks/YAMLRemarksParsingTest.cpp
M llvm/unittests/Remarks/YAMLRemarksSerializerTest.cpp
M llvm/unittests/Target/AArch64/CMakeLists.txt
M llvm/unittests/Target/LoongArch/CMakeLists.txt
M llvm/unittests/Target/RISCV/CMakeLists.txt
M llvm/unittests/Target/SPIRV/CMakeLists.txt
M llvm/unittests/Target/VE/CMakeLists.txt
M llvm/unittests/Target/WebAssembly/CMakeLists.txt
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/utils/TableGen/Basic/CMakeLists.txt
A llvm/utils/TableGen/Basic/TargetFeaturesEmitter.cpp
A llvm/utils/TableGen/Basic/TargetFeaturesEmitter.h
M llvm/utils/TableGen/CompressInstEmitter.cpp
M llvm/utils/TableGen/SubtargetEmitter.cpp
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/cppcoreguidelines/BUILD.gn
M llvm/utils/gn/secondary/lldb/test/BUILD.gn
M llvm/utils/gn/secondary/llvm/include/llvm/Config/BUILD.gn
M llvm/utils/gn/secondary/llvm/include/llvm/TargetParser/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/DebugInfo/DWARF/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/Mips/MCTargetDesc/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Frontend/BUILD.gn
M llvm/utils/gn/secondary/llvm/utils/TableGen/Basic/BUILD.gn
M mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.h
M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationOps.td
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationTypeInterfaces.h
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationTypeInterfaces.td
M mlir/include/mlir/Dialect/Bufferization/IR/UnstructuredControlFlow.h
M mlir/include/mlir/Dialect/ControlFlow/IR/ControlFlowOps.td
M mlir/include/mlir/Dialect/EmitC/IR/CMakeLists.txt
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.h
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
A mlir/include/mlir/Dialect/EmitC/IR/EmitCInterfaces.h
A mlir/include/mlir/Dialect/EmitC/IR/EmitCInterfaces.td
R mlir/include/mlir/Dialect/EmitC/IR/EmitCTraits.h
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td
M mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
M mlir/include/mlir/Dialect/Linalg/Utils/Utils.h
M mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.h
M mlir/include/mlir/Dialect/Mesh/Transforms/Passes.h
M mlir/include/mlir/Dialect/Mesh/Transforms/Passes.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/IR/BuiltinOps.td
M mlir/include/mlir/IR/OpBase.td
M mlir/include/mlir/IR/Operation.h
M mlir/include/mlir/Interfaces/ControlFlowInterfaces.h
M mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
M mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/lib/Conversion/ControlFlowToLLVM/ControlFlowToLLVM.cpp
M mlir/lib/Conversion/FuncToLLVM/FuncToLLVM.cpp
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
M mlir/lib/Conversion/GPUToSPIRV/GPUToSPIRV.cpp
M mlir/lib/Dialect/AMDGPU/Transforms/EmulateAtomics.cpp
M mlir/lib/Dialect/AMDGPU/Transforms/ResolveStridedMetadata.cpp
M mlir/lib/Dialect/AMDGPU/Transforms/TransferReadToLoad.cpp
M mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/lib/Dialect/Arith/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationDialect.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
A mlir/lib/Dialect/Bufferization/IR/BufferizationTypeInterfaces.cpp
M mlir/lib/Dialect/Bufferization/IR/CMakeLists.txt
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
M mlir/lib/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/ControlFlow/IR/ControlFlowOps.cpp
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
M mlir/lib/Dialect/EmitC/Transforms/FormExpressions.cpp
M mlir/lib/Dialect/EmitC/Transforms/Transforms.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/ConvertToDestinationStyle.cpp
M mlir/lib/Dialect/Linalg/Transforms/Padding.cpp
M mlir/lib/Dialect/Linalg/Utils/Utils.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandOps.cpp
M mlir/lib/Dialect/Mesh/IR/MeshOps.cpp
M mlir/lib/Dialect/Mesh/Transforms/ShardingPropagation.cpp
M mlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Shape/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseGPUCodegen.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorCodegen.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparsificationAndBufferizationPass.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenUtils.cpp
M mlir/lib/Dialect/Tensor/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
M mlir/lib/Interfaces/ControlFlowInterfaces.cpp
M mlir/lib/TableGen/Operator.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMIRToLLVMTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
M mlir/test/CMakeLists.txt
M mlir/test/Conversion/AMDGPUToROCDL/mfma-gfx950.mlir
M mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
M mlir/test/Conversion/ControlFlowToLLVM/branch.mlir
M mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
M mlir/test/Conversion/GPUToSPIRV/shuffle.mlir
M mlir/test/Dialect/Affine/constant-fold.mlir
M mlir/test/Dialect/Arith/canonicalize.mlir
M mlir/test/Dialect/Arith/ops.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-bufferize.mlir
M mlir/test/Dialect/ControlFlow/canonicalize.mlir
M mlir/test/Dialect/ControlFlow/invalid.mlir
M mlir/test/Dialect/ControlFlow/ops.mlir
M mlir/test/Dialect/Linalg/mesh-spmdization.mlir
M mlir/test/Dialect/Linalg/transform-op-pad.mlir
M mlir/test/Dialect/MemRef/expand-ops.mlir
A mlir/test/Dialect/Mesh/backward-sharding-propagation.mlir
A mlir/test/Dialect/Mesh/forward-backward-sharding-propagation.mlir
A mlir/test/Dialect/Mesh/forward-sharding-propagation.mlir
M mlir/test/Dialect/Mesh/spmdization.mlir
M mlir/test/Dialect/Tensor/mesh-spmdization.mlir
M mlir/test/Dialect/Tosa/constant_folding.mlir
M mlir/test/Dialect/Vector/constant-fold.mlir
M mlir/test/Dialect/Vector/invalid.mlir
M mlir/test/Dialect/Vector/ops.mlir
A mlir/test/Dialect/Vector/single-fold.mlir
M mlir/test/Dialect/XeGPU/invalid.mlir
A mlir/test/Dialect/XeGPU/layout.mlir
M mlir/test/Dialect/XeGPU/ops.mlir
M mlir/test/Dialect/XeGPU/subgroup-map-propagation.mlir
M mlir/test/Dialect/XeGPU/xegpu-blocking.mlir
M mlir/test/Dialect/XeGPU/xegpu-unroll-patterns.mlir
A mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-elemwise.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-rr.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir
M mlir/test/Integration/GPU/CUDA/dump-ptx.mlir
M mlir/test/Target/LLVMIR/Import/metadata-profiling.ll
M mlir/test/Target/LLVMIR/llvmir-invalid.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
M mlir/test/Target/SPIRV/constant.mlir
M mlir/test/Transforms/constant-fold-debuginfo.mlir
M mlir/test/Transforms/constant-fold.mlir
M mlir/test/lib/Dialect/Test/TestOpDefs.cpp
M mlir/test/lib/Dialect/Test/TestOps.h
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/test/lib/Dialect/Test/TestTypeDefs.td
M mlir/test/lib/Dialect/Test/TestTypes.cpp
M mlir/test/lib/Dialect/XeGPU/TestXeGPUTransforms.cpp
M mlir/test/lib/Transforms/CMakeLists.txt
R mlir/test/lib/Transforms/TestConstantFold.cpp
A mlir/test/lib/Transforms/TestSingleFold.cpp
M mlir/test/lit.cfg.py
R mlir/test/lit.local.cfg
M mlir/test/lit.site.cfg.py.in
M mlir/tools/mlir-opt/mlir-opt.cpp
M mlir/tools/mlir-tblgen/OpFormatGen.cpp
A offload/cmake/caches/AMDGPULibcBot.cmake
M runtimes/CMakeLists.txt
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
Fixes
Created using spr 1.3.5
Compare: https://github.com/llvm/llvm-project/compare/7cf73b248bc8...9945ddf8675d
To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications
More information about the All-commits
mailing list